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AIDA-2020 TLU - Gateware
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AIDA-2020 TLU - Gateware
Commits
1a2c5d0f
Commit
1a2c5d0f
authored
Feb 12, 2014
by
David Cussans
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Specifying VHDL as prefered language in setup_workspace.tcl
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setup_project.tcl
config/ise14/sp601/setup_project.tcl
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config/ise14/sp601/setup_project.tcl
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1a2c5d0f
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@@ -8,6 +8,7 @@ project set "Enable Multi-Threading" "2" -process "Map"
project set
"Pack I/O Registers/Latches into IOBs"
"For Inputs and Outputs"
-process
"Map"
project set
"Enable Multi-Threading"
"2"
-process
"Place & Route"
project set
"Enable BitStream Compression"
TRUE -process
"Generate Programming File"
project set
"Preferred Language"
"VHDL"
# source $::env(REPOS_FW_DIR
)
/firmware/example_designs/scripts/addfiles.tcl
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