Review layout by BE-CO team
Question A Add text: “https://www.ohwr.org/project/fmc-dio-10i-8o” so
that people can find the design files.
Answer A Indeed, the link to the projects is missing. It will be added
on the top overlay.
B: Is the multi-pin connector not too far to the back?
B: The FCS8 will be placed as close as possible to the board edge.
C: Front-panel: Text marked “IC2 bus” -> “I2C bus”.
C: FP will have proper marking, along with TOP and BOT
D: Would the name on front panel be easier to read with fmc dio-10i-8o
instead of fmc dio10i8o? (Possibly the same on the PCB, on the Top
Overlay).
D: Most probably. If no other name than FMC DIO 10I8O, the suggested
separation will allow easier reading.
E: Why is 3D picture tilted? Ask it to be straight.
E: Indeed.
F: Is it nowadays possible to have a 3D pdf file (that one can rotate
from within an Adobe reader)?
F: It will be asked or done manually.
G: Do not mount TP1 and TP2 (both are visible: strange, in BOM TP1 is
mounted, TP2 not).
G: TP1 allows easy connection with GND, it will be mounted.
H: - Some components are rather close to edge PCB (IC14, IC26, C22)
H: I am not sure we can make something about it, but I will check with
the designer
I: - Add text: “https://www.ohwr.org/project/fmc-dio-10i-8o” so that
people can find the design files.
I: See A)
J: - What is pin near IC10? (the other end of TP1 or TP2?)
J: Yes, it is the other part of TP2
K: - Is the multi-pin connector not too far to the back? I’m worried that if the front-panel is mounted, you cannot plug anything in. Could it not be moved to fit inside the front-panel? Make a prototype of front-panel before producing PCBs?
K: If I understood well, you are worried of an impossible plug in once the FMC is plugged (on FMC slot) and the front panel is put on it? I asked to change the entrance wideness also for the front panel, to me the FCS8 it is not too far on the back: http://suddendocs.samtec.com/prints/fcf8-xx-xx-x-xx.xx-s-x-mkt.pdf its mate (FCF8) is reasonably long. The front panel could be made thinner also.
L: Most non-mounted components are to make the hysteresis? They really
need not to be mounted now? Possibly ask DEM to make a V1-1 with the
components for the hysteresis mounted.
L: It is on its way, there will be 2 executions
M: - Bottom overlay: IC1E has text inside: NT1E. Remove this text
M: Indeed, I am going to ask why, otherwise it does not belong here
N: Possibly add markers for place of serial number sticker.
N: Good idea! I will see with the designer
O: PCB drill page reads: “All vias 0.2mm hole diameter must be Filled
and Capped Holes.”. But it points only to the holes under ICs and not
“all 0.2mm vias” (which would be 878 holes).
O: Probably bad description, it should be written “all connected vias”,
it is in the attached .png
P: What does the **** point to for this line? “Filled and Capped Vias:
YES ****/*”
P: I must admit that I do not know, I am going to ask. I thought it
was some internal communication
Q: Text marked “IC2 bus” -> “I2C bus”
Q: See C)
R: Should there be a marker for pin 1, or top side of connector?
R: I don’t follow you here, could you explain a bit for me?
S: Take care of Asymetry” -> Asymmetry, What is size marked 101.8?
Cannot be in mm.
S: In which file do you see that?
T: Remove text: “This drawing may not be used …” and “Ce dessin ne peut
être …”. After all, it is Open Hardware. Add the CERN OHL text (same
as used on schematics).
T: Yes, I think they add automatically this text, I only saw the pdf
when they sent me the draft for this front panel. I am going to ask for
a change here.
U: Would the name be easier to read with fmc dio-10i-8o instead of fmc
dio10i8o? (Possibly the same on the PCB, on the Top Overlay)
U: See D
V: Licence texts on each page mix V1.1 and V1.2 of CERN OHL version.
Make all V1.2. (note that each text should contain 3 times V1.2)
V: I copied it, and did not realise that 1.1 was repeated more than one,
shame on me !
W: LEDs on the front-panel are marked IN and OUT. Add to schematics
which one is IN and which one OUT.
W: I am going to change that point. It will be more logical.
X: On page 6 is marked: “TCA9539 has been preferred”. But I don’t see
it, nor in the BOM.
X: The component arrived later than the rest, but has not been
implemented, hence the legacy. The text will be removed.
Y: Supervisor circuit MAX16043TG+. We’ve had some problems where we
suspect the supervisor circuit gave us troubles as it reset the rest of
the circuit in a hard-wired way. If yours may give similar problems, Is
it possible to switch off the supervisor part via the FMC
connector/FPGA?
Y: Sadly, the DAC requires the power supplies to be timed. It is not
possible to switch off this component with the FPGA.
Z: Is it correct that TCA6416APWR (page 6) VCCP is P3V3? Should it not
be P3V3AUX, like its power pins?
Z: Yes, it is normal. We wanted to avoid to block SCL/SDA if P3V3 is
unpowered.
AA: On many places the signal names overlap the pin number of an IC
AA: I will try to brush it up
BB: The three 4.7uF capacitors could not be replaced by 10uF of which
you already have 6?
BB: For the P7V0, there are 2 locations where I need a capacitor,
however I will exceed the recommended value for the regulators.
CC: Do not mount TP1 and TP2 (strange, in BOM TP1 Is mounted, TP2 not)
CC: See G)
DD: What about the TCA9539?
DD: See W)