FMC DIO 10I8O
Project description
The FMC DIO 10i8o is an I/O card in FMC form-factor. This card uses a
low-pint count (LPC) connector.
It's 10 inputs use fast differential comparators (propagation delay < 1
ns) with 12-bit DAC to set references. The 8 outputs are LVTTL level.
There exist two interfaces for the FCS8 connector, one Patch-panel and one Breakout-board.
Other FMC projects and the FMC standard are described in FMC Projects .
Main features
- FMC low-pin count (LPC)
- Supported Vadj 1.8V and 2.5V
- FMC connectivity: all 34 differential pairs connected, I2C
- Inputs
- 10 x high speed input channels with 2 comparators per channel (to measure risetime or positive and negative thresholds)
- input levels: +-5V nominal (tolerated 15V during 5us)
- Programmable threshold: +-5V using DAC with 12bit precision (DAC7716SFPB)
- Input bandwidth: 350MHz
- Selectable: High-impedance (10kOhm) or 50 Ohm
- Outputs:
- 8 x digital LVTTL
- 2 x isolated contact for PLC fail-safe functionality
- Connectivity
- Front SAMTEC FCS8-20-01-L-S-A-TR connector
- Optional 2-pin Lemo 00 connector (LEMO EPG.00.302.NLN) for external I2C bus -> can be used as general purpose I2C master
- Comparators
- 5 x LMH7324SQ/NOPB Quad high speed comparator
- Number of comparators: 20 (2 per input channel)
- Voltage references/thresholds: 20 (1 per comparator)
- Communication with FPGA: LVDS, 1 pair per channel
- ID, memory
- Unique 64-bit identifier, 1.8V and one-wire compatible (DS2411R+)
- 64 kbit EEPROM connected for storing application parameters (24AA64T-I/MC)
- I2C TMP101 card temperature surveillance
Project information
- Patch panel is described in this page: Patch-panel and available on EDMS
- Breakout board is described on Breakout-board and available on EDA-03341-V1
PCB versions
Working versions
-
EDA-03287-V5
- studies launched end 2021, to solve below problems and in addition cope with electronics components shortage
- see also CERN internal https://gitlab.cern.ch/abt-projects/electronics/eda-03287-v5/-/blob/master/readme.md#changes-wrt-v4
- produced and tested Q2 2022, all good
-
EDA-03287-V4
- Modifications required for proper operation:
- To get rid of the N12V0 100mV ripple, place the not-mounted C1 capacitor of 150pF. This will render the LM2611 (IC2) feedback loop stable.
- About 20% of the V4 cards have a too high ripple for the N2V9 rail, change R19 from 10k to 15k for all.
- IC18_IC has its D1 (pin10) and D2 (pin9) pins floating because of a not-connected via, undetected by Altium (problem might be on previous versions as well!). When activating Ch4 and Ch5 50 Ohm termination, both channels will be electrically connected! Solder a small wire between the via and the neighbouring GND pad. Bug reported
- Modifications wrt V3:
- OUTS_EN_n signal added to ensure outputs at high-impedance during configuration/powering
- wired to MAX9122, not fully working as expected; should use OEn input from 74LVC2244 drivers instead
- doubled output drivers for higher output voltage when terminated in 50 Ohms (now 2.4V)
- unintended swap of last 4 output signals (out 4-5-6-7 wired to 7-6-5-4)!
- output ESD protection (TVS) added
- all comparator LVDS termination resistors now at 470 Ohms
- DAC RC filter improved for more precise 1/4 division; equivalent resistance matching for comparator bias currents compensation
- SPI test pads added
- N2V9 rail resistor changed to 10k for stability
- corrected i2c note
- i2c temperature sensors added
- N2V5 base resistor added to reduce HF noise (110mV -> 30mV)
- P4V5 HF noise reduced by adding 10uF+100nF+1nF caps
- P2V5 buck PCB improved; 1nf input cap added
- lemo-00 is now mounted optionally
- netname N2V5 changed to N2V9
- replace NDS331 by FDN327 (due to availability)
- OUTS_EN_n signal added to ensure outputs at high-impedance during configuration/powering
- Modifications required for proper operation:
-
EDA-03287-V3
- Modifications required for proper operation:
- For a stable N2V9 supply rail, change R19 from 3.9k to 10k.
- (Above V4 via problem might theoretically be possible as well, though not seen at production)
- Modifications wrt V2:
- main change: LMH7322SQ comparator changed to LMH7324SQ to allow Vin,diff > 1.2V
- LMH7324 Vcci from 7V to 4.5V
- LMH7324 Vee from -5V to -2.5V
- all hysteresis components removed
- 200 ohm lvds resistors changed to 470 ohm
- MAX160 sequencer:
- P2V5 EN pin linked to shdn_poss because otherwise regulator is powered too quickly and powering FPGA bank before Vcco
- added PG_C2M dependency for clean start-up - shdn_poss really needed then?
- why is the P4V5 rail sequenced? Cause on V1 schematics this rail powered the DAC reference (P5V0), changed on V2 to P12V0 though. Properly fixed on V5, see higher
- negative supplies: inductances changed to IHLP2525CZER100M01
- several others.. to be documented/copied from DFS spreadsheet
- main change: LMH7322SQ comparator changed to LMH7324SQ to allow Vin,diff > 1.2V
- Modifications required for proper operation:
Development versions
- Several components were changed on EDA-03287-V2 to make it
functional, so there's now an unofficial EDA-03287-V2.1
- EDA-03287-V21
- Documentation of the FMC DIO10I8O V2 is available on EDA-03287-V2
- Documentation of the FMC DIO10I8O V1 is available on EDA-03287-V1
- Schematics, second draft
- Schematics, first draft
- Hysteresis calculation and simulation
Production Test Suite
An automated test procedure exists, see https://wikis.cern.ch/display/TEABT/FMC+DIO+10i+8o+Automatic+tester (CERN internal for now, to be published here)
Contacts
- Pieter Van Trappen
Project
Commercial producers
- none
Project Status
Date | Event |
---|---|
02-06-2015 | First ideas for the I/O card. |
27-07-2015 | Creation of Open Hardware project, selection of connector and fast comparator. |
04-09-2015 | Design specification: Bandwidth, I/O levels, DAC choice |
08-09-2015 | First schematics and reviewing process |
02-11-2015 | Schematics, first draft available |
06-11-2015 | Review with BE-CO team and its corrections |
24-11-2015 | Schematics, second draft available |
26-11-2015 | Review of the PCB-layout from BE/CO department |
02-12-2015 | Schematics sent to CERN design office for PCB layout |
28-01-2016 | FMC V1 in production |
25-02-2016 | Breakout board created |
21-03-2016 | VDHL code writing process started |
27-04-2016 | Reception of two FMC V1 prototypes, beginning of hardware and software tests |
25-07-2016 | Patch panel sent to production |
01-09-2016 | FMC V2 required because problems with LMH7324 availability and incorrect power supply components |
16-09-2016 | FMC V2 with new schematics and new layout |
20-10-2016 | Production of 6x FMC V2 samples |
20-01-2017 | designer Simon has left CERN, Pieter taking over |
10-08-2017 | Production launch of pre-series: 12x FMC V3 |
10-10-2017 | Pre-series arrived, tests ongoing - so far so good |
2019 | Production of 50x V4 done |
17-12-2021 | CERN BE-OP needs 24 cards (+6 for ABT), launch V5 design with small corrections |
17-06-2022 | Production of 30x V5 done |