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Tomasz Wlostowski authored
hdl/top/svec: slot order according to the front panel. SDB addresses in ascending order. Fixed wrong WR Core SDB bridge address.
a989eb86
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svec_fine_delay.xise |
hdl/top/svec: slot order according to the front panel. SDB addresses in ascending order. Fixed wrong WR Core SDB bridge address.
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svec_fine_delay.xise | Loading commit data... |