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doc/manual/ffpg_core.htm
View file @ 0578698f
......@@ -955,7 +955,7 @@ Control register
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">ad9512_start_config</td>
<td class="td_field" colspan="1">ad9512_spi_override</td>
<td class="td_field" colspan="1">fine_delay_enable</td>
<td class="td_field" colspan="1">ad9512_sync</td>
......@@ -993,11 +993,13 @@ Control register
<dt><b>led_test</b> [<i>rw</i>]</dt>
<dd>LED test<br><br>If set to 1, all LEDs on the FFPG front panel will be blinking.</dd>
<dt><b>ad9512_sync</b> [<i>rw</i>]</dt>
<dd>AD9512 Synchronization<br><br>When written with 1 AD9512 dividers synchronization is performed.<br>It automatically clear to 0.</dd>
<dd>AD9512 synchronization<br><br>When written with 1 AD9512 dividers synchronization is performed.<br>It automatically clear to 0.</dd>
<dt><b>fine_delay_enable</b> [<i>rw</i>]</dt>
<dd>AD9512 OUT4 fine delay enable<br><br>If set to 1, fine delay on OUT4 output of AD9512 is enabled.<br>Fine delay itself can be set in a separate register.</dd>
<dt><b>ad9512_spi_override</b> [<i>rw</i>]</dt>
<dd>Override automatic AD9512 configuration by WB-SPI access<br><br>If set to 1, the AD9512 SPI port is connected to the WB-SPI bridge.<br>Otherwise, the automatic configuration block is connected to the AD9512 SPI.</dd>
<dt><b>ad9512_start_config</b> [<i>rw</i>]</dt>
<dd>AD9512 start configuration<br><br>When written with 1 AD9512 configuration is programmed to the device.<br>It automatically clear to 0.</dd>
</dl>
<a name="csr.vcxo_voltage"></a>
<h3>2.10. csr.vcxo_voltage</h3>
......@@ -1128,11 +1130,7 @@ Clock ratio-1 register
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="5">ext[4:0]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
......@@ -1174,6 +1172,8 @@ Clock ratio-1 register
<dl>
<dt><b>value</b> [<i>rw</i>]</dt>
<dd>Clock ratio-1</dd>
<dt><b>ext</b> [<i>rw</i>]</dt>
<dd>Clock ratio-1 (for external output)</dd>
</dl>
<a name="csr.ch1_delay_set"></a>
<h3>2.12. csr.ch1_delay_set</h3>
......
hdl/ffpg/cheby/Makefile
View file @ 0578698f
......@@ -9,14 +9,17 @@ SIM=../sim/testbench
.PHONY: all
all: $(RTL)/ffpg_core_regs.vhd \
$(DOC)/ffpg_core.htm \
$(SIM)/ffpg_csr.svh
$(DOC)/ffpg_core.htm \
$(SIM)/ffpg_csr.svh
$(RTL)/ffpg_core_regs.vhd: ffpg_csr.cheby onewire_master.cheby spi_master.cheby
$(DOC)/ffpg_core.htm: ffpg_csr.cheby onewire_master.cheby spi_master.cheby
$(RTL)/%_regs.vhd: %.cheby
$(CHEBY) --hdl vhdl --gen-hdl $@ --header=commit --input $^
$(CHEBY) --hdl vhdl --gen-hdl $@ --header=commit --input $<
$(DOC)/%.htm: %.cheby
$(CHEBY) --doc html --gen-doc $@ --input $^
$(CHEBY) --doc html --gen-doc $@ --input $<
$(SIM)/%.svh: %.cheby
$(CHEBY) --consts-style=verilog --gen-consts $@ --header=commit --input $^
$(CHEBY) --consts-style=verilog --gen-consts $@ --header=commit --input $<
hdl/ffpg/cheby/ffpg_csr.cheby
View file @ 0578698f
......@@ -136,7 +136,7 @@ memory-map:
range: 8
- field:
name: ad9512_sync
description: AD9512 Synchronization
description: AD9512 synchronization
comment: |-
When written with 1 AD9512 dividers synchronization is performed.
It automatically clear to 0.
......@@ -157,6 +157,15 @@ memory-map:
If set to 1, the AD9512 SPI port is connected to the WB-SPI bridge.
Otherwise, the automatic configuration block is connected to the AD9512 SPI.
range: 11
- field:
name: ad9512_start_config
description: AD9512 start configuration
comment: |-
When written with 1 AD9512 configuration is programmed to the device.
It automatically clear to 0.
range: 12
x-hdl:
type: autoclear
- reg:
name: vcxo_voltage
description: VCXO voltage register
......@@ -191,6 +200,10 @@ memory-map:
name: value
description: Clock ratio-1
range: 4-0
- field:
name: ext
description: Clock ratio-1 (for external output)
range: 20-16
- reg:
name: ch1_delay_set
description: SET delay configuration (channel 1)
......@@ -363,8 +376,6 @@ memory-map:
width: 32
access: rw
address: 0x3c
x-hdl:
write-strobe: True
children:
- field:
name: value
......
hdl/ffpg/rtl/Ad9512Control.vhd
View file @ 0578698f
......@@ -53,6 +53,7 @@ entity Ad9512Control is
ClockSelection_i: in std_logic; -- 0 - CLK1, 1 - CLK2
ClockRatioMinus1_ib: in std_logic_vector(4 downto 0);
ClockRatioMinus1Ext_ib: in std_logic_vector(4 downto 0);
FineDelayEnable_i: in std_logic;
FineDelay_ib: in std_logic_vector(4 downto 0);
FineDelayCurrent_ib: in std_logic_vector(2 downto 0);
......@@ -93,6 +94,7 @@ architecture syn of Ad9512Control is
signal ClockSelection: std_logic := '0';
signal ClockRatioMinus1_b: unsigned(ClockRatioMinus1_ib'range) := to_unsigned(1-1, ClockRatioMinus1_ib'length);
signal ClockRatioMinus1Ext_b: unsigned(ClockRatioMinus1Ext_ib'range) := to_unsigned(1-1, ClockRatioMinus1Ext_ib'length);
signal FineDelayEnable: std_logic := '0';
signal FineDelay_b: unsigned(FineDelay_ib'range) := to_unsigned(0, FineDelay_ib'length);
signal FineDelayCurrent_b: unsigned(FineDelayCurrent_ib'range) := to_unsigned(0, FineDelayCurrent_ib'length);
......@@ -152,6 +154,8 @@ architecture syn of Ad9512Control is
return Bypass & NoSync & ForceState & StartHL & PhaseOffset;
end function;
signal ClockRatioMinus1Dis_b: unsigned(4 downto 0) := "00000";
------------------------------------------------------------------------
-- SPI core config
------------------------------------------------------------------------
......@@ -222,6 +226,7 @@ begin
if Cfg_i = '1' then
ClockSelection <= ClockSelection_i;
ClockRatioMinus1_b <= unsigned(ClockRatioMinus1_ib);
ClockRatioMinus1Ext_b <= unsigned(ClockRatioMinus1Ext_ib);
FineDelayEnable <= FineDelayEnable_i;
FineDelay_b <= unsigned(FineDelay_ib);
FineDelayCurrent_b <= unsigned(FineDelayCurrent_ib);
......@@ -240,17 +245,17 @@ begin
-- select CLK1 input, power down CLK2 input
(X"45", if_slv(ClockSelection = '1', X"02", X"05")),
-- output frequency 200 MHz (divide by 2)
(X"4a", f_CreateDivideReg1(ClockRatioMinus1_b)), -- OUT0
(X"4c", f_CreateDivideReg1(ClockRatioMinus1_b)), -- OUT1
(X"4e", f_CreateDivideReg1(ClockRatioMinus1_b)), -- OUT2
(X"50", f_CreateDivideReg1(ClockRatioMinus1_b)), -- OUT3
(X"52", f_CreateDivideReg1(ClockRatioMinus1_b)), -- OUT4
(X"4a", f_CreateDivideReg1(ClockRatioMinus1_b)), -- OUT0 (outputs)
(X"4c", f_CreateDivideReg1(ClockRatioMinus1Ext_b)), -- OUT1 (ext)
(X"4e", f_CreateDivideReg1(ClockRatioMinus1Dis_b)), -- OUT2
(X"50", f_CreateDivideReg1(ClockRatioMinus1_b)), -- OUT3 (FPGA 1)
(X"52", f_CreateDivideReg1(ClockRatioMinus1_b)), -- OUT4 (FPGA 2)
-- phase 0
(X"4b", f_CreateDivideReg2(ClockRatioMinus1_b)), -- OUT0
(X"4d", f_CreateDivideReg2(ClockRatioMinus1_b)), -- OUT1
(X"4f", f_CreateDivideReg2(ClockRatioMinus1_b)), -- OUT2
(X"51", f_CreateDivideReg2(ClockRatioMinus1_b)), -- OUT3
(X"53", f_CreateDivideReg2(ClockRatioMinus1_b)), -- OUT4
(X"4b", f_CreateDivideReg2(ClockRatioMinus1_b)), -- OUT0 (outputs)
(X"4d", f_CreateDivideReg2(ClockRatioMinus1Ext_b)), -- OUT1 (ext)
(X"4f", f_CreateDivideReg2(ClockRatioMinus1Dis_b)), -- OUT2
(X"51", f_CreateDivideReg2(ClockRatioMinus1_b)), -- OUT3 (FPGA 1)
(X"53", f_CreateDivideReg2(ClockRatioMinus1_b)), -- OUT4 (FPGA 2)
-- function pin as sync
(X"58", X"20"),
-- confirm write
......
hdl/ffpg/rtl/FfpgCore.vhd
View file @ 0578698f
......@@ -110,8 +110,7 @@ architecture syn of FfpgCore is
signal LedSignal_b: std_logic_vector(4 downto 1);
signal Ad9512ClockSelectionChanged, Ad9512FineDelayEnableChanged: std_logic;
signal Ad9512ClockSelection, Ad9512StartConfig: std_logic;
signal Ad9512ClockSelection: std_logic;
signal Ad9512SyncePulse: std_logic;
-- Wishbone regs
......@@ -320,29 +319,6 @@ begin
'0' when WbRegsOutput.csr_control_clock_selection = "01" else -- SY58017: FPGA LOOP
'1'; -- SY58017: VCXO
cAd9512ClockSelectionChange: entity work.ChangeDetector(syn)
port map (
Clk_ik => Clk_ik,
Signal_ib => WbRegsOutput.csr_control_clock_selection,
Change_o => Ad9512ClockSelectionChanged
);
cAd9512FineDelayEnableChange: entity work.EdgeDetector(both)
port map (
Clk_ik => Clk_ik,
Signal_i => WbRegsOutput.csr_control_fine_delay_enable,
Edge_o => Ad9512FineDelayEnableChanged
);
Ad9512StartConfig <=
Ad9512ClockSelectionChanged or
WbRegsOutput.csr_clock_ratio_m1_wr or
Ad9512FineDelayEnableChanged or
(
WbRegsOutput.csr_fine_delay_wr
and WbRegsOutput.csr_control_fine_delay_enable
);
cAd9512Control: entity work.Ad9512Control(syn)
generic map (
g_ClkFrequency => g_ClkFrequency
......@@ -351,11 +327,12 @@ begin
Clk_ik => Clk_ik,
Reset_ir => Reset_r,
Cfg_i => Ad9512StartConfig,
Cfg_i => WbRegsOutput.csr_control_ad9512_start_config,
Busy_o => WbRegsInput.csr_status_clock_infrastructure_busy,
ClockSelection_i => Ad9512ClockSelection,
ClockRatioMinus1_ib => WbRegsOutput.csr_clock_ratio_m1_value,
ClockRatioMinus1Ext_ib => WbRegsOutput.csr_clock_ratio_m1_ext,
FineDelayEnable_i => WbRegsOutput.csr_control_fine_delay_enable,
FineDelay_ib => WbRegsOutput.csr_fine_delay_value,
FineDelayCurrent_ib => WbRegsOutput.csr_fine_delay_current,
......
hdl/ffpg/rtl/ffpg_core_regs.vhd
View file @ 0578698f
......@@ -19,9 +19,11 @@ package ffpg_core_regs_pkg is
csr_control_ad9512_sync : std_logic;
csr_control_fine_delay_enable : std_logic;
csr_control_ad9512_spi_override : std_logic;
csr_control_ad9512_start_config : std_logic;
csr_vcxo_voltage_value : std_logic_vector(15 downto 0);
csr_vcxo_voltage_wr : std_logic;
csr_clock_ratio_m1_value : std_logic_vector(4 downto 0);
csr_clock_ratio_m1_ext : std_logic_vector(4 downto 0);
csr_clock_ratio_m1_wr : std_logic;
csr_ch1_delay_set_value : std_logic_vector(9 downto 0);
csr_ch1_delay_set_wr : std_logic;
......@@ -42,7 +44,6 @@ package ffpg_core_regs_pkg is
csr_fine_delay_value : std_logic_vector(4 downto 0);
csr_fine_delay_current : std_logic_vector(2 downto 0);
csr_fine_delay_capacitors : std_logic_vector(2 downto 0);
csr_fine_delay_wr : std_logic;
csr_ch1_set_mem_data_dat_o : std_logic_vector(31 downto 0);
csr_ch1_res_mem_data_dat_o : std_logic_vector(31 downto 0);
csr_ch2_set_mem_data_dat_o : std_logic_vector(31 downto 0);
......@@ -143,6 +144,7 @@ architecture syn of ffpg_core_regs is
signal csr_control_ad9512_sync_reg : std_logic;
signal csr_control_fine_delay_enable_reg : std_logic;
signal csr_control_ad9512_spi_override_reg : std_logic;
signal csr_control_ad9512_start_config_reg : std_logic;
signal csr_control_wreq : std_logic;
signal csr_control_wack : std_logic;
signal csr_vcxo_voltage_value_reg : std_logic_vector(15 downto 0);
......@@ -150,6 +152,7 @@ architecture syn of ffpg_core_regs is
signal csr_vcxo_voltage_wack : std_logic;
signal csr_vcxo_voltage_wstrb : std_logic;
signal csr_clock_ratio_m1_value_reg : std_logic_vector(4 downto 0);
signal csr_clock_ratio_m1_ext_reg : std_logic_vector(4 downto 0);
signal csr_clock_ratio_m1_wreq : std_logic;
signal csr_clock_ratio_m1_wack : std_logic;
signal csr_clock_ratio_m1_wstrb : std_logic;
......@@ -190,7 +193,6 @@ architecture syn of ffpg_core_regs is
signal csr_fine_delay_capacitors_reg : std_logic_vector(2 downto 0);
signal csr_fine_delay_wreq : std_logic;
signal csr_fine_delay_wack : std_logic;
signal csr_fine_delay_wstrb : std_logic;
signal csr_ch1_set_mem_data_int_dato : std_logic_vector(31 downto 0);
signal csr_ch1_set_mem_data_ext_dat : std_logic_vector(31 downto 0);
signal csr_ch1_set_mem_data_rreq : std_logic;
......@@ -378,6 +380,7 @@ begin
csr_regs_o.csr_control_ad9512_sync <= csr_control_ad9512_sync_reg;
csr_regs_o.csr_control_fine_delay_enable <= csr_control_fine_delay_enable_reg;
csr_regs_o.csr_control_ad9512_spi_override <= csr_control_ad9512_spi_override_reg;
csr_regs_o.csr_control_ad9512_start_config <= csr_control_ad9512_start_config_reg;
csr_control_wack <= csr_control_wreq;
process (clk_i) begin
if rising_edge(clk_i) then
......@@ -391,6 +394,7 @@ begin
csr_control_ad9512_sync_reg <= '0';
csr_control_fine_delay_enable_reg <= '0';
csr_control_ad9512_spi_override_reg <= '0';
csr_control_ad9512_start_config_reg <= '0';
else
if csr_control_wreq = '1' then
csr_control_clock_selection_reg <= wr_dat_d0(1 downto 0);
......@@ -402,8 +406,10 @@ begin
csr_control_ad9512_sync_reg <= wr_dat_d0(9);
csr_control_fine_delay_enable_reg <= wr_dat_d0(10);
csr_control_ad9512_spi_override_reg <= wr_dat_d0(11);
csr_control_ad9512_start_config_reg <= wr_dat_d0(12);
else
csr_control_ad9512_sync_reg <= '0';
csr_control_ad9512_start_config_reg <= '0';
end if;
end if;
end if;
......@@ -429,15 +435,18 @@ begin
-- Register csr_clock_ratio_m1
csr_regs_o.csr_clock_ratio_m1_value <= csr_clock_ratio_m1_value_reg;
csr_regs_o.csr_clock_ratio_m1_ext <= csr_clock_ratio_m1_ext_reg;
csr_clock_ratio_m1_wack <= csr_clock_ratio_m1_wreq;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
csr_clock_ratio_m1_value_reg <= "00000";
csr_clock_ratio_m1_ext_reg <= "00000";
csr_clock_ratio_m1_wstrb <= '0';
else
if csr_clock_ratio_m1_wreq = '1' then
csr_clock_ratio_m1_value_reg <= wr_dat_d0(4 downto 0);
csr_clock_ratio_m1_ext_reg <= wr_dat_d0(20 downto 16);
end if;
csr_clock_ratio_m1_wstrb <= csr_clock_ratio_m1_wreq;
end if;
......@@ -606,18 +615,15 @@ begin
csr_fine_delay_value_reg <= "00000";
csr_fine_delay_current_reg <= "000";
csr_fine_delay_capacitors_reg <= "000";
csr_fine_delay_wstrb <= '0';
else
if csr_fine_delay_wreq = '1' then
csr_fine_delay_value_reg <= wr_dat_d0(4 downto 0);
csr_fine_delay_current_reg <= wr_dat_d0(7 downto 5);
csr_fine_delay_capacitors_reg <= wr_dat_d0(10 downto 8);
end if;
csr_fine_delay_wstrb <= csr_fine_delay_wreq;
end if;
end if;
end process;
csr_regs_o.csr_fine_delay_wr <= csr_fine_delay_wstrb;
-- Memory csr_ch1_set_mem
process (adr_int, wr_adr_d0, csr_ch1_set_mem_wr) begin
......@@ -997,19 +1003,19 @@ begin
csr_control_ch2_mode_reg, csr_control_led_test_reg,
csr_control_fine_delay_enable_reg,
csr_control_ad9512_spi_override_reg, csr_vcxo_voltage_value_reg,
csr_clock_ratio_m1_value_reg, csr_ch1_delay_set_value_reg,
csr_ch1_delay_reset_value_reg, csr_ch2_delay_set_value_reg,
csr_ch2_delay_reset_value_reg, csr_trigger_threshold_value_reg,
csr_overflow_value_reg, csr_ch1_trigger_latency_value_reg,
csr_regs_i.csr_frequency, csr_regs_i.csr_debug,
csr_regs_i.csr_version_revision, csr_regs_i.csr_version_minor,
csr_regs_i.csr_version_major, csr_ch2_trigger_latency_value_reg,
csr_fine_delay_value_reg, csr_fine_delay_current_reg,
csr_fine_delay_capacitors_reg, csr_ch1_set_mem_data_int_dato,
csr_ch1_set_mem_data_rack, csr_ch1_res_mem_data_int_dato,
csr_ch1_res_mem_data_rack, csr_ch2_set_mem_data_int_dato,
csr_ch2_set_mem_data_rack, csr_ch2_res_mem_data_int_dato,
csr_ch2_res_mem_data_rack) begin
csr_clock_ratio_m1_value_reg, csr_clock_ratio_m1_ext_reg,
csr_ch1_delay_set_value_reg, csr_ch1_delay_reset_value_reg,
csr_ch2_delay_set_value_reg, csr_ch2_delay_reset_value_reg,
csr_trigger_threshold_value_reg, csr_overflow_value_reg,
csr_ch1_trigger_latency_value_reg, csr_regs_i.csr_frequency,
csr_regs_i.csr_debug, csr_regs_i.csr_version_revision,
csr_regs_i.csr_version_minor, csr_regs_i.csr_version_major,
csr_ch2_trigger_latency_value_reg, csr_fine_delay_value_reg,
csr_fine_delay_current_reg, csr_fine_delay_capacitors_reg,
csr_ch1_set_mem_data_int_dato, csr_ch1_set_mem_data_rack,
csr_ch1_res_mem_data_int_dato, csr_ch1_res_mem_data_rack,
csr_ch2_set_mem_data_int_dato, csr_ch2_set_mem_data_rack,
csr_ch2_res_mem_data_int_dato, csr_ch2_res_mem_data_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
onewire_master_re <= '0';
......@@ -1056,7 +1062,8 @@ begin
rd_dat_d0(9) <= '0';
rd_dat_d0(10) <= csr_control_fine_delay_enable_reg;
rd_dat_d0(11) <= csr_control_ad9512_spi_override_reg;
rd_dat_d0(31 downto 12) <= (others => '0');
rd_dat_d0(12) <= '0';
rd_dat_d0(31 downto 13) <= (others => '0');
when "00000000010" =>
-- Reg csr_vcxo_voltage
rd_ack_d0 <= rd_req_int;
......@@ -1066,7 +1073,9 @@ begin
-- Reg csr_clock_ratio_m1
rd_ack_d0 <= rd_req_int;
rd_dat_d0(4 downto 0) <= csr_clock_ratio_m1_value_reg;
rd_dat_d0(31 downto 5) <= (others => '0');
rd_dat_d0(15 downto 5) <= (others => '0');
rd_dat_d0(20 downto 16) <= csr_clock_ratio_m1_ext_reg;
rd_dat_d0(31 downto 21) <= (others => '0');
when "00000000100" =>
-- Reg csr_ch1_delay_set
rd_ack_d0 <= rd_req_int;
......
hdl/ffpg/sim/testbench/ffpg_csr.svh
View file @ 0578698f
......@@ -76,6 +76,10 @@
`define FFPG_CSR_CONTROL_AD9512_SPI_OVERRIDE_WIDTH 1
`define FFPG_CSR_CONTROL_AD9512_SPI_OVERRIDE_OFFSET 11
`define FFPG_CSR_CONTROL_AD9512_SPI_OVERRIDE 'h800
`define ADDR_FFPG_CSR_CONTROL_AD9512_START_CONFIG 'h4
`define FFPG_CSR_CONTROL_AD9512_START_CONFIG_WIDTH 1
`define FFPG_CSR_CONTROL_AD9512_START_CONFIG_OFFSET 12
`define FFPG_CSR_CONTROL_AD9512_START_CONFIG 'h1000
`define ADDR_FFPG_CSR_VCXO_VOLTAGE 'h8
`define ADDR_FFPG_CSR_VCXO_VOLTAGE_VALUE 'h8
`define FFPG_CSR_VCXO_VOLTAGE_VALUE_WIDTH 16
......@@ -86,6 +90,10 @@
`define FFPG_CSR_CLOCK_RATIO_M1_VALUE_WIDTH 5
`define FFPG_CSR_CLOCK_RATIO_M1_VALUE_OFFSET 0
`define FFPG_CSR_CLOCK_RATIO_M1_VALUE 'h1f
`define ADDR_FFPG_CSR_CLOCK_RATIO_M1_EXT 'hc
`define FFPG_CSR_CLOCK_RATIO_M1_EXT_WIDTH 5
`define FFPG_CSR_CLOCK_RATIO_M1_EXT_OFFSET 16
`define FFPG_CSR_CLOCK_RATIO_M1_EXT 'h1f0000
`define ADDR_FFPG_CSR_CH1_DELAY_SET 'h10
`define ADDR_FFPG_CSR_CH1_DELAY_SET_VALUE 'h10
`define FFPG_CSR_CH1_DELAY_SET_VALUE_WIDTH 10
......
hdl/top/spec/cheby/Makefile
View file @ 0578698f
......@@ -9,4 +9,4 @@ RTL=..
all: $(RTL)/spec_top_ffpg_map.vhd
$(RTL)/%.vhd: %.cheby
$(CHEBY) --hdl vhdl --gen-hdl $@ --header=commit --input $^
$(CHEBY) --hdl vhdl --gen-hdl $@ --header=commit --input $<
hdl/top/svec/cheby/Makefile
View file @ 0578698f
......@@ -9,4 +9,4 @@ RTL=..
all: $(RTL)/svec_top_ffpg_map.vhd
$(RTL)/%.vhd: %.cheby
$(CHEBY) --hdl vhdl --gen-hdl $@ --header=commit --input $^
$(CHEBY) --hdl vhdl --gen-hdl $@ --header=commit --input $<