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doc/manual/ffpg_core.htm 0 → 100644
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doc/manual/ffpg_csr.htm deleted 100644 → 0
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doc/manual/svec/carrier_csr.htm deleted 100644 → 0
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hdl/ffpg/cheby/Makefile 0 → 100644
View file @ df8eeb6c
# SPDX-FileCopyrightText: 2024 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0+ OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
CHEBY=cheby
RTL=../rtl
DOC=../../../doc/manual
SIM=../sim/testbench
.PHONY: all
all: $(RTL)/ffpg_core_regs.vhd \
$(DOC)/ffpg_core.htm \
$(SIM)/ffpg_csr.svh
$(RTL)/%_regs.vhd: %.cheby
$(CHEBY) --hdl vhdl --gen-hdl $@ --header=commit --input $^
$(DOC)/%.htm: %.cheby
$(CHEBY) --doc html --gen-doc $@ --input $^
$(SIM)/%.svh: %.cheby
$(CHEBY) --consts-style=verilog --gen-consts $@ --header=commit --input $^
hdl/ffpg/cheby/ffpg_core.cheby 0 → 100644
View file @ df8eeb6c
# SPDX-FileCopyrightText: 2024 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0+ OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: ffpg_core
description: FMC DEL 1ns 2cha core registers
bus: wb-32-be
size: 0x20000
x-hdl:
busgroup: true
name-suffix: _regs
children:
- submap:
name: onewire_master
description: OneWire master
address: 0x1000
include: False
filename: onewire_master.cheby
- submap:
name: spi_master
description: WB SPI master
address: 0x2000
include: False
filename: spi_master.cheby
- submap:
name: csr
description: Control/status registers
address: 0x10000
include: True
filename: ffpg_csr.cheby
hdl/ffpg/cheby/ffpg_csr.cheby 0 → 100644
View file @ df8eeb6c
# SPDX-FileCopyrightText: 2024 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0+ OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: ffpg_csr
description: FMC DEL 1ns 2cha control and status registers
bus: wb-32-be
x-hdl:
busgroup: true
iogroup: csr_regs
children:
- reg:
name: status
description: Status register
width: 32
access: ro
address: 0x0
children:
- field:
name: clock_infrastructure_busy
description: Clock infrastructure configuration in progress
comment: |-
Status of the clock infrastructure configuration
0: configuration done
1: configuration in progress
range: 0
- field:
name: dac_vcxo_busy
description: VCXO DAC busy
comment: |-
Status of the VCXO DAC communication
0: DAC idle, value already set
1: DAC busy, communication in progress
range: 1
- field:
name: dac_trigger_busy
description: Trigger DAC busy
comment: |-
Status of the trigger DAC communication
0: DAC idle, value already set
1: DAC busy, communication in progress
range: 2
- field:
name: delay_configuration_busy
description: Delay configuration in progress
comment: |-
Status of the delay configuration
0: configuration done
1: configuration in progress
range: 3
- field:
name: channel_1_oe
description: Channel 1 output enabled
comment: |-
Channel 1 output enabled
0: output disabled
1: output enabled
range: 4
- field:
name: channel_2_oe
description: Channel 2 output enabled
comment: |-
Channel 2 output enabled
0: output disabled
1: output enabled
range: 5
- field:
name: channel_1_running
description: Pulse generator channel 1 running
comment: |-
Pulse generator channel 1 running
0: channel 1 is not running
1: channel 1 is running, pulses are generated
range: 6
- field:
name: channel_2_running
description: Pulse generator channel 2 running
comment: |-
Pulse generator channel 2 running
0: channel 2 is not running
1: channel 2 is running, pulses are generated
range: 7
- field:
name: input_clock_stable
description: Input clock stable
comment: |-
Indicates the stability of the input clock.
0: input clock not present or not stable
1: input clock present and stable
range: 8
- reg:
name: control
description: Control register
width: 32
access: rw
address: 0x4
children:
- field:
name: clock_selection
description: Clock source selection
comment: |-
0 (default): external clock used (connector on the front panel)
1: FPGA loop clock used
2: on-board VCXO clock used
range: 1-0
- field:
name: ch1_oe
description: CH1 output enable
range: 2
- field:
name: ch2_oe
description: CH2 output enable
range: 3
- field:
name: ch1_mode
description: CH1 mode selection
comment: |-
0 (default): stopped (no output generated)
1: continuous (non-stop memory looping)
2: one-shot (loop memory just once)
range: 5-4
- field:
name: ch2_mode
description: CH2 mode selection
comment: |-
0 (default): stopped (no output generated)
1: continuous (non-stop memory looping)
2: one-shot (loop memory just once)
range: 7-6
- field:
name: led_test
description: LED test
comment: |-
If set to 1, all LEDs on the FFPG front panel will be blinking.
range: 8
- field:
name: ad9512_sync
description: AD9512 Synchronization
comment: |-
When written with 1 AD9512 dividers synchronization is performed.
It automatically clear to 0.
range: 9
x-hdl:
type: autoclear
- field:
name: fine_delay_enable
description: AD9512 OUT4 fine delay enable
comment: |-
If set to 1, fine delay on OUT4 output of AD9512 is enabled.
Fine delay itself can be set in a separate register.
range: 10
- field:
name: ad9512_spi_override
description: Override automatic AD9512 configuration by WB-SPI access
comment: |-
If set to 1, the AD9512 SPI port is connected to the WB-SPI bridge.
Otherwise, the automatic configuration block is connected to the AD9512 SPI.
range: 11
- reg:
name: vcxo_voltage
description: VCXO voltage register
comment: |-
This register value D determines output voltage of the VCXO DAC.
Voltage should be V_OUT = D * 5 / 65536 [V] (see datasheet), but is limited by 3.3 V supply voltage of the DAC.
width: 32
access: rw
address: 0x8
x-hdl:
write-strobe: True
children:
- field:
name: value
description: VCXO voltage register value
range: 15-0
- reg:
name: clock_ratio_m1
description: Clock ratio-1 register
comment: |-
Clock ratio specifies the frequency of the serial stream clock generated by the AD9512 clock divider:
f_generated = f_input / (RATIO+1).
This ratio is used for all clocks generated on the FMC card.
Permitted values are 0-31 which renders to actual ratio 1-32.
width: 32
access: rw
address: 0xc
x-hdl:
write-strobe: True
children:
- field:
name: value
description: Clock ratio-1
range: 4-0
- reg:
name: ch1_delay_set
description: SET delay configuration (channel 1)
comment: |-
10 bit fine delay for pulse generation - delay of the SET pulse, i.e. CH1 pulse delay
width: 32
access: rw
address: 0x10
x-hdl:
write-strobe: True
children:
- field:
name: value
description: CH1 SET delay
range: 9-0
- reg:
name: ch1_delay_reset
description: RES delay configuration (channel 1)
comment: |-
10 bit fine delays for pulse generation - delay of the RES pulse, i.e. CH1 pulse width
width: 32
access: rw
address: 0x14
x-hdl:
write-strobe: True
children:
- field:
name: value
description: CH1 RES delay
range: 9-0
- reg:
name: ch2_delay_set
description: SET delay configuration (channel 2)
comment: |-
10 bit fine delay for pulse generation - delay of the SET pulse, i.e. CH2 pulse delay
width: 32
access: rw
address: 0x18
x-hdl:
write-strobe: True
children:
- field:
name: value
description: CH2 SET delay
range: 9-0
- reg:
name: ch2_delay_reset
description: RES delay configuration (channel 2)
comment: |-
10 bit fine delays for pulse generation - delay of the RES pulse, i.e. CH2 pulse width
width: 32
access: rw
address: 0x1c
x-hdl:
write-strobe: True
children:
- field:
name: value
description: CH2 RES delay
range: 9-0
- reg:
name: trigger_threshold
description: Trigger threshold voltage register
comment: |-
This register value D determines output voltage of the trigger threshold DAC.
Voltage should be V_OUT = D * 5 / 65536 [V] (see datasheet).
width: 32
access: rw
address: 0x20
x-hdl:
write-strobe: True
children:
- field:
name: value
description: Trigger threshold voltage register value
range: 15-0
- reg:
name: overflow
description: Overflow
comment: |-
Overflow index for serial stream memory.
When this index is reach when looping the memory, memory index is reset back to 0.
width: 32
access: rw
address: 0x24
x-hdl:
write-strobe: True
children:
- field:
name: value
description: Overflow value
range: 15-0
- reg:
name: ch1_trigger_latency
description: Trigger latency (channel 1)
comment: |-
The latency of the trigger in number of clock cycles of the serial stream clock, for channel 1.
When trigger is received, serial stream memory pointer is set to this value.
width: 32
access: rw
address: 0x28
x-hdl:
write-strobe: True
children:
- field:
name: value
description: Trigger latency value
range: 15-0
- reg:
name: frequency
description: Clock frequency
comment: |-
Frequency of the input clock in Hz.
width: 32
access: ro
address: 0x2c
- reg:
name: debug
description: Debug register
comment: |-
For internal use only, do not use!
width: 32
access: ro
address: 0x30
- reg:
name: version
description: Gateware version
comment: |-
Version of the current gateware in form of major.minor.revision
width: 32
access: ro
address: 0x34
children:
- field:
name: revision
description: Revision
range: 11-0
- field:
name: minor
description: Minor version
range: 21-12
- field:
name: major
description: Major version
range: 31-22
- reg:
name: ch2_trigger_latency
description: Trigger latency (channel 2)
comment: |-
The latency of the trigger in number of clock cycles of the serial stream clock, for channel 2.
When trigger is received, serial stream memory pointer is set to this value.
width: 32
access: rw
address: 0x38
x-hdl:
write-strobe: True
children:
- field:
name: value
description: Trigger latency value
range: 15-0
- reg:
name: fine_delay
description: AD9512 OUT4 fine delay
comment: |-
Value of the AD9512 OUT4 output fine delay.
The actual delay applied to the OUT4 output has an offset,
i.e. it is non-zero even when zero is written to this register
(when the fine delay is enabled - see the status register for the enable bit).
width: 32
access: rw
address: 0x3c
x-hdl:
write-strobe: True
children:
- field:
name: value
description: AD9512 OUT4 fine delay value
range: 4-0
- field:
name: current
description: Ramp current
range: 7-5
- field:
name: capacitors
description: Ramp capacitors
range: 10-8
- memory:
name: ch1_set_mem
description: CH1 SET serial stream
address: 0x2000
memsize: 8192
x-hdl:
dual-clock: true
children:
- reg:
name: data
width: 32
access: rw
- memory:
name: ch1_res_mem
description: CH1 RES serial stream
address: 0x4000
memsize: 8192
x-hdl:
dual-clock: true
children:
- reg:
name: data
width: 32
access: rw
- memory:
name: ch2_set_mem
description: CH2 SET serial stream
address: 0x6000
memsize: 8192
x-hdl:
dual-clock: true
children:
- reg:
name: data
width: 32
access: rw
- memory:
name: ch2_res_mem
description: CH2 RES serial stream
address: 0x8000
memsize: 8192
x-hdl:
dual-clock: true
children:
- reg:
name: data
width: 32
access: rw
hdl/ffpg/cheby/onewire_master.cheby 0 → 100644
View file @ df8eeb6c
# SPDX-FileCopyrightText: 2024 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0+ OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: onewire_master
description: Onewire master registers
bus: wb-32-be
x-hdl:
busgroup: true
children:
- reg:
name: ctrl_sta
description: Control/status register
width: 32
access: rw
address: 0x0
- reg:
name: cdr
description: Clock dividers register
width: 32
access: rw
address: 0x4
hdl/ffpg/cheby/spi_master.cheby 0 → 100644
View file @ df8eeb6c
# SPDX-FileCopyrightText: 2024 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0+ OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: spi_master
description: SPI master registers
bus: wb-32-be
x-hdl:
busgroup: true
children:
- reg:
name: status
description: Status register
width: 32
access: ro
address: 0x0
- reg:
name: config1
description: Config 1 register
width: 32
access: rw
address: 0x4
- reg:
name: config2
description: Config 2 register
width: 32
access: rw
address: 0x8
- reg:
name: shift_out
description: Shift out register
width: 32
access: rw
address: 0xc
- reg:
name: shift_in
description: Shift in register
width: 32
access: ro
address: 0x10
hdl/ffpg/rtl/Ad9512Control.vhd
View file @ df8eeb6c
......@@ -52,11 +52,11 @@ entity Ad9512Control is
Busy_o: out std_logic;
ClockSelection_i: in std_logic; -- 0 - CLK1, 1 - CLK2
ClockRatioMinus1_ib: in unsigned(4 downto 0);
ClockRatioMinus1_ib: in std_logic_vector(4 downto 0);
FineDelayEnable_i: in std_logic;
FineDelay_ib: in unsigned(4 downto 0);
FineDelayCurrent_ib: in unsigned(2 downto 0);
FineDelayCapacitors_ib: in unsigned(2 downto 0);
FineDelay_ib: in std_logic_vector(4 downto 0);
FineDelayCurrent_ib: in std_logic_vector(2 downto 0);
FineDelayCapacitors_ib: in std_logic_vector(2 downto 0);
SpiAd9512Sclk_o: out std_logic;
SpiAd9512Mosi_o: out std_logic;
......@@ -221,11 +221,11 @@ begin
if rising_edge(Clk_ik) then
if Cfg_i = '1' then
ClockSelection <= ClockSelection_i;
ClockRatioMinus1_b <= ClockRatioMinus1_ib;
ClockRatioMinus1_b <= unsigned(ClockRatioMinus1_ib);
FineDelayEnable <= FineDelayEnable_i;
FineDelay_b <= FineDelay_ib;
FineDelayCurrent_b <= FineDelayCurrent_ib;
FineDelayCapacitors_b <= FineDelayCapacitors_ib;
FineDelay_b <= unsigned(FineDelay_ib);
FineDelayCurrent_b <= unsigned(FineDelayCurrent_ib);
FineDelayCapacitors_b <= unsigned(FineDelayCapacitors_ib);
end if;
end if;
end process;
......
hdl/ffpg/rtl/DacsController.vhd
View file @ df8eeb6c
......@@ -44,9 +44,9 @@ entity DacsController is
port (
Clk_ik: in std_logic;
Reset_ir: in std_logic;
TriggerValue_ib16: in unsigned(15 downto 0);
TriggerValue_ib16: in std_logic_vector(15 downto 0);
TriggerLoad_i: in std_logic;
VcxoValue_ib16: in unsigned(15 downto 0);
VcxoValue_ib16: in std_logic_vector(15 downto 0);
VcxoLoad_i: in std_logic;
TriggerDac_o: out t_Ad5600Interface;
VcxoDac_o: out t_Ad5600Interface;
......@@ -108,7 +108,7 @@ begin
port map (
clk_i => Clk_ik,
rst_n_i => Reset_nr,
value_i => std_logic_vector(TriggerValue_ib16),
value_i => TriggerValue_ib16,
cs_sel_i(0) => TriggerDacEn,
load_i => TriggerDacEn,
sclk_divsel_i => c_SclkDivsel,
......@@ -128,7 +128,7 @@ begin
port map (
clk_i => Clk_ik,
rst_n_i => Reset_nr,
value_i => std_logic_vector(VcxoValue_ib16),
value_i => VcxoValue_ib16,
cs_sel_i(0) => VcxoDacEn,
load_i => VcxoDacEn,
sclk_divsel_i => c_SclkDivsel,
......
hdl/ffpg/rtl/DelayController.vhd
View file @ df8eeb6c
......@@ -42,15 +42,15 @@ entity DelayController is
port (
Clk_ik: in std_logic;
Reset_ir: in std_logic;
Ch1SetValue_ib: in unsigned(9 downto 0);
Ch1SetValue_ib: in std_logic_vector(9 downto 0);
Ch1SetValueLoad_i: in std_logic;
Ch1ResValue_ib: in unsigned(9 downto 0);
Ch1ResValue_ib: in std_logic_vector(9 downto 0);
Ch1ResValueLoad_i: in std_logic;
Ch2SetValue_ib: in unsigned(9 downto 0);
Ch2SetValue_ib: in std_logic_vector(9 downto 0);
Ch2SetValueLoad_i: in std_logic;
Ch2ResValue_ib: in unsigned(9 downto 0);
Ch2ResValue_ib: in std_logic_vector(9 downto 0);
Ch2ResValueLoad_i: in std_logic;
DelayValue_ob: out unsigned(9 downto 0);
DelayValue_ob: out std_logic_vector(9 downto 0);
Ch1SetLe_on: out std_logic;
Ch1ResLe_on: out std_logic;
Ch2SetLe_on: out std_logic;
......
hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd
View file @ df8eeb6c
......@@ -45,15 +45,15 @@ entity DelayedPulseGenerator is
Clk_ik: in std_logic;
Reset_ir: in std_logic;
-- WB interface
Overflow_ib16: in unsigned(15 downto 0);
TriggerLatency_ib16: in unsigned(15 downto 0);
Overflow_ib16: in std_logic_vector(15 downto 0);
TriggerLatency_ib16: in std_logic_vector(15 downto 0);
Mode_i: in t_Mode;
ModeLoad_i: in std_logic;
SetMemAddress_ob11: out unsigned(10 downto 0);
SetMemData_ib32: in unsigned(31 downto 0);
SetMemAddress_ob11: out std_logic_vector(10 downto 0);
SetMemData_ib32: in std_logic_vector(31 downto 0);
SetMemReadStrobe_o: out std_logic;
ResMemAddress_ob11: out unsigned(10 downto 0);
ResMemData_ib32: in unsigned(31 downto 0);
ResMemAddress_ob11: out std_logic_vector(10 downto 0);
ResMemData_ib32: in std_logic_vector(31 downto 0);
ResMemReadStrobe_o: out std_logic;
Running_o: out std_logic;
-- FMC interface
......@@ -61,7 +61,7 @@ entity DelayedPulseGenerator is
SetStream_o: out std_logic := '0';
ResetStream_o: out std_logic := '0';
-- debug
FsmState_o: out unsigned(2 downto 0)
FsmState_o: out std_logic_vector(2 downto 0)
);
end entity;
......@@ -74,9 +74,12 @@ architecture syn of DelayedPulseGenerator is
constant c_MemLatency: integer := 2+1;
-- +1 for memory output registers implemented here
signal Overflow_b16: unsigned(Overflow_ib16'range) := (others => '0');
signal TriggerLatency_b16: unsigned(TriggerLatency_ib16'range) := (others => '0');
-- for memory output registers
signal SetMemData_b32: unsigned(SetMemData_ib32'range) := (others => '0');
signal ResMemData_b32: unsigned(ResMemData_ib32'range) := (others => '0');
signal SetMemData_b32: std_logic_vector(SetMemData_ib32'range) := (others => '0');
signal ResMemData_b32: std_logic_vector(ResMemData_ib32'range) := (others => '0');
signal LastStreamPosition: unsigned(Overflow_ib16'range) := (others => '0');
signal TriggerLatencyPlusTwo: unsigned(TriggerLatency_ib16'range) := (others => '0');
......@@ -102,6 +105,9 @@ architecture syn of DelayedPulseGenerator is
begin
Overflow_b16 <= unsigned(Overflow_ib16);
TriggerLatency_b16 <= unsigned(TriggerLatency_ib16);
-- memory output registers
pMemOutputReg: process(Clk_ik) is begin
if rising_edge(Clk_ik) then
......@@ -113,8 +119,8 @@ begin
-- for better timing
pInputReg: process(Clk_ik) is begin
if rising_edge(Clk_ik) then
LastStreamPosition <= Overflow_ib16 - 1;
TriggerLatencyPlusTwo <= TriggerLatency_ib16 + 2;
LastStreamPosition <= Overflow_b16 - 1;
TriggerLatencyPlusTwo <= TriggerLatency_b16 + 2;
-- +1 because of ???
-- +1 because of output registers on Set/ResetStream_o
end if;
......@@ -176,8 +182,8 @@ begin
Value_ob => AddressCounterValue
);
SetMemAddress_ob11 <= AddressCounterValue;
ResMemAddress_ob11 <= AddressCounterValue;
SetMemAddress_ob11 <= std_logic_vector(AddressCounterValue);
ResMemAddress_ob11 <= std_logic_vector(AddressCounterValue);
SetMemReadStrobe_o <= '0'; -- this is not connected anywhere!!
ResMemReadStrobe_o <= '0'; -- this is not connected anywhere!!
......@@ -185,7 +191,7 @@ begin
-- for better timing
pStreamResetReg: process(Clk_ik) is begin
if rising_edge(Clk_ik) then
if StreamPosition = Overflow_ib16 - 2 then
if StreamPosition = Overflow_b16 - 2 then
StreamReset <= '1';
else
StreamReset <= '0';
......
hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGeneratorFsm.vhd
View file @ df8eeb6c
......@@ -53,7 +53,7 @@ entity DelayedPulseGeneratorFsm is
GenerationEnable_o: out std_logic := '0';
OutputEnable_o: out std_logic := '0';
-- debug
State_o: out unsigned(2 downto 0)
State_o: out std_logic_vector(2 downto 0)
);
end entity;
......@@ -134,6 +134,6 @@ begin
end case;
end process;
State_o <= f_State2Unsigned(State);
State_o <= std_logic_vector(f_State2Unsigned(State));
end architecture;
hdl/ffpg/rtl/DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd
View file @ df8eeb6c
......@@ -48,23 +48,23 @@ entity DelayedPulseGeneratorsCdc is
-- trigger
Trigger_i: in std_logic;
-- configuration (WB)
Ch1SetMemAddress_ob11: out unsigned(10 downto 0);
Ch1SetMemData_ib32: in unsigned(31 downto 0);
Ch1SetMemAddress_ob11: out std_logic_vector(10 downto 0);
Ch1SetMemData_ib32: in std_logic_vector(31 downto 0);
Ch1SetMemReadStrobe_o: out std_logic;
Ch1ResMemAddress_ob11: out unsigned(10 downto 0);
Ch1ResMemData_ib32: in unsigned(31 downto 0);
Ch1ResMemAddress_ob11: out std_logic_vector(10 downto 0);
Ch1ResMemData_ib32: in std_logic_vector(31 downto 0);
Ch1ResMemReadStrobe_o: out std_logic;
Ch2SetMemAddress_ob11: out unsigned(10 downto 0);
Ch2SetMemData_ib32: in unsigned(31 downto 0);
Ch2SetMemAddress_ob11: out std_logic_vector(10 downto 0);
Ch2SetMemData_ib32: in std_logic_vector(31 downto 0);
Ch2SetMemReadStrobe_o: out std_logic;
Ch2ResMemAddress_ob11: out unsigned(10 downto 0);
Ch2ResMemData_ib32: in unsigned(31 downto 0);
Ch2ResMemAddress_ob11: out std_logic_vector(10 downto 0);
Ch2ResMemData_ib32: in std_logic_vector(31 downto 0);
Ch2ResMemReadStrobe_o: out std_logic;
Overflow_ib16: in unsigned(15 downto 0);
Overflow_ib16: in std_logic_vector(15 downto 0);
OverflowLoad_i: in std_logic;
Ch1TriggerLatency_ib16: in unsigned(15 downto 0);
Ch1TriggerLatency_ib16: in std_logic_vector(15 downto 0);
Ch1TriggerLatencyLoad_i: in std_logic;
Ch2TriggerLatency_ib16: in unsigned(15 downto 0);
Ch2TriggerLatency_ib16: in std_logic_vector(15 downto 0);
Ch2TriggerLatencyLoad_i: in std_logic;
Ch1Mode_i: in t_Mode;
Ch1Running_o: out std_logic;
......@@ -77,16 +77,13 @@ entity DelayedPulseGeneratorsCdc is
Ch2SetStream_o: out std_logic;
Ch2ResetStream_o: out std_logic;
-- debug
Ch1FsmState_o: out unsigned(2 downto 0);
Ch2FsmState_o: out unsigned(2 downto 0)
Ch1FsmState_o: out std_logic_vector(2 downto 0);
Ch2FsmState_o: out std_logic_vector(2 downto 0)
);
end entity;
architecture syn of DelayedPulseGeneratorsCdc is
signal Overflow_b_slv, OverflowRf_b_slv: std_logic_vector(Overflow_ib16'range) := (others => '0');
signal Ch1TriggerLatency_b_slv, Ch1TriggerLatencyRf_b_slv: std_logic_vector(Ch1TriggerLatency_ib16'range) := (others => '0');
signal CH2TriggerLatency_b_slv, Ch2TriggerLatencyRf_b_slv: std_logic_vector(Ch2TriggerLatency_ib16'range) := (others => '0');
signal Ch1Mode_slv, Ch1ModeRf_slv: std_logic_vector(1 downto 0);
signal Ch1ModeLoad: std_logic;
signal Ch2Mode_slv, Ch2ModeRf_slv: std_logic_vector(1 downto 0);
......@@ -97,9 +94,9 @@ architecture syn of DelayedPulseGeneratorsCdc is
signal TriggerRf, TriggerRfPulse: std_logic;
signal Ch1RunningRf: std_logic;
signal Ch2RunningRf: std_logic;
signal OverflowRf_b: unsigned(Overflow_ib16'range);
signal Ch1TriggerLatencyRf_b: unsigned(Ch1TriggerLatency_ib16'range);
signal Ch2TriggerLatencyRf_b: unsigned(Ch2TriggerLatency_ib16'range);
signal OverflowRf_b: std_logic_vector(Overflow_ib16'range);
signal Ch1TriggerLatencyRf_b: std_logic_vector(Ch1TriggerLatency_ib16'range);
signal Ch2TriggerLatencyRf_b: std_logic_vector(Ch2TriggerLatency_ib16'range);
signal Ch1ModeRf: t_Mode;
signal Ch1ModeLoadRf: std_logic;
signal Ch2ModeRf: t_Mode;
......@@ -139,52 +136,40 @@ begin
-- Overflow
Overflow_b_slv <= std_logic_vector(Overflow_ib16);
cOverflowSyncer: entity work.RegSyncer(syn)
port map (
ClkIn_ik => Clk_ik,
ClkOut_ik => ClkRf_ik,
Data_ib => Overflow_b_slv,
Data_ib => Overflow_ib16,
Load_i => OverflowLoad_i,
Data_ob => OverflowRf_b_slv,
Data_ob => OverflowRf_b,
Load_o => open
);
OverflowRf_b <= unsigned(OverflowRf_b_slv);
-- Ch1TriggerLatency
Ch1TriggerLatency_b_slv <= std_logic_vector(Ch1TriggerLatency_ib16);
cCh1TriggerLatencySyncer: entity work.RegSyncer(syn)
port map (
ClkIn_ik => Clk_ik,
ClkOut_ik => ClkRf_ik,
Data_ib => Ch1TriggerLatency_b_slv,
Data_ib => Ch1TriggerLatency_ib16,
Load_i => Ch1TriggerLatencyLoad_i,
Data_ob => Ch1TriggerLatencyRf_b_slv,
Data_ob => Ch1TriggerLatencyRf_b,
Load_o => open
);
Ch1TriggerLatencyRf_b <= unsigned(Ch1TriggerLatencyRf_b_slv);
-- Ch2TriggerLatency
Ch2TriggerLatency_b_slv <= std_logic_vector(Ch2TriggerLatency_ib16);
cCh2TriggerLatencySyncer: entity work.RegSyncer(syn)
port map (
ClkIn_ik => Clk_ik,
ClkOut_ik => ClkRf_ik,
Data_ib => Ch2TriggerLatency_b_slv,
Data_ib => Ch2TriggerLatency_ib16,
Load_i => Ch2TriggerLatencyLoad_i,
Data_ob => Ch2TriggerLatencyRf_b_slv,
Data_ob => Ch2TriggerLatencyRf_b,
Load_o => open
);
Ch2TriggerLatencyRf_b <= unsigned(Ch2TriggerLatencyRf_b_slv);
-- Ch1Mode
Ch1Mode_slv <= f_ModeToSlv(Ch1Mode_i);
......
hdl/ffpg/rtl/FfpgCore.vhd
View file @ df8eeb6c
This diff is collapsed.
hdl/ffpg/rtl/FfpgCoreWrapper.vhd
View file @ df8eeb6c
......@@ -64,7 +64,7 @@ entity FfpgCoreWrapper is
Ch1OutputEnable_o: out std_logic;
Ch2OutputEnable_o: out std_logic;
-- delay configuration
DelayValue_ob: out unsigned(9 downto 0);
DelayValue_ob: out std_logic_vector(9 downto 0);
Ch1SetLe_on: out std_logic;
Ch1ResLe_on: out std_logic;
Ch2SetLe_on: out std_logic;
......@@ -106,7 +106,7 @@ architecture sp6 of FfpgCoreWrapper is
-- for differentials outputs
signal Ch1Set, Ch1Res, Ch2Set, Ch2Res: std_logic;
signal ClkOutDdr, ClkOut_k: std_logic;
signal ClkOutDdr, ClkOut_k, ClkOut_nk: std_logic;
begin
......@@ -206,6 +206,8 @@ begin
OB => Ch2ResN_o
);
ClkOut_nk <= not ClkOut_k;
cClkOutOddr: ODDR2
generic map(
DDR_ALIGNMENT => "C0",
......@@ -214,7 +216,7 @@ begin
port map (
Q => ClkOutDdr,
C0 => ClkOut_k,
C1 => not ClkOut_k,
C1 => ClkOut_nk,
CE => '1',
D0 => '1',
D1 => '0',
......
hdl/ffpg/rtl/FfpgPkg.vhd
View file @ df8eeb6c
......@@ -58,27 +58,6 @@ package FfpgPkg is
e_ModeSingle
);
-- FFPG SDB description
constant c_FfpgSdbDevice: t_sdb_device := (
abi_class => x"0000",
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32 bit granularity
sdb_component => (
addr_first => x"0000_0000_0000_0000",
addr_last => x"0000_0000_0000_ffff",
product => (
vendor_id => x"0000_0000_0000_CE42",
device_id => x"3f76563f",
version => x"00000001",
date => x"20160725",
name => "WB-FFPG pulse gen. ")));
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_FfpgBridgeSdb: t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001_ffff", x"0000_0000");
function f_ModeToSlv(Mode: t_Mode) return std_logic_vector;
function f_SlvToMode(Slv: std_logic_vector(1 downto 0)) return t_Mode;
......
hdl/ffpg/rtl/FfpgSlave.vhd deleted 100644 → 0
View file @ 641d61cb
This diff is collapsed.
hdl/ffpg/rtl/FrequencySense.vhd
View file @ df8eeb6c
......@@ -47,7 +47,7 @@ entity FrequencySense is
port (
Clk_ik: in std_logic;
SenseClk_ik: in std_logic;
SenseFrequency_ob: out unsigned(g_SenseFrequencyWidth-1 downto 0);
SenseFrequency_ob: out std_logic_vector(g_SenseFrequencyWidth-1 downto 0);
SenseFrequencyStable_o: out std_logic -- clock stable and present (f > 0)
);
end entity;
......@@ -112,7 +112,7 @@ begin
end if;
end process;
SenseFrequency_ob <= SenseFrequency_b;
SenseFrequency_ob <= std_logic_vector(SenseFrequency_b);
-- clock stability
......
hdl/ffpg/rtl/Manifest.py
View file @ df8eeb6c
files = [
"ffpg_csr.vhd",
"ffpg_csr_pkg.vhd",
"ffpg_core_regs.vhd",
"FfpgCore.vhd",
"FfpgCoreWrapper.vhd",
"FfpgPkg.vhd",
"FfpgSlave.vhd",
"Ad9512Control.vhd",
"Ad9512Syncer.vhd",
"ChangeDetector.vhd",
......@@ -26,5 +24,4 @@ files = [
"ShiftRegister.vhd",
"SlowToggle.vhd",
"SpiMasterWb.v",
"WbSlaveWrapper.vhd",
]