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hdl/ffpg/cheby/Makefile
View file @ df8eeb6c
......@@ -2,18 +2,21 @@
#
# SPDX-License-Identifier: CC-BY-SA-4.0+ OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
CHEBY=cheby
RTL=../rtl
DOC=../../../doc/manual
SIM=../sim/testbench
.PHONY: all
all: $(RTL)/ffpg_csr.vhd $(DOC)/ffpg_csr.htm $(SIM)/ffpg_csr.svh
all: $(RTL)/ffpg_core_regs.vhd \
$(DOC)/ffpg_core.htm \
$(SIM)/ffpg_csr.svh
$(RTL)/%.vhd: %.cheby
cheby --hdl vhdl --gen-hdl $@ --header=commit --input $^
$(RTL)/%_regs.vhd: %.cheby
$(CHEBY) --hdl vhdl --gen-hdl $@ --header=commit --input $^
$(DOC)/%.htm: %.cheby
cheby --doc html --gen-doc $@ --input $^
$(CHEBY) --doc html --gen-doc $@ --input $^
$(SIM)/%.svh: %.cheby
cheby --consts-style=verilog --gen-consts $@ --header=commit --input $^
$(CHEBY) --consts-style=verilog --gen-consts $@ --header=commit --input $^
hdl/ffpg/cheby/ffpg_core.cheby 0 → 100644
View file @ df8eeb6c
# SPDX-FileCopyrightText: 2024 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0+ OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: ffpg_core
description: FMC DEL 1ns 2cha core registers
bus: wb-32-be
size: 0x20000
x-hdl:
busgroup: true
name-suffix: _regs
children:
- submap:
name: onewire_master
description: OneWire master
address: 0x1000
include: False
filename: onewire_master.cheby
- submap:
name: spi_master
description: WB SPI master
address: 0x2000
include: False
filename: spi_master.cheby
- submap:
name: csr
description: Control/status registers
address: 0x10000
include: True
filename: ffpg_csr.cheby
hdl/ffpg/cheby/ffpg_csr.cheby
View file @ df8eeb6c
......@@ -4,13 +4,11 @@
memory-map:
name: ffpg_csr
description: FMC DEL 1ns 2cha core registers
comment: Wishbone slave for FMC DEL 1ns 2cha core
description: FMC DEL 1ns 2cha control and status registers
bus: wb-32-be
size: 0x20000
x-hdl:
busgroup: true
iogroup: ffpg_csr_regs
iogroup: csr_regs
children:
- reg:
name: status
......
hdl/ffpg/cheby/onewire_master.cheby 0 → 100644
View file @ df8eeb6c
# SPDX-FileCopyrightText: 2024 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0+ OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: onewire_master
description: Onewire master registers
bus: wb-32-be
x-hdl:
busgroup: true
children:
- reg:
name: ctrl_sta
description: Control/status register
width: 32
access: rw
address: 0x0
- reg:
name: cdr
description: Clock dividers register
width: 32
access: rw
address: 0x4
hdl/ffpg/cheby/spi_master.cheby 0 → 100644
View file @ df8eeb6c
# SPDX-FileCopyrightText: 2024 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0+ OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: spi_master
description: SPI master registers
bus: wb-32-be
x-hdl:
busgroup: true
children:
- reg:
name: status
description: Status register
width: 32
access: ro
address: 0x0
- reg:
name: config1
description: Config 1 register
width: 32
access: rw
address: 0x4
- reg:
name: config2
description: Config 2 register
width: 32
access: rw
address: 0x8
- reg:
name: shift_out
description: Shift out register
width: 32
access: rw
address: 0xc
- reg:
name: shift_in
description: Shift in register
width: 32
access: ro
address: 0x10
hdl/ffpg/rtl/FfpgCore.vhd
View file @ df8eeb6c
This diff is collapsed.
hdl/ffpg/rtl/FfpgCoreWrapper.vhd
View file @ df8eeb6c
......@@ -106,7 +106,7 @@ architecture sp6 of FfpgCoreWrapper is
-- for differentials outputs
signal Ch1Set, Ch1Res, Ch2Set, Ch2Res: std_logic;
signal ClkOutDdr, ClkOut_k: std_logic;
signal ClkOutDdr, ClkOut_k, ClkOut_nk: std_logic;
begin
......@@ -206,6 +206,8 @@ begin
OB => Ch2ResN_o
);
ClkOut_nk <= not ClkOut_k;
cClkOutOddr: ODDR2
generic map(
DDR_ALIGNMENT => "C0",
......@@ -214,7 +216,7 @@ begin
port map (
Q => ClkOutDdr,
C0 => ClkOut_k,
C1 => not ClkOut_k,
C1 => ClkOut_nk,
CE => '1',
D0 => '1',
D1 => '0',
......
hdl/ffpg/rtl/FfpgPkg.vhd
View file @ df8eeb6c
......@@ -58,27 +58,6 @@ package FfpgPkg is
e_ModeSingle
);
-- FFPG SDB description
constant c_FfpgSdbDevice: t_sdb_device := (
abi_class => x"0000",
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32 bit granularity
sdb_component => (
addr_first => x"0000_0000_0000_0000",
addr_last => x"0000_0000_0000_ffff",
product => (
vendor_id => x"0000_0000_0000_CE42",
device_id => x"3f76563f",
version => x"00000001",
date => x"20160725",
name => "WB-FFPG pulse gen. ")));
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_FfpgBridgeSdb: t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001_ffff", x"0000_0000");
function f_ModeToSlv(Mode: t_Mode) return std_logic_vector;
function f_SlvToMode(Slv: std_logic_vector(1 downto 0)) return t_Mode;
......
hdl/ffpg/rtl/FfpgSlave.vhd deleted 100644 → 0
View file @ 25a2ea48
-------------------------------------------------------------------------------
-- Title : FFPG Wishbone slave
-- Project : FMC DEL 1ns 2cha (FFPG)
-- URL : http://www.ohwr.org/projects/fmc-del-1ns-2cha
-------------------------------------------------------------------------------
-- File : FfpgSlave.vhd
-- Author(s) : Jan Pospisil <j.pospisil@cern.ch>
-- Company : CERN (BE-BI-QP)
-- Created : 2016-07-25
-- Last update: 2016-08-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Encapsulates AD5600 DACs controller, MC100EP195 delay
-- controller, two Delayed Pulse Generator cores, clock
-- infrastructure (AD9512 and various clock inputs) configuration,
-- RF clock sense (frequency and stability) and informative LEDs
-- output.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CERN (BE-BI-QP)
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Comment
-- 2016-08-24 1.0 Jan Pospisil
-- 2016-09-01 1.1 Jan Pospisil added version numbers (major.minor.rev)
-- added clock_stable status bit
-- 2016-09-05 1.2 Jan Pospisil Independent Trigger Latency for the two
-- channels (issue 1389)
-- 2016-09-07 1.3 Jan Pospisil added AD9512 OUT4 fine delay
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FfpgPkg.all;
use work.ffpg_csr_pkg.all;
use work.wishbone_pkg.all;
entity FfpgSlave is
generic (
g_ClkFrequency: positive; -- input clock frequency in Hz
g_Version: std_logic_vector(31 downto 0)
);
port (
-- Wishbone connection
Clk_ik: in std_logic;
Reset_ir: in std_logic;
Wb_i: in t_wishbone_slave_in;
Wb_o: out t_wishbone_slave_out;
--- FMC interface
-- clock
ClkIn0_ik: in std_logic;
-- DACs
TriggerDac_o: out t_Ad5600Interface;
VcxoDac_o: out t_Ad5600Interface;
-- output enable
Ch1OutputEnable_o: out std_logic;
Ch2OutputEnable_o: out std_logic;
-- delay configuration
DelayValue_ob: out std_logic_vector(9 downto 0);
Ch1SetLe_on: out std_logic;
Ch1ResLe_on: out std_logic;
Ch2SetLe_on: out std_logic;
Ch2ResLe_on: out std_logic;
--
Ch1Set_o: out std_logic;
Ch1Res_o: out std_logic;
Ch2Set_o: out std_logic;
Ch2Res_o: out std_logic;
Trigger_i: in std_logic;
Clk2Sel_o: out std_logic;
-- LEDs
Led_ob: out std_logic_vector(4 downto 1);
-- AD9512 SPI
SpiAd9512Sclk_o: out std_logic;
SpiAd9512Mosi_o: out std_logic;
SpiAd9512Miso_i: in std_logic;
SpiAd9512Cs_on: out std_logic;
Ad9512SpiOverride_o: out std_logic;
-- AD9512 func. pin
Ad9512Func_o: out std_logic;
-- clock output
ClkOut_ok: out std_logic
);
end entity;
architecture syn of FfpgSlave is
signal ClkRf_k: std_logic;
signal TriggerRf: std_logic;
signal ClkRfStable: std_logic := '0';
signal WbRegsInput: t_ffpg_csr_regs_master_in;
signal WbRegsOutput: t_ffpg_csr_regs_master_out;
signal LedSignal_b: std_logic_vector(4 downto 1);
signal Ad9512ClockSelectionChanged, Ad9512FineDelayEnableChanged: std_logic;
signal Ad9512ClockSelection, Ad9512StartConfig: std_logic;
signal Ad9512SyncePulse: std_logic;
begin
ClkRf_k <= ClkIn0_ik;
----------------------------------
-- Wishbone slave
----------------------------------
cWbSlave: entity work.ffpg_csr(syn)
port map (
rst_n_i => not Reset_ir,
clk_i => Clk_ik,
wb_i => Wb_i,
wb_o => Wb_o,
ffpg_csr_regs_i => WbRegsInput,
ffpg_csr_regs_o => WbRegsOutput
);
----------------------------------
-- DACs
----------------------------------
cDacsController: entity work.DacsController(syn)
generic map (
g_ClkFrequency => g_ClkFrequency
)
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
TriggerValue_ib16 => WbRegsOutput.trigger_threshold_value,
TriggerLoad_i => WbRegsOutput.trigger_threshold_wr,
VcxoValue_ib16 => WbRegsOutput.vcxo_voltage_value,
VcxoLoad_i => WbRegsOutput.vcxo_voltage_wr,
TriggerDac_o => TriggerDac_o,
VcxoDac_o => VcxoDac_o,
TriggerBusy_o => WbRegsInput.status_dac_trigger_busy,
VcxoBusy_o => WbRegsInput.status_dac_vcxo_busy
);
----------------------------------
-- channel delay configuration
----------------------------------
cDelayController: entity work.DelayController(syn)
generic map (
g_ClkFrequency => g_ClkFrequency
)
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Ch1SetValue_ib => WbRegsOutput.ch1_delay_set_value,
Ch1SetValueLoad_i => WbRegsOutput.ch1_delay_set_wr,
Ch1ResValue_ib => WbRegsOutput.ch1_delay_reset_value,
Ch1ResValueLoad_i => WbRegsOutput.ch1_delay_reset_wr,
Ch2SetValue_ib => WbRegsOutput.ch2_delay_set_value,
Ch2SetValueLoad_i => WbRegsOutput.ch2_delay_set_wr,
Ch2ResValue_ib => WbRegsOutput.ch2_delay_reset_value,
Ch2ResValueLoad_i => WbRegsOutput.ch2_delay_reset_wr,
DelayValue_ob => DelayValue_ob,
Ch1SetLe_on => Ch1SetLe_on,
Ch1ResLe_on => Ch1ResLe_on,
Ch2SetLe_on => Ch2SetLe_on,
Ch2ResLe_on => Ch2ResLe_on,
Busy_o => WbRegsInput.status_delay_configuration_busy
);
----------------------------------
-- output enable controls
----------------------------------
Ch1OutputEnable_o <= WbRegsOutput.control_ch1_oe;
Ch2OutputEnable_o <= WbRegsOutput.control_ch2_oe;
WbRegsInput.status_channel_1_oe <= WbRegsOutput.control_ch1_oe;
WbRegsInput.status_channel_2_oe <= WbRegsOutput.control_ch2_oe;
----------------------------------
-- serial stream generators in CDC entity
----------------------------------
cDelayedPulseGeneratorsCdc: entity work.DelayedPulseGeneratorsCdc(syn)
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Trigger_i => Trigger_i,
Ch1SetMemAddress_ob11 => WbRegsInput.ch1_set_mem_adr_i,
Ch1SetMemData_ib32 => WbRegsOutput.ch1_set_mem_data_dat_o,
Ch1SetMemReadStrobe_o => WbRegsInput.ch1_set_mem_data_rd_i,
Ch1ResMemAddress_ob11 => WbRegsInput.ch1_res_mem_adr_i,
Ch1ResMemData_ib32 => WbRegsOutput.ch1_res_mem_data_dat_o,
Ch1ResMemReadStrobe_o => WbRegsInput.ch1_res_mem_data_rd_i,
Ch2SetMemAddress_ob11 => WbRegsInput.ch2_set_mem_adr_i,
Ch2SetMemData_ib32 => WbRegsOutput.ch2_set_mem_data_dat_o,
Ch2SetMemReadStrobe_o => WbRegsInput.ch2_set_mem_data_rd_i,
Ch2ResMemAddress_ob11 => WbRegsInput.ch2_res_mem_adr_i,
Ch2ResMemData_ib32 => WbRegsOutput.ch2_res_mem_data_dat_o,
Ch2ResMemReadStrobe_o => WbRegsInput.ch2_res_mem_data_rd_i,
Overflow_ib16 => WbRegsOutput.overflow_value,
OverflowLoad_i => WbRegsOutput.overflow_wr,
Ch1TriggerLatency_ib16 => WbRegsOutput.ch1_trigger_latency_value,
Ch1TriggerLatencyLoad_i => WbRegsOutput.ch1_trigger_latency_wr,
Ch2TriggerLatency_ib16 => WbRegsOutput.ch2_trigger_latency_value,
Ch2TriggerLatencyLoad_i => WbRegsOutput.ch2_trigger_latency_wr,
Ch1Mode_i => f_SlvToMode(WbRegsOutput.control_ch1_mode),
Ch1Running_o => WbRegsInput.status_channel_1_running,
Ch2Mode_i => f_SlvToMode(WbRegsOutput.control_ch2_mode),
Ch2Running_o => WbRegsInput.status_channel_2_running,
ClkRf_ik => ClkRf_k,
Ch1SetStream_o => Ch1Set_o,
Ch1ResetStream_o => Ch1Res_o,
Ch2SetStream_o => Ch2Set_o,
Ch2ResetStream_o => Ch2Res_o,
Ch1FsmState_o => WbRegsInput.debug(2 downto 0),
Ch2FsmState_o => WbRegsInput.debug(5 downto 3)
);
WbRegsInput.ch1_set_mem_clk_i <= ClkRf_k;
WbRegsInput.ch1_res_mem_clk_i <= ClkRf_k;
WbRegsInput.ch2_set_mem_clk_i <= ClkRf_k;
WbRegsInput.ch2_res_mem_clk_i <= ClkRf_k;
----------------------------------
-- LED outputs
----------------------------------
-- "TRIG IN" LED can only be blinking if ClkRf_k is present
cTriggerSyncer: entity work.Delay(syn)
generic map (
g_Width => 1,
g_Delay => 3,
g_AsyncRegUsed => "TRUE"
)
port map (
Clk_ik => ClkRf_k,
Data_ib(0) => Trigger_i,
Data_ob(0) => TriggerRf
);
-- OUT1 - enabled and running
LedSignal_b(1) <= WbRegsInput.status_channel_1_running and WbRegsOutput.control_ch1_oe;
-- OUT2 - enabled and running
LedSignal_b(2) <= WbRegsInput.status_channel_2_running and WbRegsOutput.control_ch2_oe;
-- TRIG IN
LedSignal_b(3) <= TriggerRf;
-- CLK IN
LedSignal_b(4) <= ClkRfStable;
cSlowToggle: entity work.SlowToggle(behavioral)
generic map (
g_Width => 4,
g_Ticks => g_ClkFrequency/15
)
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Test_i => WbRegsOutput.control_led_test,
Signal_ib => LedSignal_b,
Signal_ob => Led_ob
);
----------------------------------
-- Clock infrastructure
----------------------------------
-- CLOCK_SELECTION [read/write]: Clock source selection
-- 0 (default): external clock used (connector on the front panel)
-- 1: FPGA loop clock used
-- 2: on-board VCXO clock used
Ad9512ClockSelection <=
'0' when WbRegsOutput.control_clock_selection = "00" else -- AD9512: CLK1
'1'; -- AD9512: CLK2
Clk2Sel_o <=
'0' when WbRegsOutput.control_clock_selection = "01" else -- SY58017: FPGA LOOP
'1'; -- SY58017: VCXO
cAd9512ClockSelectionChange: entity work.ChangeDetector(syn)
port map (
Clk_ik => Clk_ik,
Signal_ib => WbRegsOutput.control_clock_selection,
Change_o => Ad9512ClockSelectionChanged
);
cAd9512FineDelayEnableChange: entity work.EdgeDetector(both)
port map (
Clk_ik => Clk_ik,
Signal_i => WbRegsOutput.control_fine_delay_enable,
Edge_o => Ad9512FineDelayEnableChanged
);
Ad9512StartConfig <=
Ad9512ClockSelectionChanged or
WbRegsOutput.clock_ratio_m1_wr or
Ad9512FineDelayEnableChanged or
(
WbRegsOutput.fine_delay_wr
and WbRegsOutput.control_fine_delay_enable
);
cAd9512Control: entity work.Ad9512Control(syn)
generic map (
g_ClkFrequency => g_ClkFrequency
)
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_ir,
Cfg_i => Ad9512StartConfig,
Busy_o => WbRegsInput.status_clock_infrastructure_busy,
ClockSelection_i => Ad9512ClockSelection,
ClockRatioMinus1_ib => WbRegsOutput.clock_ratio_m1_value,
FineDelayEnable_i => WbRegsOutput.control_fine_delay_enable,
FineDelay_ib => WbRegsOutput.fine_delay_value,
FineDelayCurrent_ib => WbRegsOutput.fine_delay_current,
FineDelayCapacitors_ib => WbRegsOutput.fine_delay_capacitors,
SpiAd9512Sclk_o => SpiAd9512Sclk_o,
SpiAd9512Mosi_o => SpiAd9512Mosi_o,
SpiAd9512Miso_i => SpiAd9512Miso_i,
SpiAd9512Cs_on => SpiAd9512Cs_on
);
Ad9512SpiOverride_o <= WbRegsOutput.control_ad9512_spi_override;
cAd9512Syncer: entity work.Ad9512Syncer(syn)
generic map (
g_ClkFrequency => g_ClkFrequency
)
port map (
Clk_ik => Clk_ik,
StartSync_i => WbRegsOutput.control_ad9512_sync,
Trigger_i => Trigger_i,
Ad9512Sync_o => Ad9512SyncePulse
);
Ad9512Func_o <= not Ad9512SyncePulse;
ClkOut_ok <= Clk_ik;
----------------------------------
-- RF frequency sense
----------------------------------
cFrequencySense: entity work.FrequencySense(syn)
generic map (
g_ClkFrequency => g_ClkFrequency,
g_SenseFrequencyWidth => WbRegsInput.frequency'length,
g_SenseFrequencyStableCount => 3,
g_SenseFrequencyStableWidth => 10
)
port map (
Clk_ik => Clk_ik,
SenseClk_ik => ClkRf_k,
SenseFrequency_ob => WbRegsInput.frequency,
SenseFrequencyStable_o => ClkRfStable
);
WbRegsInput.status_input_clock_stable <= ClkRfStable;
----------------------------------
-- debug
----------------------------------
WbRegsInput.debug(31 downto 6) <= (others => '0');
----------------------------------
-- Version information
----------------------------------
WbRegsInput.version_major <= "00" & g_Version(31 downto 24);
WbRegsInput.version_minor <= "00" & g_Version(23 downto 16);
WbRegsInput.version_revision <= g_Version(11 downto 0);
end architecture;
hdl/ffpg/rtl/Manifest.py
View file @ df8eeb6c
files = [
"ffpg_csr.vhd",
"ffpg_core_regs.vhd",
"FfpgCore.vhd",
"FfpgCoreWrapper.vhd",
"FfpgPkg.vhd",
"FfpgSlave.vhd",
"Ad9512Control.vhd",
"Ad9512Syncer.vhd",
"ChangeDetector.vhd",
......
hdl/ffpg/rtl/ffpg_core_regs.vhd 0 → 100644
View file @ df8eeb6c
This diff is collapsed.
hdl/ffpg/rtl/ffpg_csr.vhd deleted 100644 → 0
View file @ 25a2ea48
This diff is collapsed.
hdl/ffpg/sim/testbench/ffpg_csr.svh
View file @ df8eeb6c
// Do not edit. Generated by cheby 1.6.0rc1 using these options:
// --consts-style=verilog --gen-consts ../sim/testbench/ffpg_csr.svh --header=commit --input ffpg_csr.cheby
`define FFPG_CSR_SIZE 131072
`define FFPG_CSR_SIZE 40960
`define ADDR_FFPG_CSR_STATUS 'h0
`define ADDR_FFPG_CSR_STATUS_CLOCK_INFRASTRUCTURE_BUSY 'h0
`define FFPG_CSR_STATUS_CLOCK_INFRASTRUCTURE_BUSY_WIDTH 1
......
hdl/top/spec/cheby/Makefile
View file @ df8eeb6c
......@@ -2,10 +2,11 @@
#
# SPDX-License-Identifier: CC-BY-SA-4.0+ OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
CHEBY=cheby
RTL=..
.PHONY: all
all: $(RTL)/spec_top_ffpg_map.vhd
$(RTL)/%.vhd: %.cheby
cheby --hdl vhdl --gen-hdl $@ --header=commit --input $^
$(CHEBY) --hdl vhdl --gen-hdl $@ --header=commit --input $^
hdl/top/spec/cheby/spec_top_ffpg_map.cheby
View file @ df8eeb6c
......@@ -22,4 +22,4 @@ memory-map:
description: FFPG core 0
address: 0x20000
include: False
filename: ../../../ffpg/cheby/ffpg_csr.cheby
filename: ../../../ffpg/cheby/ffpg_core.cheby
hdl/top/spec/spec_top_ffpg.vhd
View file @ df8eeb6c
......@@ -242,6 +242,7 @@ architecture top of spec_top_ffpg is
-- Clocks & reset
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5 : std_logic := '1';
signal rst_sys_62m5_n : std_logic := '0';
-- Wishbone
......@@ -356,6 +357,8 @@ begin
app_wb_i => master_wb_in
);
rst_sys_62m5 <= not rst_sys_62m5_n;
------------------------------------------------------------------------------
-- Carrier front panel LEDs
------------------------------------------------------------------------------
......@@ -385,7 +388,7 @@ begin
)
port map (
Clk_ik => clk_sys_62m5,
Reset_ira => not rst_sys_62m5_n,
Reset_ira => rst_sys_62m5,
Wb_i => ffpg0_wb_in,
Wb_o => ffpg0_wb_out,
ClkIn0P_ik => Fmc0ClkIn0P_ik,
......
hdl/top/svec/cheby/Makefile
View file @ df8eeb6c
......@@ -2,10 +2,11 @@
#
# SPDX-License-Identifier: CC-BY-SA-4.0+ OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
CHEBY=cheby
RTL=..
.PHONY: all
all: $(RTL)/svec_top_ffpg_map.vhd
$(RTL)/%.vhd: %.cheby
cheby --hdl vhdl --gen-hdl $@ --header=commit --input $^
$(CHEBY) --hdl vhdl --gen-hdl $@ --header=commit --input $^
hdl/top/svec/cheby/svec_top_ffpg_map.cheby
View file @ df8eeb6c
......@@ -22,10 +22,10 @@ memory-map:
description: FFPG core 0
address: 0x20000
include: False
filename: ../../../ffpg/cheby/ffpg_csr.cheby
filename: ../../../ffpg/cheby/ffpg_core.cheby
- submap:
name: ffpg1
description: FFPG core 1
address: 0x60000
include: False
filename: ../../../ffpg/cheby/ffpg_csr.cheby
filename: ../../../ffpg/cheby/ffpg_core.cheby
hdl/top/svec/svec_top_ffpg.vhd
View file @ df8eeb6c
......@@ -319,6 +319,7 @@ architecture top of svec_top_ffpg is
-- Clocks & reset
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5 : std_logic := '1';
signal rst_sys_62m5_n : std_logic := '0';
-- Wishbone
......@@ -455,6 +456,8 @@ begin
app_wb_i => master_wb_in
);
rst_sys_62m5 <= not rst_sys_62m5_n;
------------------------------------------------------------------------------
-- Carrier front panel LEDs and LEMOs
------------------------------------------------------------------------------
......@@ -559,7 +562,7 @@ begin
)
port map (
Clk_ik => clk_sys_62m5,
Reset_ira => not rst_sys_62m5_n,
Reset_ira => rst_sys_62m5,
Wb_i => ffpg0_wb_in,
Wb_o => ffpg0_wb_out,
ClkIn0P_ik => Fmc0ClkIn0P_ik,
......@@ -606,7 +609,7 @@ begin
)
port map (
Clk_ik => clk_sys_62m5,
Reset_ira => not rst_sys_62m5_n,
Reset_ira => rst_sys_62m5,
Wb_i => ffpg1_wb_in,
Wb_o => ffpg1_wb_out,
ClkIn0P_ik => Fmc1ClkIn0P_ik,
......