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doc/manual/ffpg_core.htm
View file @ 17bfcce2
......@@ -160,9 +160,9 @@
<tr class="tr_even">
<td class="td_code">0x10014</td>
<td>REG</td>
<td><A href="#csr.ch1_delay_reset">csr.ch1_delay_reset</a></td>
<td class="td_code">csr_ch1_delay_reset</td>
<td class="td_code">csr.ch1_delay_reset</td>
<td><A href="#csr.ch1_delay_res">csr.ch1_delay_res</a></td>
<td class="td_code">csr_ch1_delay_res</td>
<td class="td_code">csr.ch1_delay_res</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x10018</td>
......@@ -174,16 +174,16 @@
<tr class="tr_even">
<td class="td_code">0x1001c</td>
<td>REG</td>
<td><A href="#csr.ch2_delay_reset">csr.ch2_delay_reset</a></td>
<td class="td_code">csr_ch2_delay_reset</td>
<td class="td_code">csr.ch2_delay_reset</td>
<td><A href="#csr.ch2_delay_res">csr.ch2_delay_res</a></td>
<td class="td_code">csr_ch2_delay_res</td>
<td class="td_code">csr.ch2_delay_res</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x10020</td>
<td>REG</td>
<td><A href="#csr.trigger_threshold">csr.trigger_threshold</a></td>
<td class="td_code">csr_trigger_threshold</td>
<td class="td_code">csr.trigger_threshold</td>
<td><A href="#csr.trig_threshold">csr.trig_threshold</a></td>
<td class="td_code">csr_trig_threshold</td>
<td class="td_code">csr.trig_threshold</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x10024</td>
......@@ -195,9 +195,9 @@
<tr class="tr_odd">
<td class="td_code">0x10028</td>
<td>REG</td>
<td><A href="#csr.ch1_trigger_latency">csr.ch1_trigger_latency</a></td>
<td class="td_code">csr_ch1_trigger_latency</td>
<td class="td_code">csr.ch1_trigger_latency</td>
<td><A href="#csr.ch1_trig_latency">csr.ch1_trig_latency</a></td>
<td class="td_code">csr_ch1_trig_latency</td>
<td class="td_code">csr.ch1_trig_latency</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x1002c</td>
......@@ -223,9 +223,9 @@
<tr class="tr_odd">
<td class="td_code">0x10038</td>
<td>REG</td>
<td><A href="#csr.ch2_trigger_latency">csr.ch2_trigger_latency</a></td>
<td class="td_code">csr_ch2_trigger_latency</td>
<td class="td_code">csr.ch2_trigger_latency</td>
<td><A href="#csr.ch2_trig_latency">csr.ch2_trig_latency</a></td>
<td class="td_code">csr_ch2_trig_latency</td>
<td class="td_code">csr.ch2_trig_latency</td>
</tr>
<tr class="tr_even">
<td class="td_code">0x1003c</td>
......@@ -1010,7 +1010,7 @@ Control register
<tr><td><b>C block offset:</b></td><td class="td_code">0x8</td></tr>
</table>
<p>
VCXO voltage register
VCXO voltage
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -1093,7 +1093,7 @@ VCXO voltage register
<tr><td><b>C block offset:</b></td><td class="td_code">0xc</td></tr>
</table>
<p>
Clock ratio-1 register
Clock ratio minus 1
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -1171,9 +1171,9 @@ Clock ratio-1 register
</table>
<dl>
<dt><b>value</b> [<i>rw</i>]</dt>
<dd>Clock ratio-1</dd>
<dd>Clock ratio minus 1</dd>
<dt><b>ext</b> [<i>rw</i>]</dt>
<dd>Clock ratio-1 (for external output)</dd>
<dd>Clock ratio minus 1 (for external output)</dd>
</dl>
<a name="csr.ch1_delay_set"></a>
<h3>2.12. csr.ch1_delay_set</h3>
......@@ -1184,7 +1184,7 @@ Clock ratio-1 register
<tr><td><b>C block offset:</b></td><td class="td_code">0x10</td></tr>
</table>
<p>
SET delay configuration (channel 1)
CH1 set delay
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -1262,18 +1262,18 @@ SET delay configuration (channel 1)
</table>
<dl>
<dt><b>value</b> [<i>rw</i>]</dt>
<dd>CH1 SET delay</dd>
<dd>CH1 set delay</dd>
</dl>
<a name="csr.ch1_delay_reset"></a>
<h3>2.13. csr.ch1_delay_reset</h3>
<a name="csr.ch1_delay_res"></a>
<h3>2.13. csr.ch1_delay_res</h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">csr_ch1_delay_reset</td></tr>
<tr><td><b>HW prefix:</b></td><td class="td_code">csr_ch1_delay_res</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10014</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">csr.ch1_delay_reset</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">csr.ch1_delay_res</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x14</td></tr>
</table>
<p>
RES delay configuration (channel 1)
CH1 reset delay
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -1351,7 +1351,7 @@ RES delay configuration (channel 1)
</table>
<dl>
<dt><b>value</b> [<i>rw</i>]</dt>
<dd>CH1 RES delay</dd>
<dd>CH1 reset delay</dd>
</dl>
<a name="csr.ch2_delay_set"></a>
<h3>2.14. csr.ch2_delay_set</h3>
......@@ -1362,7 +1362,7 @@ RES delay configuration (channel 1)
<tr><td><b>C block offset:</b></td><td class="td_code">0x18</td></tr>
</table>
<p>
SET delay configuration (channel 2)
CH2 set delay
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -1440,18 +1440,18 @@ SET delay configuration (channel 2)
</table>
<dl>
<dt><b>value</b> [<i>rw</i>]</dt>
<dd>CH2 SET delay</dd>
<dd>CH2 set delay</dd>
</dl>
<a name="csr.ch2_delay_reset"></a>
<h3>2.15. csr.ch2_delay_reset</h3>
<a name="csr.ch2_delay_res"></a>
<h3>2.15. csr.ch2_delay_res</h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">csr_ch2_delay_reset</td></tr>
<tr><td><b>HW prefix:</b></td><td class="td_code">csr_ch2_delay_res</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x1001c</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">csr.ch2_delay_reset</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">csr.ch2_delay_res</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x1c</td></tr>
</table>
<p>
RES delay configuration (channel 2)
CH2 reset delay
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -1529,18 +1529,18 @@ RES delay configuration (channel 2)
</table>
<dl>
<dt><b>value</b> [<i>rw</i>]</dt>
<dd>CH2 RES delay</dd>
<dd>CH2 reset delay</dd>
</dl>
<a name="csr.trigger_threshold"></a>
<h3>2.16. csr.trigger_threshold</h3>
<a name="csr.trig_threshold"></a>
<h3>2.16. csr.trig_threshold</h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">csr_trigger_threshold</td></tr>
<tr><td><b>HW prefix:</b></td><td class="td_code">csr_trig_threshold</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10020</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">csr.trigger_threshold</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">csr.trig_threshold</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x20</td></tr>
</table>
<p>
Trigger threshold voltage register
Trigger threshold voltage
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -1612,7 +1612,7 @@ Trigger threshold voltage register
</table>
<dl>
<dt><b>value</b> [<i>rw</i>]</dt>
<dd>Trigger threshold voltage register value</dd>
<dd>Trigger threshold voltage value</dd>
</dl>
<a name="csr.overflow"></a>
<h3>2.17. csr.overflow</h3>
......@@ -1697,16 +1697,16 @@ Overflow
<dt><b>value</b> [<i>rw</i>]</dt>
<dd>Overflow value</dd>
</dl>
<a name="csr.ch1_trigger_latency"></a>
<h3>2.18. csr.ch1_trigger_latency</h3>
<a name="csr.ch1_trig_latency"></a>
<h3>2.18. csr.ch1_trig_latency</h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">csr_ch1_trigger_latency</td></tr>
<tr><td><b>HW prefix:</b></td><td class="td_code">csr_ch1_trig_latency</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10028</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">csr.ch1_trigger_latency</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">csr.ch1_trig_latency</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x28</td></tr>
</table>
<p>
Trigger latency (channel 1)
CH1 trigger latency
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -1927,7 +1927,7 @@ Debug register
<tr><td><b>C block offset:</b></td><td class="td_code">0x34</td></tr>
</table>
<p>
Gateware version
FFPG version
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -1993,16 +1993,16 @@ Gateware version
<dt><b>major</b> [<i>ro</i>]</dt>
<dd>Major version</dd>
</dl>
<a name="csr.ch2_trigger_latency"></a>
<h3>2.22. csr.ch2_trigger_latency</h3>
<a name="csr.ch2_trig_latency"></a>
<h3>2.22. csr.ch2_trig_latency</h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">csr_ch2_trigger_latency</td></tr>
<tr><td><b>HW prefix:</b></td><td class="td_code">csr_ch2_trig_latency</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x10038</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">csr.ch2_trigger_latency</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">csr.ch2_trig_latency</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x38</td></tr>
</table>
<p>
Trigger latency (channel 2)
CH2 trigger latency
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......
hdl/ffpg/cheby/Makefile
View file @ 17bfcce2
......@@ -6,14 +6,19 @@ CHEBY=cheby
RTL=../rtl
DOC=../../../doc/manual
SIM=../sim/testbench
DRV=../../../sw/driver
.PHONY: all
all: $(RTL)/ffpg_core_regs.vhd \
$(DOC)/ffpg_core.htm \
$(SIM)/ffpg_csr.svh
$(SIM)/ffpg_csr.svh \
$(DRV)/fmc_fpg_vme_hw_desc.csv \
$(DRV)/fmc_fpg_pci_hw_desc.csv
$(RTL)/ffpg_core_regs.vhd: ffpg_csr.cheby onewire_master.cheby spi_master.cheby
$(DOC)/ffpg_core.htm: ffpg_csr.cheby onewire_master.cheby spi_master.cheby
$(DRV)/fmc_fpg_vme_hw_desc.csv: ffpg_csr.cheby onewire_master.cheby spi_master.cheby
$(DRV)/fmc_fpg_pci_hw_desc.csv: ffpg_csr.cheby onewire_master.cheby spi_master.cheby
$(RTL)/%_regs.vhd: %.cheby
$(CHEBY) --hdl vhdl --gen-hdl $@ --header=commit --input $<
......@@ -23,3 +28,6 @@ $(DOC)/%.htm: %.cheby
$(SIM)/%.svh: %.cheby
$(CHEBY) --consts-style=verilog --gen-consts $@ --header=commit --input $<
$(DRV)/%_hw_desc.csv: %.cheby
$(CHEBY) --gen-edge3 $@ --input $<
\ No newline at end of file
hdl/ffpg/cheby/ffpg_csr.cheby
View file @ 17bfcce2
......@@ -25,6 +25,8 @@ memory-map:
0: configuration done
1: configuration in progress
range: 0
x-driver-edge:
generate: false
- field:
name: dac_vcxo_busy
description: VCXO DAC busy
......@@ -33,6 +35,8 @@ memory-map:
0: DAC idle, value already set
1: DAC busy, communication in progress
range: 1
x-driver-edge:
generate: false
- field:
name: dac_trigger_busy
description: Trigger DAC busy
......@@ -41,6 +45,8 @@ memory-map:
0: DAC idle, value already set
1: DAC busy, communication in progress
range: 2
x-driver-edge:
generate: false
- field:
name: delay_configuration_busy
description: Delay configuration in progress
......@@ -49,6 +55,8 @@ memory-map:
0: configuration done
1: configuration in progress
range: 3
x-driver-edge:
generate: false
- field:
name: channel_1_oe
description: Channel 1 output enabled
......@@ -57,6 +65,8 @@ memory-map:
0: output disabled
1: output enabled
range: 4
x-driver-edge:
generate: false
- field:
name: channel_2_oe
description: Channel 2 output enabled
......@@ -65,6 +75,8 @@ memory-map:
0: output disabled
1: output enabled
range: 5
x-driver-edge:
generate: false
- field:
name: channel_1_running
description: Pulse generator channel 1 running
......@@ -73,6 +85,8 @@ memory-map:
0: channel 1 is not running
1: channel 1 is running, pulses are generated
range: 6
x-driver-edge:
generate: false
- field:
name: channel_2_running
description: Pulse generator channel 2 running
......@@ -81,6 +95,8 @@ memory-map:
0: channel 2 is not running
1: channel 2 is running, pulses are generated
range: 7
x-driver-edge:
generate: false
- field:
name: input_clock_stable
description: Input clock stable
......@@ -89,6 +105,8 @@ memory-map:
0: input clock not present or not stable
1: input clock present and stable
range: 8
x-driver-edge:
generate: false
- reg:
name: control
description: Control register
......@@ -104,14 +122,20 @@ memory-map:
1: FPGA loop clock used
2: on-board VCXO clock used
range: 1-0
x-driver-edge:
generate: false
- field:
name: ch1_oe
description: CH1 output enable
range: 2
x-driver-edge:
generate: false
- field:
name: ch2_oe
description: CH2 output enable
range: 3
x-driver-edge:
generate: false
- field:
name: ch1_mode
description: CH1 mode selection
......@@ -120,6 +144,8 @@ memory-map:
1: continuous (non-stop memory looping)
2: one-shot (loop memory just once)
range: 5-4
x-driver-edge:
generate: false
- field:
name: ch2_mode
description: CH2 mode selection
......@@ -128,12 +154,16 @@ memory-map:
1: continuous (non-stop memory looping)
2: one-shot (loop memory just once)
range: 7-6
x-driver-edge:
generate: false
- field:
name: led_test
description: LED test
comment: |-
If set to 1, all LEDs on the FFPG front panel will be blinking.
range: 8
x-driver-edge:
generate: false
- field:
name: ad9512_sync
description: AD9512 synchronization
......@@ -143,6 +173,8 @@ memory-map:
range: 9
x-hdl:
type: autoclear
x-driver-edge:
generate: false
- field:
name: fine_delay_enable
description: AD9512 OUT4 fine delay enable
......@@ -150,6 +182,8 @@ memory-map:
If set to 1, fine delay on OUT4 output of AD9512 is enabled.
Fine delay itself can be set in a separate register.
range: 10
x-driver-edge:
generate: false
- field:
name: ad9512_spi_override
description: Override automatic AD9512 configuration by WB-SPI access
......@@ -157,6 +191,8 @@ memory-map:
If set to 1, the AD9512 SPI port is connected to the WB-SPI bridge.
Otherwise, the automatic configuration block is connected to the AD9512 SPI.
range: 11
x-driver-edge:
generate: false
- field:
name: ad9512_start_config
description: AD9512 start configuration
......@@ -166,9 +202,11 @@ memory-map:
range: 12
x-hdl:
type: autoclear
x-driver-edge:
generate: false
- reg:
name: vcxo_voltage
description: VCXO voltage register
description: VCXO voltage
comment: |-
This register value D determines output voltage of the VCXO DAC.
Voltage should be V_OUT = D * 5 / 65536 [V] (see datasheet), but is limited by 3.3 V supply voltage of the DAC.
......@@ -182,9 +220,11 @@ memory-map:
name: value
description: VCXO voltage register value
range: 15-0
x-driver-edge:
generate: false
- reg:
name: clock_ratio_m1
description: Clock ratio-1 register
description: Clock ratio minus 1
comment: |-
Clock ratio specifies the frequency of the serial stream clock generated by the AD9512 clock divider:
f_generated = f_input / (RATIO+1).
......@@ -198,15 +238,19 @@ memory-map:
children:
- field:
name: value
description: Clock ratio-1
description: Clock ratio minus 1
range: 4-0
x-driver-edge:
generate: false
- field:
name: ext
description: Clock ratio-1 (for external output)
description: Clock ratio minus 1 (for external output)
range: 20-16
x-driver-edge:
generate: false
- reg:
name: ch1_delay_set
description: SET delay configuration (channel 1)
description: CH1 set delay
comment: |-
10 bit fine delay for pulse generation - delay of the SET pulse, i.e. CH1 pulse delay
width: 32
......@@ -217,11 +261,13 @@ memory-map:
children:
- field:
name: value
description: CH1 SET delay
description: CH1 set delay
range: 9-0
x-driver-edge:
generate: false
- reg:
name: ch1_delay_reset
description: RES delay configuration (channel 1)
name: ch1_delay_res
description: CH1 reset delay
comment: |-
10 bit fine delays for pulse generation - delay of the RES pulse, i.e. CH1 pulse width
width: 32
......@@ -232,11 +278,13 @@ memory-map:
children:
- field:
name: value
description: CH1 RES delay
description: CH1 reset delay
range: 9-0
x-driver-edge:
generate: false
- reg:
name: ch2_delay_set
description: SET delay configuration (channel 2)
description: CH2 set delay
comment: |-
10 bit fine delay for pulse generation - delay of the SET pulse, i.e. CH2 pulse delay
width: 32
......@@ -247,11 +295,13 @@ memory-map:
children:
- field:
name: value
description: CH2 SET delay
description: CH2 set delay
range: 9-0
x-driver-edge:
generate: false
- reg:
name: ch2_delay_reset
description: RES delay configuration (channel 2)
name: ch2_delay_res
description: CH2 reset delay
comment: |-
10 bit fine delays for pulse generation - delay of the RES pulse, i.e. CH2 pulse width
width: 32
......@@ -262,11 +312,13 @@ memory-map:
children:
- field:
name: value
description: CH2 RES delay
description: CH2 reset delay
range: 9-0
x-driver-edge:
generate: false
- reg:
name: trigger_threshold
description: Trigger threshold voltage register
name: trig_threshold
description: Trigger threshold voltage
comment: |-
This register value D determines output voltage of the trigger threshold DAC.
Voltage should be V_OUT = D * 5 / 65536 [V] (see datasheet).
......@@ -278,8 +330,10 @@ memory-map:
children:
- field:
name: value
description: Trigger threshold voltage register value
description: Trigger threshold voltage value
range: 15-0
x-driver-edge:
generate: false
- reg:
name: overflow
description: Overflow
......@@ -296,9 +350,11 @@ memory-map:
name: value
description: Overflow value
range: 15-0
x-driver-edge:
generate: false
- reg:
name: ch1_trigger_latency
description: Trigger latency (channel 1)
name: ch1_trig_latency
description: CH1 trigger latency
comment: |-
The latency of the trigger in number of clock cycles of the serial stream clock, for channel 1.
When trigger is received, serial stream memory pointer is set to this value.
......@@ -312,6 +368,8 @@ memory-map:
name: value
description: Trigger latency value
range: 15-0
x-driver-edge:
generate: false
- reg:
name: frequency
description: Clock frequency
......@@ -330,7 +388,7 @@ memory-map:
address: 0x30
- reg:
name: version
description: Gateware version
description: FFPG version
comment: |-
Version of the current gateware in form of major.minor.revision
width: 32
......@@ -341,17 +399,23 @@ memory-map:
name: revision
description: Revision
range: 11-0
x-driver-edge:
generate: false
- field:
name: minor
description: Minor version
range: 21-12
x-driver-edge:
generate: false
- field:
name: major
description: Major version
range: 31-22
x-driver-edge:
generate: false
- reg:
name: ch2_trigger_latency
description: Trigger latency (channel 2)
name: ch2_trig_latency
description: CH2 trigger latency
comment: |-
The latency of the trigger in number of clock cycles of the serial stream clock, for channel 2.
When trigger is received, serial stream memory pointer is set to this value.
......@@ -365,6 +429,8 @@ memory-map:
name: value
description: Trigger latency value
range: 15-0
x-driver-edge:
generate: false
- reg:
name: fine_delay
description: AD9512 OUT4 fine delay
......@@ -381,14 +447,20 @@ memory-map:
name: value
description: AD9512 OUT4 fine delay value
range: 4-0
x-driver-edge:
generate: false
- field:
name: current
description: Ramp current
range: 7-5
x-driver-edge:
generate: false
- field:
name: capacitors
description: Ramp capacitors
range: 10-8
x-driver-edge:
generate: false
- memory:
name: ch1_set_mem
description: CH1 SET serial stream
......
hdl/ffpg/cheby/fmc_fpg_pci.cheby 0 → 100644
View file @ 17bfcce2
memory-map:
name: FMC-FPG
description: "FMC Fast Pulse Generator"
bus: wb-32-be
x-driver-edge:
board-type: fmc_fpg
driver-version: 1.0.0-pci
schema-version: 3.1
bus-type: PCI
endianness: little
device-info:
vendor-id: 0x10DC
device-id: 0x01A3
subvendor-id: 0x1A39
subdevice-id: 0x0004
children:
- address-space:
name: registers
size: 0x40000
children:
- submap:
name: onewire_master
description: OneWire master
address: 0x21000
filename: onewire_master.cheby
- submap:
name: spi_master
description: WB SPI master
address: 0x22000
filename: spi_master.cheby
- submap:
name: csr
description: Control/status registers
address: 0x30000
filename: ffpg_csr.cheby
hdl/ffpg/cheby/fmc_fpg_vme.cheby 0 → 100644
View file @ 17bfcce2
memory-map:
name: FMC-FPG
description: "FMC Fast Pulse Generator"
bus: wb-32-be
x-driver-edge:
board-type: fmc_fpg
driver-version: 1.0.0-vme
schema-version: 3.1
bus-type: VME
endianness: big
children:
- address-space:
name: registers
size: 0x40000
x-driver-edge:
number: 0
addr-mode: A24
data-width: 32
dma-mode: BLT|MBLT
children:
- submap:
name: onewire_master
description: OneWire master
address: 0x21000
filename: onewire_master.cheby
- submap:
name: spi_master
description: WB SPI master
address: 0x22000
filename: spi_master.cheby
- submap:
name: csr
description: Control/status registers
address: 0x30000
filename: ffpg_csr.cheby
hdl/ffpg/rtl/FfpgCore.vhd
View file @ 17bfcce2
......@@ -173,8 +173,8 @@ begin
port map (
Clk_ik => Clk_ik,
Reset_ir => Reset_r,
TriggerValue_ib16 => WbRegsOutput.csr_trigger_threshold_value,
TriggerLoad_i => WbRegsOutput.csr_trigger_threshold_wr,
TriggerValue_ib16 => WbRegsOutput.csr_trig_threshold_value,
TriggerLoad_i => WbRegsOutput.csr_trig_threshold_wr,
VcxoValue_ib16 => WbRegsOutput.csr_vcxo_voltage_value,
VcxoLoad_i => WbRegsOutput.csr_vcxo_voltage_wr,
TriggerDac_o => TriggerDac_o,
......@@ -195,12 +195,12 @@ begin
Reset_ir => Reset_r,
Ch1SetValue_ib => WbRegsOutput.csr_ch1_delay_set_value,
Ch1SetValueLoad_i => WbRegsOutput.csr_ch1_delay_set_wr,
Ch1ResValue_ib => WbRegsOutput.csr_ch1_delay_reset_value,
Ch1ResValueLoad_i => WbRegsOutput.csr_ch1_delay_reset_wr,
Ch1ResValue_ib => WbRegsOutput.csr_ch1_delay_res_value,
Ch1ResValueLoad_i => WbRegsOutput.csr_ch1_delay_res_wr,
Ch2SetValue_ib => WbRegsOutput.csr_ch2_delay_set_value,
Ch2SetValueLoad_i => WbRegsOutput.csr_ch2_delay_set_wr,
Ch2ResValue_ib => WbRegsOutput.csr_ch2_delay_reset_value,
Ch2ResValueLoad_i => WbRegsOutput.csr_ch2_delay_reset_wr,
Ch2ResValue_ib => WbRegsOutput.csr_ch2_delay_res_value,
Ch2ResValueLoad_i => WbRegsOutput.csr_ch2_delay_res_wr,
DelayValue_ob => DelayValue_ob,
Ch1SetLe_on => Ch1SetLe_on,
Ch1ResLe_on => Ch1ResLe_on,
......@@ -239,10 +239,10 @@ begin
Ch2ResMemReadStrobe_o => WbRegsInput.csr_ch2_res_mem_data_rd_i,
Overflow_ib16 => WbRegsOutput.csr_overflow_value,
OverflowLoad_i => WbRegsOutput.csr_overflow_wr,
Ch1TriggerLatency_ib16 => WbRegsOutput.csr_ch1_trigger_latency_value,
Ch1TriggerLatencyLoad_i => WbRegsOutput.csr_ch1_trigger_latency_wr,
Ch2TriggerLatency_ib16 => WbRegsOutput.csr_ch2_trigger_latency_value,
Ch2TriggerLatencyLoad_i => WbRegsOutput.csr_ch2_trigger_latency_wr,
Ch1TriggerLatency_ib16 => WbRegsOutput.csr_ch1_trig_latency_value,
Ch1TriggerLatencyLoad_i => WbRegsOutput.csr_ch1_trig_latency_wr,
Ch2TriggerLatency_ib16 => WbRegsOutput.csr_ch2_trig_latency_value,
Ch2TriggerLatencyLoad_i => WbRegsOutput.csr_ch2_trig_latency_wr,
Ch1Mode_i => f_SlvToMode(WbRegsOutput.csr_control_ch1_mode),
Ch1Running_o => WbRegsInput.csr_status_channel_1_running,
Ch2Mode_i => f_SlvToMode(WbRegsOutput.csr_control_ch2_mode),
......
hdl/ffpg/rtl/ffpg_core_regs.vhd
View file @ 17bfcce2
......@@ -27,20 +27,20 @@ package ffpg_core_regs_pkg is
csr_clock_ratio_m1_wr : std_logic;
csr_ch1_delay_set_value : std_logic_vector(9 downto 0);
csr_ch1_delay_set_wr : std_logic;
csr_ch1_delay_reset_value : std_logic_vector(9 downto 0);
csr_ch1_delay_reset_wr : std_logic;
csr_ch1_delay_res_value : std_logic_vector(9 downto 0);
csr_ch1_delay_res_wr : std_logic;
csr_ch2_delay_set_value : std_logic_vector(9 downto 0);
csr_ch2_delay_set_wr : std_logic;
csr_ch2_delay_reset_value : std_logic_vector(9 downto 0);
csr_ch2_delay_reset_wr : std_logic;
csr_trigger_threshold_value : std_logic_vector(15 downto 0);
csr_trigger_threshold_wr : std_logic;
csr_ch2_delay_res_value : std_logic_vector(9 downto 0);
csr_ch2_delay_res_wr : std_logic;
csr_trig_threshold_value : std_logic_vector(15 downto 0);
csr_trig_threshold_wr : std_logic;
csr_overflow_value : std_logic_vector(15 downto 0);
csr_overflow_wr : std_logic;
csr_ch1_trigger_latency_value : std_logic_vector(15 downto 0);
csr_ch1_trigger_latency_wr : std_logic;
csr_ch2_trigger_latency_value : std_logic_vector(15 downto 0);
csr_ch2_trigger_latency_wr : std_logic;
csr_ch1_trig_latency_value : std_logic_vector(15 downto 0);
csr_ch1_trig_latency_wr : std_logic;
csr_ch2_trig_latency_value : std_logic_vector(15 downto 0);
csr_ch2_trig_latency_wr : std_logic;
csr_fine_delay_value : std_logic_vector(4 downto 0);
csr_fine_delay_current : std_logic_vector(2 downto 0);
csr_fine_delay_capacitors : std_logic_vector(2 downto 0);
......@@ -160,34 +160,34 @@ architecture syn of ffpg_core_regs is
signal csr_ch1_delay_set_wreq : std_logic;
signal csr_ch1_delay_set_wack : std_logic;
signal csr_ch1_delay_set_wstrb : std_logic;
signal csr_ch1_delay_reset_value_reg : std_logic_vector(9 downto 0);
signal csr_ch1_delay_reset_wreq : std_logic;
signal csr_ch1_delay_reset_wack : std_logic;
signal csr_ch1_delay_reset_wstrb : std_logic;
signal csr_ch1_delay_res_value_reg : std_logic_vector(9 downto 0);
signal csr_ch1_delay_res_wreq : std_logic;
signal csr_ch1_delay_res_wack : std_logic;
signal csr_ch1_delay_res_wstrb : std_logic;
signal csr_ch2_delay_set_value_reg : std_logic_vector(9 downto 0);
signal csr_ch2_delay_set_wreq : std_logic;
signal csr_ch2_delay_set_wack : std_logic;
signal csr_ch2_delay_set_wstrb : std_logic;
signal csr_ch2_delay_reset_value_reg : std_logic_vector(9 downto 0);
signal csr_ch2_delay_reset_wreq : std_logic;
signal csr_ch2_delay_reset_wack : std_logic;
signal csr_ch2_delay_reset_wstrb : std_logic;
signal csr_trigger_threshold_value_reg : std_logic_vector(15 downto 0);
signal csr_trigger_threshold_wreq : std_logic;
signal csr_trigger_threshold_wack : std_logic;
signal csr_trigger_threshold_wstrb : std_logic;
signal csr_ch2_delay_res_value_reg : std_logic_vector(9 downto 0);
signal csr_ch2_delay_res_wreq : std_logic;
signal csr_ch2_delay_res_wack : std_logic;
signal csr_ch2_delay_res_wstrb : std_logic;
signal csr_trig_threshold_value_reg : std_logic_vector(15 downto 0);
signal csr_trig_threshold_wreq : std_logic;
signal csr_trig_threshold_wack : std_logic;
signal csr_trig_threshold_wstrb : std_logic;
signal csr_overflow_value_reg : std_logic_vector(15 downto 0);
signal csr_overflow_wreq : std_logic;
signal csr_overflow_wack : std_logic;
signal csr_overflow_wstrb : std_logic;
signal csr_ch1_trigger_latency_value_reg : std_logic_vector(15 downto 0);
signal csr_ch1_trigger_latency_wreq : std_logic;
signal csr_ch1_trigger_latency_wack : std_logic;
signal csr_ch1_trigger_latency_wstrb : std_logic;
signal csr_ch2_trigger_latency_value_reg : std_logic_vector(15 downto 0);
signal csr_ch2_trigger_latency_wreq : std_logic;
signal csr_ch2_trigger_latency_wack : std_logic;
signal csr_ch2_trigger_latency_wstrb : std_logic;
signal csr_ch1_trig_latency_value_reg : std_logic_vector(15 downto 0);
signal csr_ch1_trig_latency_wreq : std_logic;
signal csr_ch1_trig_latency_wack : std_logic;
signal csr_ch1_trig_latency_wstrb : std_logic;
signal csr_ch2_trig_latency_value_reg : std_logic_vector(15 downto 0);
signal csr_ch2_trig_latency_wreq : std_logic;
signal csr_ch2_trig_latency_wack : std_logic;
signal csr_ch2_trig_latency_wstrb : std_logic;
signal csr_fine_delay_value_reg : std_logic_vector(4 downto 0);
signal csr_fine_delay_current_reg : std_logic_vector(2 downto 0);
signal csr_fine_delay_capacitors_reg : std_logic_vector(2 downto 0);
......@@ -472,23 +472,23 @@ begin
end process;
csr_regs_o.csr_ch1_delay_set_wr <= csr_ch1_delay_set_wstrb;
-- Register csr_ch1_delay_reset
csr_regs_o.csr_ch1_delay_reset_value <= csr_ch1_delay_reset_value_reg;
csr_ch1_delay_reset_wack <= csr_ch1_delay_reset_wreq;
-- Register csr_ch1_delay_res
csr_regs_o.csr_ch1_delay_res_value <= csr_ch1_delay_res_value_reg;
csr_ch1_delay_res_wack <= csr_ch1_delay_res_wreq;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
csr_ch1_delay_reset_value_reg <= "0000000000";
csr_ch1_delay_reset_wstrb <= '0';
csr_ch1_delay_res_value_reg <= "0000000000";
csr_ch1_delay_res_wstrb <= '0';
else
if csr_ch1_delay_reset_wreq = '1' then
csr_ch1_delay_reset_value_reg <= wr_dat_d0(9 downto 0);
if csr_ch1_delay_res_wreq = '1' then
csr_ch1_delay_res_value_reg <= wr_dat_d0(9 downto 0);
end if;
csr_ch1_delay_reset_wstrb <= csr_ch1_delay_reset_wreq;
csr_ch1_delay_res_wstrb <= csr_ch1_delay_res_wreq;
end if;
end if;
end process;
csr_regs_o.csr_ch1_delay_reset_wr <= csr_ch1_delay_reset_wstrb;
csr_regs_o.csr_ch1_delay_res_wr <= csr_ch1_delay_res_wstrb;
-- Register csr_ch2_delay_set
csr_regs_o.csr_ch2_delay_set_value <= csr_ch2_delay_set_value_reg;
......@@ -508,41 +508,41 @@ begin
end process;
csr_regs_o.csr_ch2_delay_set_wr <= csr_ch2_delay_set_wstrb;
-- Register csr_ch2_delay_reset
csr_regs_o.csr_ch2_delay_reset_value <= csr_ch2_delay_reset_value_reg;
csr_ch2_delay_reset_wack <= csr_ch2_delay_reset_wreq;
-- Register csr_ch2_delay_res
csr_regs_o.csr_ch2_delay_res_value <= csr_ch2_delay_res_value_reg;
csr_ch2_delay_res_wack <= csr_ch2_delay_res_wreq;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
csr_ch2_delay_reset_value_reg <= "0000000000";
csr_ch2_delay_reset_wstrb <= '0';
csr_ch2_delay_res_value_reg <= "0000000000";
csr_ch2_delay_res_wstrb <= '0';
else
if csr_ch2_delay_reset_wreq = '1' then
csr_ch2_delay_reset_value_reg <= wr_dat_d0(9 downto 0);
if csr_ch2_delay_res_wreq = '1' then
csr_ch2_delay_res_value_reg <= wr_dat_d0(9 downto 0);
end if;
csr_ch2_delay_reset_wstrb <= csr_ch2_delay_reset_wreq;
csr_ch2_delay_res_wstrb <= csr_ch2_delay_res_wreq;
end if;
end if;
end process;
csr_regs_o.csr_ch2_delay_reset_wr <= csr_ch2_delay_reset_wstrb;
csr_regs_o.csr_ch2_delay_res_wr <= csr_ch2_delay_res_wstrb;
-- Register csr_trigger_threshold
csr_regs_o.csr_trigger_threshold_value <= csr_trigger_threshold_value_reg;
csr_trigger_threshold_wack <= csr_trigger_threshold_wreq;
-- Register csr_trig_threshold
csr_regs_o.csr_trig_threshold_value <= csr_trig_threshold_value_reg;
csr_trig_threshold_wack <= csr_trig_threshold_wreq;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
csr_trigger_threshold_value_reg <= "0000000000000000";
csr_trigger_threshold_wstrb <= '0';
csr_trig_threshold_value_reg <= "0000000000000000";
csr_trig_threshold_wstrb <= '0';
else
if csr_trigger_threshold_wreq = '1' then
csr_trigger_threshold_value_reg <= wr_dat_d0(15 downto 0);
if csr_trig_threshold_wreq = '1' then
csr_trig_threshold_value_reg <= wr_dat_d0(15 downto 0);
end if;
csr_trigger_threshold_wstrb <= csr_trigger_threshold_wreq;
csr_trig_threshold_wstrb <= csr_trig_threshold_wreq;
end if;
end if;
end process;
csr_regs_o.csr_trigger_threshold_wr <= csr_trigger_threshold_wstrb;
csr_regs_o.csr_trig_threshold_wr <= csr_trig_threshold_wstrb;
-- Register csr_overflow
csr_regs_o.csr_overflow_value <= csr_overflow_value_reg;
......@@ -562,23 +562,23 @@ begin
end process;
csr_regs_o.csr_overflow_wr <= csr_overflow_wstrb;
-- Register csr_ch1_trigger_latency
csr_regs_o.csr_ch1_trigger_latency_value <= csr_ch1_trigger_latency_value_reg;
csr_ch1_trigger_latency_wack <= csr_ch1_trigger_latency_wreq;
-- Register csr_ch1_trig_latency
csr_regs_o.csr_ch1_trig_latency_value <= csr_ch1_trig_latency_value_reg;
csr_ch1_trig_latency_wack <= csr_ch1_trig_latency_wreq;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
csr_ch1_trigger_latency_value_reg <= "0000000000000000";
csr_ch1_trigger_latency_wstrb <= '0';
csr_ch1_trig_latency_value_reg <= "0000000000000000";
csr_ch1_trig_latency_wstrb <= '0';
else
if csr_ch1_trigger_latency_wreq = '1' then
csr_ch1_trigger_latency_value_reg <= wr_dat_d0(15 downto 0);
if csr_ch1_trig_latency_wreq = '1' then
csr_ch1_trig_latency_value_reg <= wr_dat_d0(15 downto 0);
end if;
csr_ch1_trigger_latency_wstrb <= csr_ch1_trigger_latency_wreq;
csr_ch1_trig_latency_wstrb <= csr_ch1_trig_latency_wreq;
end if;
end if;
end process;
csr_regs_o.csr_ch1_trigger_latency_wr <= csr_ch1_trigger_latency_wstrb;
csr_regs_o.csr_ch1_trig_latency_wr <= csr_ch1_trig_latency_wstrb;
-- Register csr_frequency
......@@ -586,23 +586,23 @@ begin
-- Register csr_version
-- Register csr_ch2_trigger_latency
csr_regs_o.csr_ch2_trigger_latency_value <= csr_ch2_trigger_latency_value_reg;
csr_ch2_trigger_latency_wack <= csr_ch2_trigger_latency_wreq;
-- Register csr_ch2_trig_latency
csr_regs_o.csr_ch2_trig_latency_value <= csr_ch2_trig_latency_value_reg;
csr_ch2_trig_latency_wack <= csr_ch2_trig_latency_wreq;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
csr_ch2_trigger_latency_value_reg <= "0000000000000000";
csr_ch2_trigger_latency_wstrb <= '0';
csr_ch2_trig_latency_value_reg <= "0000000000000000";
csr_ch2_trig_latency_wstrb <= '0';
else
if csr_ch2_trigger_latency_wreq = '1' then
csr_ch2_trigger_latency_value_reg <= wr_dat_d0(15 downto 0);
if csr_ch2_trig_latency_wreq = '1' then
csr_ch2_trig_latency_value_reg <= wr_dat_d0(15 downto 0);
end if;
csr_ch2_trigger_latency_wstrb <= csr_ch2_trigger_latency_wreq;
csr_ch2_trig_latency_wstrb <= csr_ch2_trig_latency_wreq;
end if;
end if;
end process;
csr_regs_o.csr_ch2_trigger_latency_wr <= csr_ch2_trigger_latency_wstrb;
csr_regs_o.csr_ch2_trig_latency_wr <= csr_ch2_trig_latency_wstrb;
-- Register csr_fine_delay
csr_regs_o.csr_fine_delay_value <= csr_fine_delay_value_reg;
......@@ -868,10 +868,10 @@ begin
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, onewire_master_wack, spi_master_wack,
csr_control_wack, csr_vcxo_voltage_wack, csr_clock_ratio_m1_wack,
csr_ch1_delay_set_wack, csr_ch1_delay_reset_wack,
csr_ch2_delay_set_wack, csr_ch2_delay_reset_wack,
csr_trigger_threshold_wack, csr_overflow_wack,
csr_ch1_trigger_latency_wack, csr_ch2_trigger_latency_wack,
csr_ch1_delay_set_wack, csr_ch1_delay_res_wack,
csr_ch2_delay_set_wack, csr_ch2_delay_res_wack,
csr_trig_threshold_wack, csr_overflow_wack,
csr_ch1_trig_latency_wack, csr_ch2_trig_latency_wack,
csr_fine_delay_wack) begin
onewire_master_we <= '0';
spi_master_we <= '0';
......@@ -879,13 +879,13 @@ begin
csr_vcxo_voltage_wreq <= '0';
csr_clock_ratio_m1_wreq <= '0';
csr_ch1_delay_set_wreq <= '0';
csr_ch1_delay_reset_wreq <= '0';
csr_ch1_delay_res_wreq <= '0';
csr_ch2_delay_set_wreq <= '0';
csr_ch2_delay_reset_wreq <= '0';
csr_trigger_threshold_wreq <= '0';
csr_ch2_delay_res_wreq <= '0';
csr_trig_threshold_wreq <= '0';
csr_overflow_wreq <= '0';
csr_ch1_trigger_latency_wreq <= '0';
csr_ch2_trigger_latency_wreq <= '0';
csr_ch1_trig_latency_wreq <= '0';
csr_ch2_trig_latency_wreq <= '0';
csr_fine_delay_wreq <= '0';
csr_ch1_set_mem_data_int_wr <= '0';
csr_ch1_res_mem_data_int_wr <= '0';
......@@ -922,29 +922,29 @@ begin
csr_ch1_delay_set_wreq <= wr_req_d0;
wr_ack_int <= csr_ch1_delay_set_wack;
when "00000000101" =>
-- Reg csr_ch1_delay_reset
csr_ch1_delay_reset_wreq <= wr_req_d0;
wr_ack_int <= csr_ch1_delay_reset_wack;
-- Reg csr_ch1_delay_res
csr_ch1_delay_res_wreq <= wr_req_d0;
wr_ack_int <= csr_ch1_delay_res_wack;
when "00000000110" =>
-- Reg csr_ch2_delay_set
csr_ch2_delay_set_wreq <= wr_req_d0;
wr_ack_int <= csr_ch2_delay_set_wack;
when "00000000111" =>
-- Reg csr_ch2_delay_reset
csr_ch2_delay_reset_wreq <= wr_req_d0;
wr_ack_int <= csr_ch2_delay_reset_wack;
-- Reg csr_ch2_delay_res
csr_ch2_delay_res_wreq <= wr_req_d0;
wr_ack_int <= csr_ch2_delay_res_wack;
when "00000001000" =>
-- Reg csr_trigger_threshold
csr_trigger_threshold_wreq <= wr_req_d0;
wr_ack_int <= csr_trigger_threshold_wack;
-- Reg csr_trig_threshold
csr_trig_threshold_wreq <= wr_req_d0;
wr_ack_int <= csr_trig_threshold_wack;
when "00000001001" =>
-- Reg csr_overflow
csr_overflow_wreq <= wr_req_d0;
wr_ack_int <= csr_overflow_wack;
when "00000001010" =>
-- Reg csr_ch1_trigger_latency
csr_ch1_trigger_latency_wreq <= wr_req_d0;
wr_ack_int <= csr_ch1_trigger_latency_wack;
-- Reg csr_ch1_trig_latency
csr_ch1_trig_latency_wreq <= wr_req_d0;
wr_ack_int <= csr_ch1_trig_latency_wack;
when "00000001011" =>
-- Reg csr_frequency
wr_ack_int <= wr_req_d0;
......@@ -955,9 +955,9 @@ begin
-- Reg csr_version
wr_ack_int <= wr_req_d0;
when "00000001110" =>
-- Reg csr_ch2_trigger_latency
csr_ch2_trigger_latency_wreq <= wr_req_d0;
wr_ack_int <= csr_ch2_trigger_latency_wack;
-- Reg csr_ch2_trig_latency
csr_ch2_trig_latency_wreq <= wr_req_d0;
wr_ack_int <= csr_ch2_trig_latency_wack;
when "00000001111" =>
-- Reg csr_fine_delay
csr_fine_delay_wreq <= wr_req_d0;
......@@ -1004,13 +1004,13 @@ begin
csr_control_fine_delay_enable_reg,
csr_control_ad9512_spi_override_reg, csr_vcxo_voltage_value_reg,
csr_clock_ratio_m1_value_reg, csr_clock_ratio_m1_ext_reg,
csr_ch1_delay_set_value_reg, csr_ch1_delay_reset_value_reg,
csr_ch2_delay_set_value_reg, csr_ch2_delay_reset_value_reg,
csr_trigger_threshold_value_reg, csr_overflow_value_reg,
csr_ch1_trigger_latency_value_reg, csr_regs_i.csr_frequency,
csr_ch1_delay_set_value_reg, csr_ch1_delay_res_value_reg,
csr_ch2_delay_set_value_reg, csr_ch2_delay_res_value_reg,
csr_trig_threshold_value_reg, csr_overflow_value_reg,
csr_ch1_trig_latency_value_reg, csr_regs_i.csr_frequency,
csr_regs_i.csr_debug, csr_regs_i.csr_version_revision,
csr_regs_i.csr_version_minor, csr_regs_i.csr_version_major,
csr_ch2_trigger_latency_value_reg, csr_fine_delay_value_reg,
csr_ch2_trig_latency_value_reg, csr_fine_delay_value_reg,
csr_fine_delay_current_reg, csr_fine_delay_capacitors_reg,
csr_ch1_set_mem_data_int_dato, csr_ch1_set_mem_data_rack,
csr_ch1_res_mem_data_int_dato, csr_ch1_res_mem_data_rack,
......@@ -1082,9 +1082,9 @@ begin
rd_dat_d0(9 downto 0) <= csr_ch1_delay_set_value_reg;
rd_dat_d0(31 downto 10) <= (others => '0');
when "00000000101" =>
-- Reg csr_ch1_delay_reset
-- Reg csr_ch1_delay_res
rd_ack_d0 <= rd_req_int;
rd_dat_d0(9 downto 0) <= csr_ch1_delay_reset_value_reg;
rd_dat_d0(9 downto 0) <= csr_ch1_delay_res_value_reg;
rd_dat_d0(31 downto 10) <= (others => '0');
when "00000000110" =>
-- Reg csr_ch2_delay_set
......@@ -1092,14 +1092,14 @@ begin
rd_dat_d0(9 downto 0) <= csr_ch2_delay_set_value_reg;
rd_dat_d0(31 downto 10) <= (others => '0');
when "00000000111" =>
-- Reg csr_ch2_delay_reset
-- Reg csr_ch2_delay_res
rd_ack_d0 <= rd_req_int;
rd_dat_d0(9 downto 0) <= csr_ch2_delay_reset_value_reg;
rd_dat_d0(9 downto 0) <= csr_ch2_delay_res_value_reg;
rd_dat_d0(31 downto 10) <= (others => '0');
when "00000001000" =>
-- Reg csr_trigger_threshold
-- Reg csr_trig_threshold
rd_ack_d0 <= rd_req_int;
rd_dat_d0(15 downto 0) <= csr_trigger_threshold_value_reg;
rd_dat_d0(15 downto 0) <= csr_trig_threshold_value_reg;
rd_dat_d0(31 downto 16) <= (others => '0');
when "00000001001" =>
-- Reg csr_overflow
......@@ -1107,9 +1107,9 @@ begin
rd_dat_d0(15 downto 0) <= csr_overflow_value_reg;
rd_dat_d0(31 downto 16) <= (others => '0');
when "00000001010" =>
-- Reg csr_ch1_trigger_latency
-- Reg csr_ch1_trig_latency
rd_ack_d0 <= rd_req_int;
rd_dat_d0(15 downto 0) <= csr_ch1_trigger_latency_value_reg;
rd_dat_d0(15 downto 0) <= csr_ch1_trig_latency_value_reg;
rd_dat_d0(31 downto 16) <= (others => '0');
when "00000001011" =>
-- Reg csr_frequency
......@@ -1126,9 +1126,9 @@ begin
rd_dat_d0(21 downto 12) <= csr_regs_i.csr_version_minor;
rd_dat_d0(31 downto 22) <= csr_regs_i.csr_version_major;
when "00000001110" =>
-- Reg csr_ch2_trigger_latency
-- Reg csr_ch2_trig_latency
rd_ack_d0 <= rd_req_int;
rd_dat_d0(15 downto 0) <= csr_ch2_trigger_latency_value_reg;
rd_dat_d0(15 downto 0) <= csr_ch2_trig_latency_value_reg;
rd_dat_d0(31 downto 16) <= (others => '0');
when "00000001111" =>
-- Reg csr_fine_delay
......
hdl/ffpg/sim/testbench/ffpg_csr.svh
View file @ 17bfcce2
......@@ -99,36 +99,36 @@
`define FFPG_CSR_CH1_DELAY_SET_VALUE_WIDTH 10
`define FFPG_CSR_CH1_DELAY_SET_VALUE_OFFSET 0
`define FFPG_CSR_CH1_DELAY_SET_VALUE 'h3ff
`define ADDR_FFPG_CSR_CH1_DELAY_RESET 'h14
`define ADDR_FFPG_CSR_CH1_DELAY_RESET_VALUE 'h14
`define FFPG_CSR_CH1_DELAY_RESET_VALUE_WIDTH 10
`define FFPG_CSR_CH1_DELAY_RESET_VALUE_OFFSET 0
`define FFPG_CSR_CH1_DELAY_RESET_VALUE 'h3ff
`define ADDR_FFPG_CSR_CH1_DELAY_RES 'h14
`define ADDR_FFPG_CSR_CH1_DELAY_RES_VALUE 'h14
`define FFPG_CSR_CH1_DELAY_RES_VALUE_WIDTH 10
`define FFPG_CSR_CH1_DELAY_RES_VALUE_OFFSET 0
`define FFPG_CSR_CH1_DELAY_RES_VALUE 'h3ff
`define ADDR_FFPG_CSR_CH2_DELAY_SET 'h18
`define ADDR_FFPG_CSR_CH2_DELAY_SET_VALUE 'h18
`define FFPG_CSR_CH2_DELAY_SET_VALUE_WIDTH 10
`define FFPG_CSR_CH2_DELAY_SET_VALUE_OFFSET 0
`define FFPG_CSR_CH2_DELAY_SET_VALUE 'h3ff
`define ADDR_FFPG_CSR_CH2_DELAY_RESET 'h1c
`define ADDR_FFPG_CSR_CH2_DELAY_RESET_VALUE 'h1c
`define FFPG_CSR_CH2_DELAY_RESET_VALUE_WIDTH 10
`define FFPG_CSR_CH2_DELAY_RESET_VALUE_OFFSET 0
`define FFPG_CSR_CH2_DELAY_RESET_VALUE 'h3ff
`define ADDR_FFPG_CSR_TRIGGER_THRESHOLD 'h20
`define ADDR_FFPG_CSR_TRIGGER_THRESHOLD_VALUE 'h20
`define FFPG_CSR_TRIGGER_THRESHOLD_VALUE_WIDTH 16
`define FFPG_CSR_TRIGGER_THRESHOLD_VALUE_OFFSET 0
`define FFPG_CSR_TRIGGER_THRESHOLD_VALUE 'hffff
`define ADDR_FFPG_CSR_CH2_DELAY_RES 'h1c
`define ADDR_FFPG_CSR_CH2_DELAY_RES_VALUE 'h1c
`define FFPG_CSR_CH2_DELAY_RES_VALUE_WIDTH 10
`define FFPG_CSR_CH2_DELAY_RES_VALUE_OFFSET 0
`define FFPG_CSR_CH2_DELAY_RES_VALUE 'h3ff
`define ADDR_FFPG_CSR_TRIG_THRESHOLD 'h20
`define ADDR_FFPG_CSR_TRIG_THRESHOLD_VALUE 'h20
`define FFPG_CSR_TRIG_THRESHOLD_VALUE_WIDTH 16
`define FFPG_CSR_TRIG_THRESHOLD_VALUE_OFFSET 0
`define FFPG_CSR_TRIG_THRESHOLD_VALUE 'hffff
`define ADDR_FFPG_CSR_OVERFLOW 'h24
`define ADDR_FFPG_CSR_OVERFLOW_VALUE 'h24
`define FFPG_CSR_OVERFLOW_VALUE_WIDTH 16
`define FFPG_CSR_OVERFLOW_VALUE_OFFSET 0
`define FFPG_CSR_OVERFLOW_VALUE 'hffff
`define ADDR_FFPG_CSR_CH1_TRIGGER_LATENCY 'h28
`define ADDR_FFPG_CSR_CH1_TRIGGER_LATENCY_VALUE 'h28
`define FFPG_CSR_CH1_TRIGGER_LATENCY_VALUE_WIDTH 16
`define FFPG_CSR_CH1_TRIGGER_LATENCY_VALUE_OFFSET 0
`define FFPG_CSR_CH1_TRIGGER_LATENCY_VALUE 'hffff
`define ADDR_FFPG_CSR_CH1_TRIG_LATENCY 'h28
`define ADDR_FFPG_CSR_CH1_TRIG_LATENCY_VALUE 'h28
`define FFPG_CSR_CH1_TRIG_LATENCY_VALUE_WIDTH 16
`define FFPG_CSR_CH1_TRIG_LATENCY_VALUE_OFFSET 0
`define FFPG_CSR_CH1_TRIG_LATENCY_VALUE 'hffff
`define ADDR_FFPG_CSR_FREQUENCY 'h2c
`define ADDR_FFPG_CSR_DEBUG 'h30
`define ADDR_FFPG_CSR_VERSION 'h34
......@@ -144,11 +144,11 @@
`define FFPG_CSR_VERSION_MAJOR_WIDTH 10
`define FFPG_CSR_VERSION_MAJOR_OFFSET 22
`define FFPG_CSR_VERSION_MAJOR 'hffc00000
`define ADDR_FFPG_CSR_CH2_TRIGGER_LATENCY 'h38
`define ADDR_FFPG_CSR_CH2_TRIGGER_LATENCY_VALUE 'h38
`define FFPG_CSR_CH2_TRIGGER_LATENCY_VALUE_WIDTH 16
`define FFPG_CSR_CH2_TRIGGER_LATENCY_VALUE_OFFSET 0
`define FFPG_CSR_CH2_TRIGGER_LATENCY_VALUE 'hffff
`define ADDR_FFPG_CSR_CH2_TRIG_LATENCY 'h38
`define ADDR_FFPG_CSR_CH2_TRIG_LATENCY_VALUE 'h38
`define FFPG_CSR_CH2_TRIG_LATENCY_VALUE_WIDTH 16
`define FFPG_CSR_CH2_TRIG_LATENCY_VALUE_OFFSET 0
`define FFPG_CSR_CH2_TRIG_LATENCY_VALUE 'hffff
`define ADDR_FFPG_CSR_FINE_DELAY 'h3c
`define ADDR_FFPG_CSR_FINE_DELAY_VALUE 'h3c
`define FFPG_CSR_FINE_DELAY_VALUE_WIDTH 5
......
sw/driver/fmc_fpg_pci_hw_desc.csv
View file @ 17bfcce2
#Encore Driver GEnerator version 3.1
# Module description table
hw_mod_name, hw_lif_name, hw_lif_vers, edge_vers, bus, endian, description
FMC-FPG, fmc_fpg, 1.0.0-pci, 3.1, PCI, LE, FMC Fast Pulse Generator
# Device Identification table definition
vendor, device, args
0x10DC, 0x01A3, subvendor=0x1A39 subdevice=0x0004
# BARs definition table
res_def_name, type, res_no, args, description
registers, MEM, 0, ,
# Block definition table
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
csr, REG, status, 0x0, r, 32, 0x1, , , Status register
csr, REG, control, 0x4, rw, 32, 0x1, , , Control register
csr, REG, vcxo_voltage, 0x8, rw, 32, 0x1, , , VCXO voltage
csr, REG, clock_ratio_m1, 0xc, rw, 32, 0x1, , , Clock ratio minus 1
csr, REG, ch1_delay_set, 0x10, rw, 32, 0x1, , , CH1 set delay
csr, REG, ch1_delay_res, 0x14, rw, 32, 0x1, , , CH1 reset delay
csr, REG, ch2_delay_set, 0x18, rw, 32, 0x1, , , CH2 set delay
csr, REG, ch2_delay_res, 0x1c, rw, 32, 0x1, , , CH2 reset delay
csr, REG, trig_threshold, 0x20, rw, 32, 0x1, , , Trigger threshold voltage
csr, REG, overflow, 0x24, rw, 32, 0x1, , , Overflow
csr, REG, ch1_trig_latency, 0x28, rw, 32, 0x1, , , CH1 trigger latency
csr, REG, frequency, 0x2c, r, 32, 0x1, , , Clock frequency
csr, REG, debug, 0x30, r, 32, 0x1, , , Debug register
csr, REG, version, 0x34, r, 32, 0x1, , , FFPG version
csr, REG, ch2_trig_latency, 0x38, rw, 32, 0x1, , , CH2 trigger latency
csr, REG, fine_delay, 0x3c, rw, 32, 0x1, , , AD9512 OUT4 fine delay
csr, REG, ch1_set_mem, 0x2000, rw, 32, 0x800, , , CH1 SET serial stream
csr, REG, ch1_res_mem, 0x4000, rw, 32, 0x800, , , CH1 RES serial stream
csr, REG, ch2_set_mem, 0x6000, rw, 32, 0x800, , , CH2 SET serial stream
csr, REG, ch2_res_mem, 0x8000, rw, 32, 0x800, , , CH2 RES serial stream
# Block definition table
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
spi_master, REG, status, 0x0, rw, 32, 0x1, , , Status register
spi_master, REG, config1, 0x4, rw, 32, 0x1, , , Config 1 register
spi_master, REG, config2, 0x8, rw, 32, 0x1, , , Config 2 register
spi_master, REG, shift_out, 0xc, rw, 32, 0x1, , , Shift out register
spi_master, REG, shift_in, 0x10, rw, 32, 0x1, , , Shift in register
# Block definition table
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
onewire_master, REG, ctrl_sta, 0x0, rw, 32, 0x1, , , Control/status register
onewire_master, REG, cdr, 0x4, rw, 32, 0x1, , , Clock dividers register
# Block instances table
block_inst_name, block_def_name, res_def_name, offset, description
onewire_master, onewire_master, registers, 0x21000, OneWire master
spi_master, spi_master, registers, 0x22000, WB SPI master
csr, csr, registers, 0x30000, Control/status registers
# Reg roles table
reg_role, reg_name, block_def_name, args
#Encore Driver GEnerator version: 3.1
#LIF (Logical Interface) table definition
hw_mod_name, hw_lif_name, hw_lif_vers, edge_vers, bus, endian, description
FMC-FPG, fmc_fpg, 1.0.0-pci, 3.1, PCI, LE, FMC Fast Pulse Generator
#Device Identification table definition
vendor, device, args
0x10dc, 0x1a3, subvendor=0x1a39 subdevice=0x4
#Resources (Memory(BARs) - DMA - IRQ) table definition
res_def_name, type, res_no, args, description
registers, MEM, 0, ,
#Block table definition
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
onewire_master, REG, ctrl_sta, 0x0, rw, 32, 0x1, , , Control/status register
onewire_master, REG, cdr, 0x4, rw, 32, 0x1, , , Clock dividers register
#Block table definition
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
spi_master, REG, status, 0x0, r, 32, 0x1, , , Status register
spi_master, REG, config1, 0x4, rw, 32, 0x1, , , Config 1 register
spi_master, REG, config2, 0x8, rw, 32, 0x1, , , Config 2 register
spi_master, REG, shift_out, 0xc, rw, 32, 0x1, , , Shift out register
spi_master, REG, shift_in, 0x10, r, 32, 0x1, , , Shift in register
#Block table definition
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
ffpg_csr, REG, status, 0x0, r, 32, 0x1, , , Status register
ffpg_csr, REG, control, 0x4, rw, 32, 0x1, , , Control register
ffpg_csr, REG, vcxo_voltage, 0x8, rw, 32, 0x1, , , VCXO voltage
ffpg_csr, REG, clock_ratio_m1, 0xc, rw, 32, 0x1, , , Clock ratio minus 1
ffpg_csr, REG, ch1_delay_set, 0x10, rw, 32, 0x1, , , CH1 set delay
ffpg_csr, REG, ch1_delay_res, 0x14, rw, 32, 0x1, , , CH1 reset delay
ffpg_csr, REG, ch2_delay_set, 0x18, rw, 32, 0x1, , , CH2 set delay
ffpg_csr, REG, ch2_delay_res, 0x1c, rw, 32, 0x1, , , CH2 reset delay
ffpg_csr, REG, trig_threshold, 0x20, rw, 32, 0x1, , , Trigger threshold voltage
ffpg_csr, REG, overflow, 0x24, rw, 32, 0x1, , , Overflow
ffpg_csr, REG, ch1_trig_latency, 0x28, rw, 32, 0x1, , , CH1 trigger latency
ffpg_csr, REG, frequency, 0x2c, r, 32, 0x1, , , Clock frequency
ffpg_csr, REG, debug, 0x30, r, 32, 0x1, , , Debug register
ffpg_csr, REG, version, 0x34, r, 32, 0x1, , , FFPG version
ffpg_csr, REG, ch2_trig_latency, 0x38, rw, 32, 0x1, , , CH2 trigger latency
ffpg_csr, REG, fine_delay, 0x3c, rw, 32, 0x1, , , AD9512 OUT4 fine delay
ffpg_csr, REG, ch1_set_mem, 0x2000, rw, 32, 0x800, , , CH1 SET serial stream
ffpg_csr, REG, ch1_res_mem, 0x4000, rw, 32, 0x800, , , CH1 RES serial stream
ffpg_csr, REG, ch2_set_mem, 0x6000, rw, 32, 0x800, , , CH2 SET serial stream
ffpg_csr, REG, ch2_res_mem, 0x8000, rw, 32, 0x800, , , CH2 RES serial stream
#Block instances table definition
block_inst_name, block_def_name, res_def_name, offset, description
onewire_master, onewire_master, registers, 0x21000, OneWire master
spi_master, spi_master, registers, 0x22000, WB SPI master
csr, ffpg_csr, registers, 0x30000, Control/status registers
#Interrupt Controller (INTC) table definition
intc_name, type, reg_name, block_def_name, chained_intc_name, chained_intc_mask, args, description
#Register Roles table definition
reg_role, reg_name, block_def_name, args
sw/driver/fmc_fpg_vme_hw_desc.csv
View file @ 17bfcce2
#Encore Driver GEnerator version 3.1
# Module description table
hw_mod_name, hw_lif_name, hw_lif_vers, edge_vers, bus, endian, description
FMC-FPG, fmc_fpg, 1.0.0-vme, 3.1, VME, BE, FMC Fast Pulse Generator
# BARs definition table
res_def_name, type, res_no, args, description
registers, MEM, 0, addrspace=A24 dwidth=32 size=0x20000 dma=BLT|MBLT,
# Block definition table
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
csr, REG, status, 0x0, r, 32, 0x1, , , Status register
csr, REG, control, 0x4, rw, 32, 0x1, , , Control register
csr, REG, vcxo_voltage, 0x8, rw, 32, 0x1, , , VCXO voltage
csr, REG, clock_ratio_m1, 0xc, rw, 32, 0x1, , , Clock ratio minus 1
csr, REG, ch1_delay_set, 0x10, rw, 32, 0x1, , , CH1 set delay
csr, REG, ch1_delay_res, 0x14, rw, 32, 0x1, , , CH1 reset delay
csr, REG, ch2_delay_set, 0x18, rw, 32, 0x1, , , CH2 set delay
csr, REG, ch2_delay_res, 0x1c, rw, 32, 0x1, , , CH2 reset delay
csr, REG, trig_threshold, 0x20, rw, 32, 0x1, , , Trigger threshold voltage
csr, REG, overflow, 0x24, rw, 32, 0x1, , , Overflow
csr, REG, ch1_trig_latency, 0x28, rw, 32, 0x1, , , CH1 trigger latency
csr, REG, frequency, 0x2c, r, 32, 0x1, , , Clock frequency
csr, REG, debug, 0x30, r, 32, 0x1, , , Debug register
csr, REG, version, 0x34, r, 32, 0x1, , , FFPG version
csr, REG, ch2_trig_latency, 0x38, rw, 32, 0x1, , , CH2 trigger latency
csr, REG, fine_delay, 0x3c, rw, 32, 0x1, , , AD9512 OUT4 fine delay
csr, REG, ch1_set_mem, 0x2000, rw, 32, 0x800, , , CH1 SET serial stream
csr, REG, ch1_res_mem, 0x4000, rw, 32, 0x800, , , CH1 RES serial stream
csr, REG, ch2_set_mem, 0x6000, rw, 32, 0x800, , , CH2 SET serial stream
csr, REG, ch2_res_mem, 0x8000, rw, 32, 0x800, , , CH2 RES serial stream
# Block definition table
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
spi_master, REG, status, 0x0, rw, 32, 0x1, , , Status register
spi_master, REG, config1, 0x4, rw, 32, 0x1, , , Config 1 register
spi_master, REG, config2, 0x8, rw, 32, 0x1, , , Config 2 register
spi_master, REG, shift_out, 0xc, rw, 32, 0x1, , , Shift out register
spi_master, REG, shift_in, 0x10, rw, 32, 0x1, , , Shift in register
# Block definition table
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
onewire_master, REG, ctrl_sta, 0x0, rw, 32, 0x1, , , Control/status register
onewire_master, REG, cdr, 0x4, rw, 32, 0x1, , , Clock dividers register
# Block instances table
block_inst_name, block_def_name, res_def_name, offset, description
onewire_master, onewire_master, registers, 0x21000, OneWire master
spi_master, spi_master, registers, 0x22000, WB SPI master
csr, csr, registers, 0x30000, Control/status registers
# Reg roles table
reg_role, reg_name, block_def_name, args
#Encore Driver GEnerator version: 3.1
#LIF (Logical Interface) table definition
hw_mod_name, hw_lif_name, hw_lif_vers, edge_vers, bus, endian, description
FMC-FPG, fmc_fpg, 1.0.0-vme, 3.1, VME, BE, FMC Fast Pulse Generator
#Resources (Memory(BARs) - DMA - IRQ) table definition
res_def_name, type, res_no, args, description
registers, MEM, 0, addrspace=A24 dwidth=32 size=0x40000 dma=BLT|MBLT,
#Block table definition
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
onewire_master, REG, ctrl_sta, 0x0, rw, 32, 0x1, , , Control/status register
onewire_master, REG, cdr, 0x4, rw, 32, 0x1, , , Clock dividers register
#Block table definition
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
spi_master, REG, status, 0x0, r, 32, 0x1, , , Status register
spi_master, REG, config1, 0x4, rw, 32, 0x1, , , Config 1 register
spi_master, REG, config2, 0x8, rw, 32, 0x1, , , Config 2 register
spi_master, REG, shift_out, 0xc, rw, 32, 0x1, , , Shift out register
spi_master, REG, shift_in, 0x10, r, 32, 0x1, , , Shift in register
#Block table definition
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
ffpg_csr, REG, status, 0x0, r, 32, 0x1, , , Status register
ffpg_csr, REG, control, 0x4, rw, 32, 0x1, , , Control register
ffpg_csr, REG, vcxo_voltage, 0x8, rw, 32, 0x1, , , VCXO voltage
ffpg_csr, REG, clock_ratio_m1, 0xc, rw, 32, 0x1, , , Clock ratio minus 1
ffpg_csr, REG, ch1_delay_set, 0x10, rw, 32, 0x1, , , CH1 set delay
ffpg_csr, REG, ch1_delay_res, 0x14, rw, 32, 0x1, , , CH1 reset delay
ffpg_csr, REG, ch2_delay_set, 0x18, rw, 32, 0x1, , , CH2 set delay
ffpg_csr, REG, ch2_delay_res, 0x1c, rw, 32, 0x1, , , CH2 reset delay
ffpg_csr, REG, trig_threshold, 0x20, rw, 32, 0x1, , , Trigger threshold voltage
ffpg_csr, REG, overflow, 0x24, rw, 32, 0x1, , , Overflow
ffpg_csr, REG, ch1_trig_latency, 0x28, rw, 32, 0x1, , , CH1 trigger latency
ffpg_csr, REG, frequency, 0x2c, r, 32, 0x1, , , Clock frequency
ffpg_csr, REG, debug, 0x30, r, 32, 0x1, , , Debug register
ffpg_csr, REG, version, 0x34, r, 32, 0x1, , , FFPG version
ffpg_csr, REG, ch2_trig_latency, 0x38, rw, 32, 0x1, , , CH2 trigger latency
ffpg_csr, REG, fine_delay, 0x3c, rw, 32, 0x1, , , AD9512 OUT4 fine delay
ffpg_csr, REG, ch1_set_mem, 0x2000, rw, 32, 0x800, , , CH1 SET serial stream
ffpg_csr, REG, ch1_res_mem, 0x4000, rw, 32, 0x800, , , CH1 RES serial stream
ffpg_csr, REG, ch2_set_mem, 0x6000, rw, 32, 0x800, , , CH2 SET serial stream
ffpg_csr, REG, ch2_res_mem, 0x8000, rw, 32, 0x800, , , CH2 RES serial stream
#Block instances table definition
block_inst_name, block_def_name, res_def_name, offset, description
onewire_master, onewire_master, registers, 0x21000, OneWire master
spi_master, spi_master, registers, 0x22000, WB SPI master
csr, ffpg_csr, registers, 0x30000, Control/status registers
#Interrupt Controller (INTC) table definition
intc_name, type, reg_name, block_def_name, chained_intc_name, chained_intc_mask, args, description
#Register Roles table definition
reg_role, reg_name, block_def_name, args