V2 schematics review, January 2014

Reviewer:* T.Wlostowski
Commit:* 490f3b2f

General

Altium complains about missing files: FMC.Harness.
Missing title block contents (please use standard CERN EDA document template)
Make names consistent (Ux vs ICxx for ICs, etc.)
Clean up (wires over components, etc.)
Use one symbol for all power nets and ground nets. There is a bar and "earth" ground in use, same for the powers (bar, arrow, circle).
Make power net naming more precise. E.g. P3V3_CLEAN-> P3V3_AD9516, P3V3_PLL (in fact it powers the ADF4002 PD) -> P3V3_PD, P3V3CLK -> P3V3_AD9510.

U22: DE and \RE pins should be connected to P3V3D, otherwise the buffer will be permanently disabled.

PLL_REF_SEL goes nowhere. Since this pin is not needed, place a no-error marker.
Same for PD and \REFIN pins.
Net REF_CLK (25 MHz VCXO) - the name is a bit confusing, as there are multiple reference clocks in the design. Figure out a more precise name.
OUT0: place coupling caps close to the output of the PLL.
An explanation of the loop filter component values would be very appreciated (e.g. a note pointing to
Analog Device's simulation file)
Place labels with the default clock frequencies next to the PLL outputs.

Loop filter components: same as for the clock distribution PLL, explain the values or attach the AD simulation file and a link/note where to find it on the schematic.

Check the power dissipation of the P6V0 regulator - it's about 100-120 mA (corresponding to 0.6-0.8 W of power dissipation), so probably some extra cooling space will be needed on the PCB.

Why a dedicated comparator for the FPGA clock output? Wouldn't it be simpler to use an AC-coupled LVPECL output of IC13?
IC13: in AC-coupled mode, \CLK pin should be shorted with Vref and Vt pins.
IC13: check input level. Jitter-wise, ADCLK944 doesn't like slow edges in the
input signal (i.e. sine wave from the lowpass filter). Check "Clock inputs" section in the datasheet, page 9.
Cleanliness: loose net labels close to IC13.
IC19: for full scale DAC output the amplifier will produce ~4 Vpp (unless its output is source-terminated). This exceeds the input range of the clock fanout.
IC19: Match the output impedance of the amplifier to the filter (series resistor?).
R8: Shouldn't it be after C76/C23 (LVPECL is usually not terminated with DC-coupled 100 ohms)?
U11: Pin 11 (digital 3.3V) is connected to the analog power supply? Is this intended? Also, s/U/IC.

Are R4/C1 necessary if the ADC is connected already to the PD's lowpass filter output?

R15/R42: AFAIK in order to bias a bipolar LVTTL output, one should use small pulldown resistors (I used 470 ohm in the Fine Delay).
The pulse output will drive a rather small voltage on a 50 Ohm load (less than 1.5 V). Is this OK?

Unconnected SCL, SDA ports in the FMC connector
Add most important net names on the connections on the block diagram. This will make the design easier to follow.