FMC DAC 600M 12b 1cha DDS
Project description
The FMC DAC 600M 12b 1cha DDS board can be used to distribute RF signals over the WR network. The idea is shown below:
Together with the Simple PCIe FMC Carrier - SPEC makes a complete WR RF distribution node.
FMC DDS prototype board (version 0)*
Main Features
- Low-Pin Count FMC
- 14-bit 600MHz DAC with splitter and amplifier
- ADF4002 phase detector + programmable LPF + 16-bit ADC
- Clocking resources
- 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100 MHz (Silicon Labs Si570, freely usable)
- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
- 2x low-jitter frequency synthesizer/fanout
- 64kbit EEPROM (24AA64T-I/MC) connected for storing application parameters
- Miscellaneous
- On-board thermometer IC (DS18B20U+)
- 4-layer PCB
Project information
- Official production documentation (schematics, PCB, etc.): EDMS: EDA-03010
- Users
- Frequently Asked Questions
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Related projects
Contacts
Commercial producers
- Creotech, Poland
General question about project
-
Tomasz Włostowski - CERN
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Status
Date | Event |
01-04-2013 | Specification written |
15-04-2013 | Order received from CERN |
24-04-2013 | Boards received and powered on, no smoke so far. One bug fixed (no 3.3V routed to the VCXO and PLL) |
08-05-2013 | Proof-of-concept VHDL and software |
20-11-2013 | Specification of new version (v2) of the board including functionality of pulse generation with <50 ps RMS jitter and programmable fine delay |
22-11-2013 | LNLS put order for the v2 design |
29-12-2013 | Schematics of v2 at repository - ready for review |
20-01-2014 | Reviewed schematics of v2: Review-jan-2014 |
24-09-2014 | V2 Design released in EDMS |
24 September 2014