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Grzegorz Kasprowicz authored
Added die-casted shield + heatsink fixed schematic bugs after review added voltage level translator/buffer between FPGA and ADC improved signal integrity of clock circuit
6f1bd639
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| .. | ||
| ADC.SchDoc | ||
| ADC_Buffers.SchDoc | ||
| Clock_Distribution.SchDoc | ||
| EEPROM_Temp_LEDs.SchDoc | ||
| FMC_ADC_top.SchDoc | ||
| FMC_connector.SchDoc | ||
| Supply.SchDoc | ||
| Triggers.SchDoc |