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FMC ADC 250M 16b 4cha
Commit 6f1bd639 authored by Grzegorz Kasprowicz's avatar Grzegorz Kasprowicz
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improved symmetry of the channels. 

Added die-casted shield + heatsink
fixed schematic bugs after review
added voltage level translator/buffer between FPGA and ADC
improved signal integrity of clock circuit
parent c552b9a1
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Showing with 31 additions and 17 deletions
FMC_ADC_250.DsnWrk deleted 100644 → 0
View file @ c552b9a1
[ProjectGroup]
Version=1.0
[Project1]
ProjectPath=..\FMC ADC 125M 14b 1ch DAC 600M 14b 1ch\FMC_ADC_DAC.PrjPCB
[Project2]
ProjectPath=..\FmcAdc250M12b2cha\FmcAdc250M12b2cha_1_00_Altium\FmcAdc250M12b2cha.PrjPCB
[Project3]
ProjectPath=..\FMC-ADC-100m14b4cha\EDA-02063-V5-0.PrjPcb
[Project4]
ProjectPath=FMC_ADC_250M 16B 4ch\FMC_ADC_250M_16B_4ch.PrjPCB
[Project5]
ProjectPath=..\GEM_XDAQS\2D detector\GEM_FE_board_2D_PCB_v0.2\FE_board_2D.PrjPcb
fmc-adc-250m-16b-4cha/FMC_ADC_250M_16B_4ch.PrjPCB
View file @ 6f1bd639
[Design]
Version=1.0
HierarchyMode=0
HierarchyMode=2
ChannelRoomNamingStyle=0
OutputPath=
LogFolderPath=
......@@ -17,7 +17,7 @@ TemplateLocationPath=
PinSwapBy_Netlabel=1
PinSwapBy_Pin=1
AllowPortNetNames=0
AllowSheetEntryNetNames=1
AllowSheetEntryNetNames=0
AppendSheetNumberToLocalNets=0
NetlistSinglePinNets=0
DefaultConfiguration=
......@@ -25,10 +25,11 @@ UserID=0xFFFFFFFF
DefaultPcbProtel=1
DefaultPcbPcad=0
ReorderDocumentsOnCompile=1
NameNetsHierarchically=0
PowerPortNamesTakePriority=0
NameNetsHierarchically=1
PowerPortNamesTakePriority=1
PushECOToAnnotationFile=1
DItemRevisionGUID=
ReportSuppressedErrorsInMessages=0
[Document1]
DocumentPath=Schematics\FMC_ADC_top.SchDoc
......@@ -299,6 +300,10 @@ Variation40=Designator=TR1|UniqueId=\LKCJFEAM\GOQMEGCL|Kind=0|AlternatePart=
Variation41=Designator=TR?|UniqueId=\LKCJFEAM\CVXNBVWD|Kind=1|AlternatePart=
ParamVariationCount=0
[GeneratedDocument1]
DocumentPath=FMC_ADC_250M_16B_4ch_pcb.PcbDoc.htm
DItemRevisionGUID=
[PCBConfiguration1]
ReleaseItemId=
CurrentRevision=
......@@ -565,6 +570,12 @@ OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
PageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType18=PCBLIB Print
OutputName18=PCBLIB Prints
OutputDocumentPath18=
OutputVariantName18=
OutputDefault18=0
PageOptions18=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
[OutputGroup4]
Name=Assembly Outputs
......@@ -898,8 +909,23 @@ PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate
OutputType1=ExportSTEP
OutputName1=Export STEP
OutputDocumentPath1=
OutputVariantName1=
OutputVariantName1=[No Variations]
OutputDefault1=0
OutputType2=AutoCAD dwg/dxf PCB
OutputName2=AutoCAD dwg/dxf File PCB
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
OutputType3=AutoCAD dwg/dxf Schematic
OutputName3=AutoCAD dwg/dxf File Schematic
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0
OutputType4=ExportIDF
OutputName4=Export IDF
OutputDocumentPath4=
OutputVariantName4=
OutputDefault4=0
[Modification Levels]
Type1=1
......
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