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FMC ADC 100M 14b 4cha
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FMC ADC 100M 14b 4cha
Commits
9eca5c98
Commit
9eca5c98
authored
Feb 02, 2021
by
Tristan Gingold
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svec_ref_fmc_adc_100Ms: move to offset 0x4000
parent
5f61c4fb
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4 changed files
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21 additions
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21 deletions
+21
-21
svec_ref_fmc_adc_100Ms_mmap.cheby
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby
+4
-4
svec_ref_fmc_adc_100Ms_mmap.vhd
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.vhd
+11
-11
svec_ref_fmc_adc_100Ms_mmap.v
hdl/testbench/include/svec_ref_fmc_adc_100Ms_mmap.v
+4
-4
svec_ref_fmc_adc_100Ms.vhd
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
+2
-2
No files found.
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.cheby
View file @
9eca5c98
...
...
@@ -6,14 +6,14 @@ memory-map:
name: svec_ref_fmc_adc_100m_mmap
bus: wb-32-be
description: SPEC FMC-ADC-100M memory map
size: 0x
8
000
size: 0x
10
000
x-hdl:
busgroup: True
pipeline: wr,rd
children:
- submap:
name: metadata
address: 0x
2
000
address: 0x
4
000
size: 0x40
interface: wb-32-be
x-hdl:
...
...
@@ -21,11 +21,11 @@ memory-map:
description: a ROM containing the application metadata
- submap:
name: fmc1_adc_mezzanine
address: 0x
4
000
address: 0x
6
000
description: FMC ADC Mezzanine slot 1
filename: fmc_adc_mezzanine_mmap.cheby
- submap:
name: fmc2_adc_mezzanine
address: 0x
6
000
address: 0x
8
000
description: FMC ADC Mezzanine slot 2
filename: fmc_adc_mezzanine_mmap.cheby
hdl/cheby/svec_ref_fmc_adc_100Ms_mmap.vhd
View file @
9eca5c98
...
...
@@ -32,7 +32,7 @@ entity svec_ref_fmc_adc_100m_mmap is
end
svec_ref_fmc_adc_100m_mmap
;
architecture
syn
of
svec_ref_fmc_adc_100m_mmap
is
signal
adr_int
:
std_logic_vector
(
1
4
downto
2
);
signal
adr_int
:
std_logic_vector
(
1
5
downto
2
);
signal
rd_req_int
:
std_logic
;
signal
wr_req_int
:
std_logic
;
signal
rd_ack_int
:
std_logic
;
...
...
@@ -63,7 +63,7 @@ architecture syn of svec_ref_fmc_adc_100m_mmap is
signal
fmc2_adc_mezzanine_wack
:
std_logic
;
signal
fmc2_adc_mezzanine_rack
:
std_logic
;
signal
rd_req_d0
:
std_logic
;
signal
rd_adr_d0
:
std_logic_vector
(
1
4
downto
2
);
signal
rd_adr_d0
:
std_logic_vector
(
1
5
downto
2
);
signal
rd_ack_d0
:
std_logic
;
signal
rd_dat_d0
:
std_logic_vector
(
31
downto
0
);
signal
wr_req_d0
:
std_logic
;
...
...
@@ -73,7 +73,7 @@ architecture syn of svec_ref_fmc_adc_100m_mmap is
begin
-- WB decode signals
adr_int
<=
wb_i
.
adr
(
1
4
downto
2
);
adr_int
<=
wb_i
.
adr
(
1
5
downto
2
);
wb_en
<=
wb_i
.
cyc
and
wb_i
.
stb
;
process
(
clk_i
)
begin
...
...
@@ -196,16 +196,16 @@ begin
metadata_we
<=
'0'
;
fmc1_adc_mezzanine_we
<=
'0'
;
fmc2_adc_mezzanine_we
<=
'0'
;
case
rd_adr_d0
(
1
4
downto
13
)
is
when
"01"
=>
case
rd_adr_d0
(
1
5
downto
13
)
is
when
"01
0
"
=>
-- Submap metadata
metadata_we
<=
wr_req_d0
;
wr_ack_d0
<=
metadata_wack
;
when
"
10
"
=>
when
"
011
"
=>
-- Submap fmc1_adc_mezzanine
fmc1_adc_mezzanine_we
<=
wr_req_d0
;
wr_ack_d0
<=
fmc1_adc_mezzanine_wack
;
when
"1
1
"
=>
when
"1
00
"
=>
-- Submap fmc2_adc_mezzanine
fmc2_adc_mezzanine_we
<=
wr_req_d0
;
wr_ack_d0
<=
fmc2_adc_mezzanine_wack
;
...
...
@@ -221,18 +221,18 @@ begin
metadata_re
<=
'0'
;
fmc1_adc_mezzanine_re
<=
'0'
;
fmc2_adc_mezzanine_re
<=
'0'
;
case
rd_adr_d0
(
1
4
downto
13
)
is
when
"01"
=>
case
rd_adr_d0
(
1
5
downto
13
)
is
when
"01
0
"
=>
-- Submap metadata
metadata_re
<=
rd_req_d0
;
rd_dat_d0
<=
metadata_i
.
dat
;
rd_ack_d0
<=
metadata_rack
;
when
"
10
"
=>
when
"
011
"
=>
-- Submap fmc1_adc_mezzanine
fmc1_adc_mezzanine_re
<=
rd_req_d0
;
rd_dat_d0
<=
fmc1_adc_mezzanine_i
.
dat
;
rd_ack_d0
<=
fmc1_adc_mezzanine_rack
;
when
"1
1
"
=>
when
"1
00
"
=>
-- Submap fmc2_adc_mezzanine
fmc2_adc_mezzanine_re
<=
rd_req_d0
;
rd_dat_d0
<=
fmc2_adc_mezzanine_i
.
dat
;
...
...
hdl/testbench/include/svec_ref_fmc_adc_100Ms_mmap.v
View file @
9eca5c98
...
...
@@ -2,10 +2,10 @@
//
// SPDX-License-Identifier: CC0-1.0
`define
SVEC_REF_FMC_ADC_100M_MMAP_SIZE
32768
`define
ADDR_SVEC_REF_FMC_ADC_100M_MMAP_METADATA
'
h
2
000
`define
SVEC_REF_FMC_ADC_100M_MMAP_SIZE
65536
`define
ADDR_SVEC_REF_FMC_ADC_100M_MMAP_METADATA
'
h
4
000
`define
SVEC_REF_FMC_ADC_100M_MMAP_METADATA_SIZE 64
`define
ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE
'
h
4
000
`define
ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE
'
h
6
000
`define
SVEC_REF_FMC_ADC_100M_MMAP_FMC1_ADC_MEZZANINE_SIZE 8192
`define
ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE
'
h
6
000
`define
ADDR_SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE
'
h
8
000
`define
SVEC_REF_FMC_ADC_100M_MMAP_FMC2_ADC_MEZZANINE_SIZE 8192
hdl/top/svec_ref_design/svec_ref_fmc_adc_100Ms.vhd
View file @
9eca5c98
...
...
@@ -240,7 +240,7 @@ architecture arch of svec_ref_fmc_adc_100Ms is
constant
c_WB_SLAVE_FMC1_ADC
:
integer
:
=
2
;
-- FMC slot 2 ADC mezzanine
-- Convention metadata base address
constant
c_METADATA_ADDR
:
t_wishbone_address
:
=
x"0000_
2
000"
;
constant
c_METADATA_ADDR
:
t_wishbone_address
:
=
x"0000_
4
000"
;
------------------------------------------------------------------------------
-- Signals declaration
...
...
@@ -475,7 +475,7 @@ begin -- architecture arch
generic
map
(
g_VENDOR_ID
=>
x"0000_10DC"
,
g_DEVICE_ID
=>
x"4144_4302"
,
-- "ADC2"
g_VERSION
=>
x"0500_000
0
"
,
g_VERSION
=>
x"0500_000
2
"
,
g_CAPABILITIES
=>
x"0000_0000"
,
g_COMMIT_ID
=>
(
others
=>
'0'
))
port
map
(
...
...
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