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FMC ADC 100M 14b 4cha
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FMC ADC 100M 14b 4cha
Commits
4da0fe72
Commit
4da0fe72
authored
Mar 31, 2016
by
Dimitris Lampridis
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Merge branch 'dlamprid-dev' into dlamprid-mshotmem
parents
2213467d
523e8a0a
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15 changed files
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394 additions
and
1969 deletions
+394
-1969
.gitignore
.gitignore
+3
-0
Makefile
hdl/spec/sim/Makefile
+0
-1512
Manifest.py
hdl/spec/sim/Manifest.py
+8
-3
hdlmake.sh
hdl/spec/sim/hdlmake.sh
+0
-1
ddr3_parameters.vh
hdl/spec/sim/sim_models/2048Mb_ddr3/ddr3_parameters.vh
+2
-1
spec.do
hdl/spec/sim/spec.do
+11
-10
wave.do
hdl/spec/sim/wave.do
+5
-5
wave_adc_core.do
hdl/spec/sim/wave_adc_core.do
+155
-157
wave_datapath.do
hdl/spec/sim/wave_datapath.do
+52
-53
wave_end_acq_irq.do
hdl/spec/sim/wave_end_acq_irq.do
+71
-75
wave_multishot.do
hdl/spec/sim/wave_multishot.do
+56
-56
wave_onewire.do
hdl/spec/sim/wave_onewire.do
+12
-39
wave_reset.do
hdl/spec/sim/wave_reset.do
+0
-1
wave_serdes.do
hdl/spec/sim/wave_serdes.do
+9
-9
wave_wb_buses.do
hdl/spec/sim/wave_wb_buses.do
+10
-47
No files found.
.gitignore
View file @
4da0fe72
hdl/ip_cores/.lso
hdl/ip_cores/_xmsgs
hdl/*/sim/transcript
hdl/*/sim/vsim.wlf
hdl/*/sim/Makefile
hdl/*/sim/modelsim.ini
hdl/*/sim/work/
hdl/*/sim/fifo_generator_v6_1/
...
...
hdl/spec/sim/Makefile
deleted
100644 → 0
View file @
2213467d
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD
:=
$(
shell
pwd
)
MODELSIM_INI_PATH
:=
/opt/modelsim_10.0c/modeltech
VCOM_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VSIM_FLAGS
:=
VLOG_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VERILOG_SRC
:=
sim_models/2048Mb_ddr3/ddr3.v
\
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
\
VERILOG_OBJ
:=
work/ddr3/.ddr3_v
\
work/sockit_owm/.sockit_owm_v
\
work/spi_clgen/.spi_clgen_v
\
work/spi_shift/.spi_shift_v
\
work/spi_top/.spi_top_v
\
work/lm32_allprofiles/.lm32_allprofiles_v
\
work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v
\
work/jtag_cores/.jtag_cores_v
\
work/lm32_adder/.lm32_adder_v
\
work/lm32_addsub/.lm32_addsub_v
\
work/lm32_logic_op/.lm32_logic_op_v
\
work/lm32_shifter/.lm32_shifter_v
\
work/lm32_multiplier/.lm32_multiplier_v
\
work/jtag_tap/.jtag_tap_v
\
VHDL_SRC
:=
testbench/util.vhd
\
testbench/textutil.vhd
\
testbench/mem_model.vhd
\
testbench/cmd_router.vhd
\
testbench/tb_spec.vhd
\
testbench/cmd_router1.vhd
\
../../ip_cores/adc_sync_fifo.vhd
\
../../ip_cores/multishot_dpram.vhd
\
../../ip_cores/wb_ddr_fifo.vhd
\
../../ip_cores/adc_serdes.vhd
\
../../ip_cores/monostable/monostable_rtl.vhd
\
../../ip_cores/utils/utils_pkg.vhd
\
../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd
\
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
\
../rtl/carrier_csr.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
\
../../ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
\
../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd
\
../../adc/rtl/fmc_adc_mezzanine_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
\
../rtl/sdb_meta_pkg.vhd
\
../../adc/rtl/fmc_adc_100Ms_csr.vhd
\
../../adc/rtl/fmc_adc_eic.vhd
\
../../adc/rtl/offset_gain_s.vhd
\
../../ip_cores/timetag_core/rtl/timetag_core_regs.vhd
\
../../ip_cores/timetag_core/rtl/timetag_core.vhd
\
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
\
testbench/gn412x_bfm.vhd
\
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd
\
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
\
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
\
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
\
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
\
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
\
../../ip_cores/general-cores/modules/common/gc_reset.vhd
\
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
\
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
\
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
\
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
\
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
\
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
\
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd
\
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd
\
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
\
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd
\
../../adc/rtl/fmc_adc_100Ms_core.vhd
\
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
\
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
\
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd
\
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd
\
../../adc/rtl/fmc_adc_mezzanine.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
\
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
\
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
\
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
\
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
\
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
\
../rtl/dma_eic.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
\
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
\
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd
\
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd
\
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd
\
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
\
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd
\
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd
\
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd
\
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd
\
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd
\
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd
\
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd
\
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
\
../rtl/spec_top_fmc_adc_100Ms.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd
\
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd
\
VHDL_OBJ
:=
work/util/.util_vhd
\
work/textutil/.textutil_vhd
\
work/mem_model/.mem_model_vhd
\
work/cmd_router/.cmd_router_vhd
\
work/tb_spec/.tb_spec_vhd
\
work/cmd_router1/.cmd_router1_vhd
\
work/adc_sync_fifo/.adc_sync_fifo_vhd
\
work/multishot_dpram/.multishot_dpram_vhd
\
work/wb_ddr_fifo/.wb_ddr_fifo_vhd
\
work/adc_serdes/.adc_serdes_vhd
\
work/monostable_rtl/.monostable_rtl_vhd
\
work/utils_pkg/.utils_pkg_vhd
\
work/ext_pulse_sync_rtl/.ext_pulse_sync_rtl_vhd
\
work/genram_pkg/.genram_pkg_vhd
\
work/carrier_csr/.carrier_csr_vhd
\
work/wbgen2_pkg/.wbgen2_pkg_vhd
\
work/timetag_core_pkg/.timetag_core_pkg_vhd
\
work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg_vhd
\
work/fmc_adc_mezzanine_pkg/.fmc_adc_mezzanine_pkg_vhd
\
work/wishbone_pkg/.wishbone_pkg_vhd
\
work/sdb_meta_pkg/.sdb_meta_pkg_vhd
\
work/fmc_adc_100Ms_csr/.fmc_adc_100Ms_csr_vhd
\
work/fmc_adc_eic/.fmc_adc_eic_vhd
\
work/offset_gain_s/.offset_gain_s_vhd
\
work/timetag_core_regs/.timetag_core_regs_vhd
\
work/timetag_core/.timetag_core_vhd
\
work/gencores_pkg/.gencores_pkg_vhd
\
work/gn412x_bfm/.gn412x_bfm_vhd
\
work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg_vhd
\
work/gc_crc_gen/.gc_crc_gen_vhd
\
work/gc_moving_average/.gc_moving_average_vhd
\
work/gc_extend_pulse/.gc_extend_pulse_vhd
\
work/gc_delay_gen/.gc_delay_gen_vhd
\
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd
\
work/gc_reset/.gc_reset_vhd
\
work/gc_serial_dac/.gc_serial_dac_vhd
\
work/gc_sync_ffs/.gc_sync_ffs_vhd
\
work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd
\
work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd
\
work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2_vhd
\
work/gc_frequency_meter/.gc_frequency_meter_vhd
\
work/gc_rr_arbiter/.gc_rr_arbiter_vhd
\
work/gc_prio_encoder/.gc_prio_encoder_vhd
\
work/gc_word_packer/.gc_word_packer_vhd
\
work/gc_big_adder/.gc_big_adder_vhd
\
work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core_vhd
\
work/memory_loader_pkg/.memory_loader_pkg_vhd
\
work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd
\
work/inferred_sync_fifo/.inferred_sync_fifo_vhd
\
work/inferred_async_fifo/.inferred_async_fifo_vhd
\
work/fmc_adc_mezzanine/.fmc_adc_mezzanine_vhd
\
work/generic_dpram/.generic_dpram_vhd
\
work/generic_dpram_sameclock/.generic_dpram_sameclock_vhd
\
work/generic_dpram_dualclock/.generic_dpram_dualclock_vhd
\
work/generic_simple_dpram/.generic_simple_dpram_vhd
\
work/generic_spram/.generic_spram_vhd
\
work/gc_shiftreg/.gc_shiftreg_vhd
\
work/generic_async_fifo/.generic_async_fifo_vhd
\
work/generic_sync_fifo/.generic_sync_fifo_vhd
\
work/wb_async_bridge/.wb_async_bridge_vhd
\
work/xwb_async_bridge/.xwb_async_bridge_vhd
\
work/wb_onewire_master/.wb_onewire_master_vhd
\
work/xwb_onewire_master/.xwb_onewire_master_vhd
\
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd
\
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd
\
work/i2c_master_top/.i2c_master_top_vhd
\
work/wb_i2c_master/.wb_i2c_master_vhd
\
work/xwb_i2c_master/.xwb_i2c_master_vhd
\
work/xwb_bus_fanout/.xwb_bus_fanout_vhd
\
work/xwb_dpram/.xwb_dpram_vhd
\
work/wb_gpio_port/.wb_gpio_port_vhd
\
work/xwb_gpio_port/.xwb_gpio_port_vhd
\
work/wb_tics/.wb_tics_vhd
\
work/xwb_tics/.xwb_tics_vhd
\
work/uart_async_rx/.uart_async_rx_vhd
\
work/uart_async_tx/.uart_async_tx_vhd
\
work/uart_baud_gen/.uart_baud_gen_vhd
\
work/simple_uart_pkg/.simple_uart_pkg_vhd
\
work/simple_uart_wb/.simple_uart_wb_vhd
\
work/wb_simple_uart/.wb_simple_uart_vhd
\
work/xwb_simple_uart/.xwb_simple_uart_vhd
\
work/vic_prio_enc/.vic_prio_enc_vhd
\
work/wb_slave_vic/.wb_slave_vic_vhd
\
work/wb_vic/.wb_vic_vhd
\
work/xwb_vic/.xwb_vic_vhd
\
work/wb_spi/.wb_spi_vhd
\
work/xwb_spi/.xwb_spi_vhd
\
work/sdb_rom/.sdb_rom_vhd
\
work/xwb_crossbar/.xwb_crossbar_vhd
\
work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd
\
work/wb_irq_pkg/.wb_irq_pkg_vhd
\
work/irqm_core/.irqm_core_vhd
\
work/wb_irq_lm32/.wb_irq_lm32_vhd
\
work/wb_irq_slave/.wb_irq_slave_vhd
\
work/wb_irq_master/.wb_irq_master_vhd
\
work/wb_irq_timer/.wb_irq_timer_vhd
\
work/xwb_lm32/.xwb_lm32_vhd
\
work/lm32_dp_ram/.lm32_dp_ram_vhd
\
work/lm32_ram/.lm32_ram_vhd
\
work/wb_slave_adapter/.wb_slave_adapter_vhd
\
work/xwb_clock_crossing/.xwb_clock_crossing_vhd
\
work/xwb_dma/.xwb_dma_vhd
\
work/xwb_streamer/.xwb_streamer_vhd
\
work/wb_serial_lcd/.wb_serial_lcd_vhd
\
work/wb_spi_flash/.wb_spi_flash_vhd
\
work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg_vhd
\
work/simple_pwm_wb/.simple_pwm_wb_vhd
\
work/wb_simple_pwm/.wb_simple_pwm_vhd
\
work/xwb_simple_pwm/.xwb_simple_pwm_vhd
\
work/wbgen2_dpssram/.wbgen2_dpssram_vhd
\
work/wbgen2_eic/.wbgen2_eic_vhd
\
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd
\
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd
\
work/dma_eic/.dma_eic_vhd
\
work/xloader_registers_pkg/.xloader_registers_pkg_vhd
\
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd
\
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd
\
work/xloader_wb/.xloader_wb_vhd
\
work/ddr3_ctrl/.ddr3_ctrl_vhd
\
work/ddr3_ctrl_wb/.ddr3_ctrl_wb_vhd
\
work/ddr3_ctrl_wrapper_pkg/.ddr3_ctrl_wrapper_pkg_vhd
\
work/ddr3_ctrl_wrapper/.ddr3_ctrl_wrapper_vhd
\
work/gn4124_core_pkg/.gn4124_core_pkg_vhd
\
work/ddr3_ctrl_spec_bank3_64b_32b/.ddr3_ctrl_spec_bank3_64b_32b_vhd
\
work/memc3_infrastructure/.memc3_infrastructure_vhd
\
work/memc3_wrapper/.memc3_wrapper_vhd
\
work/iodrp_controller/.iodrp_controller_vhd
\
work/iodrp_mcb_controller/.iodrp_mcb_controller_vhd
\
work/mcb_raw_wrapper/.mcb_raw_wrapper_vhd
\
work/mcb_soft_calibration_top/.mcb_soft_calibration_top_vhd
\
work/mcb_soft_calibration/.mcb_soft_calibration_vhd
\
work/dma_controller/.dma_controller_vhd
\
work/dma_controller_wb_slave/.dma_controller_wb_slave_vhd
\
work/l2p_arbiter/.l2p_arbiter_vhd
\
work/l2p_dma_master/.l2p_dma_master_vhd
\
work/p2l_decode32/.p2l_decode32_vhd
\
work/p2l_dma_master/.p2l_dma_master_vhd
\
work/wbmaster32/.wbmaster32_vhd
\
work/gn4124_core/.gn4124_core_vhd
\
work/spec_top_fmc_adc_100Ms/.spec_top_fmc_adc_100Ms_vhd
\
work/l2p_ser/.l2p_ser_vhd
\
work/p2l_des/.p2l_des_vhd
\
work/serdes_1_to_n_clk_pll_s2_diff/.serdes_1_to_n_clk_pll_s2_diff_vhd
\
work/serdes_1_to_n_data_s2_se/.serdes_1_to_n_data_s2_se_vhd
\
work/serdes_n_to_1_s2_diff/.serdes_n_to_1_s2_diff_vhd
\
work/serdes_n_to_1_s2_se/.serdes_n_to_1_s2_se_vhd
\
work/pulse_sync_rtl/.pulse_sync_rtl_vhd
\
LIBS
:=
work
LIB_IND
:=
work/.work
## rules #################################
sim
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
$(VHDL_OBJ)
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
clean
:
rm
-rf
./modelsim.ini
$(LIBS)
.PHONY
:
clean
work/.work
:
(
vlib work
&&
vmap
-modelsimini
modelsim.ini work
&&
touch
work/.work
)||
rm
-rf
work
work/ddr3/.ddr3_v
:
sim_models/2048Mb_ddr3/ddr3.v sim_models/2048Mb_ddr3/ddr3_parameters.vh
vlog
-work
work
$(VLOG_FLAGS)
+incdir+sim_models/2048Mb_ddr3 +incdir+sim_models/2048Mb_ddr3 +define+sg15E +define+x16
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/sockit_owm/.sockit_owm_v
:
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/spi_clgen/.spi_clgen_v
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/spi_shift/.spi_shift_v
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/spi_top/.spi_top_v
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v ../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_spi
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_allprofiles/.lm32_allprofiles_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/jtag_cores/.jtag_cores_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_adder/.lm32_adder_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_addsub/.lm32_addsub_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_logic_op/.lm32_logic_op_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_shifter/.lm32_shifter_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_multiplier/.lm32_multiplier_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v ../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/jtag_tap/.jtag_tap_v
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
vlog
-work
work
$(VLOG_FLAGS)
+incdir+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/util/.util_vhd
:
testbench/util.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/textutil/.textutil_vhd
:
testbench/textutil.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/textutil/.textutil
:
\
work/util/.util
work/mem_model/.mem_model_vhd
:
testbench/mem_model.vhd
vcom
$(VCOM_FLAGS)
-87
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/cmd_router/.cmd_router_vhd
:
testbench/cmd_router.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/cmd_router/.cmd_router
:
\
work/util/.util
\
work/textutil/.textutil
work/tb_spec/.tb_spec_vhd
:
testbench/tb_spec.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/tb_spec/.tb_spec
:
\
work/util/.util
\
work/textutil/.textutil
work/cmd_router1/.cmd_router1_vhd
:
testbench/cmd_router1.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/cmd_router1/.cmd_router1
:
\
work/util/.util
\
work/textutil/.textutil
work/adc_sync_fifo/.adc_sync_fifo_vhd
:
../../ip_cores/adc_sync_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/multishot_dpram/.multishot_dpram_vhd
:
../../ip_cores/multishot_dpram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_ddr_fifo/.wb_ddr_fifo_vhd
:
../../ip_cores/wb_ddr_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/adc_serdes/.adc_serdes_vhd
:
../../ip_cores/adc_serdes.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/monostable_rtl/.monostable_rtl_vhd
:
../../ip_cores/monostable/monostable_rtl.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/utils_pkg/.utils_pkg_vhd
:
../../ip_cores/utils/utils_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/ext_pulse_sync_rtl/.ext_pulse_sync_rtl_vhd
:
../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/ext_pulse_sync_rtl/.ext_pulse_sync_rtl
:
\
work/utils_pkg/.utils_pkg
work/genram_pkg/.genram_pkg_vhd
:
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/carrier_csr/.carrier_csr_vhd
:
../rtl/carrier_csr.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_pkg/.wbgen2_pkg_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/timetag_core_pkg/.timetag_core_pkg_vhd
:
../../ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg_vhd
:
../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg
:
\
work/timetag_core_pkg/.timetag_core_pkg
work/fmc_adc_mezzanine_pkg/.fmc_adc_mezzanine_pkg_vhd
:
../../adc/rtl/fmc_adc_mezzanine_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fmc_adc_mezzanine_pkg/.fmc_adc_mezzanine_pkg
:
\
work/timetag_core_pkg/.timetag_core_pkg
work/wishbone_pkg/.wishbone_pkg_vhd
:
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wishbone_pkg/.wishbone_pkg
:
\
work/genram_pkg/.genram_pkg
work/sdb_meta_pkg/.sdb_meta_pkg_vhd
:
../rtl/sdb_meta_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/sdb_meta_pkg/.sdb_meta_pkg
:
\
work/wishbone_pkg/.wishbone_pkg
work/fmc_adc_100Ms_csr/.fmc_adc_100Ms_csr_vhd
:
../../adc/rtl/fmc_adc_100Ms_csr.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fmc_adc_eic/.fmc_adc_eic_vhd
:
../../adc/rtl/fmc_adc_eic.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fmc_adc_eic/.fmc_adc_eic
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/offset_gain_s/.offset_gain_s_vhd
:
../../adc/rtl/offset_gain_s.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/timetag_core_regs/.timetag_core_regs_vhd
:
../../ip_cores/timetag_core/rtl/timetag_core_regs.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/timetag_core/.timetag_core_vhd
:
../../ip_cores/timetag_core/rtl/timetag_core.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/timetag_core/.timetag_core
:
\
work/timetag_core_pkg/.timetag_core_pkg
work/gencores_pkg/.gencores_pkg_vhd
:
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gencores_pkg/.gencores_pkg
:
\
work/genram_pkg/.genram_pkg
work/gn412x_bfm/.gn412x_bfm_vhd
:
testbench/gn412x_bfm.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gn412x_bfm/.gn412x_bfm
:
\
work/util/.util
\
work/mem_model/.mem_model
\
work/textutil/.textutil
work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg_vhd
:
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_crc_gen/.gc_crc_gen_vhd
:
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_crc_gen/.gc_crc_gen
:
\
work/gencores_pkg/.gencores_pkg
work/gc_moving_average/.gc_moving_average_vhd
:
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_moving_average/.gc_moving_average
:
\
work/gencores_pkg/.gencores_pkg
work/gc_extend_pulse/.gc_extend_pulse_vhd
:
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_extend_pulse/.gc_extend_pulse
:
\
work/genram_pkg/.genram_pkg
\
work/gencores_pkg/.gencores_pkg
work/gc_delay_gen/.gc_delay_gen_vhd
:
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_delay_gen/.gc_delay_gen
:
\
work/gencores_pkg/.gencores_pkg
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd
:
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_dual_pi_controller/.gc_dual_pi_controller
:
\
work/gencores_pkg/.gencores_pkg
work/gc_reset/.gc_reset_vhd
:
../../ip_cores/general-cores/modules/common/gc_reset.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_serial_dac/.gc_serial_dac_vhd
:
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_sync_ffs/.gc_sync_ffs_vhd
:
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd
:
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_arbitrated_mux/.gc_arbitrated_mux
:
\
work/genram_pkg/.genram_pkg
\
work/gencores_pkg/.gencores_pkg
work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd
:
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_pulse_synchronizer/.gc_pulse_synchronizer
:
\
work/gencores_pkg/.gencores_pkg
work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2_vhd
:
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_pulse_synchronizer2/.gc_pulse_synchronizer2
:
\
work/gencores_pkg/.gencores_pkg
work/gc_frequency_meter/.gc_frequency_meter_vhd
:
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_frequency_meter/.gc_frequency_meter
:
\
work/gencores_pkg/.gencores_pkg
work/gc_rr_arbiter/.gc_rr_arbiter_vhd
:
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_prio_encoder/.gc_prio_encoder_vhd
:
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_word_packer/.gc_word_packer_vhd
:
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_word_packer/.gc_word_packer
:
\
work/genram_pkg/.genram_pkg
work/gc_big_adder/.gc_big_adder_vhd
:
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_big_adder/.gc_big_adder
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core_vhd
:
../../adc/rtl/fmc_adc_100Ms_core.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fmc_adc_100Ms_core/.fmc_adc_100Ms_core
:
\
work/genram_pkg/.genram_pkg
\
work/timetag_core_pkg/.timetag_core_pkg
work/memory_loader_pkg/.memory_loader_pkg_vhd
:
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/memory_loader_pkg/.memory_loader_pkg
:
\
work/genram_pkg/.genram_pkg
work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd
:
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_shiftreg_fifo/.generic_shiftreg_fifo
:
\
work/genram_pkg/.genram_pkg
work/inferred_sync_fifo/.inferred_sync_fifo_vhd
:
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/inferred_sync_fifo/.inferred_sync_fifo
:
\
work/genram_pkg/.genram_pkg
work/inferred_async_fifo/.inferred_async_fifo_vhd
:
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/inferred_async_fifo/.inferred_async_fifo
:
\
work/genram_pkg/.genram_pkg
work/fmc_adc_mezzanine/.fmc_adc_mezzanine_vhd
:
../../adc/rtl/fmc_adc_mezzanine.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/fmc_adc_mezzanine/.fmc_adc_mezzanine
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/timetag_core_pkg/.timetag_core_pkg
\
work/fmc_adc_100Ms_core_pkg/.fmc_adc_100Ms_core_pkg
work/generic_dpram/.generic_dpram_vhd
:
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_dpram/.generic_dpram
:
\
work/genram_pkg/.genram_pkg
\
work/memory_loader_pkg/.memory_loader_pkg
work/generic_dpram_sameclock/.generic_dpram_sameclock_vhd
:
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_dpram_sameclock/.generic_dpram_sameclock
:
\
work/genram_pkg/.genram_pkg
\
work/memory_loader_pkg/.memory_loader_pkg
work/generic_dpram_dualclock/.generic_dpram_dualclock_vhd
:
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_dpram_dualclock/.generic_dpram_dualclock
:
\
work/genram_pkg/.genram_pkg
\
work/memory_loader_pkg/.memory_loader_pkg
work/generic_simple_dpram/.generic_simple_dpram_vhd
:
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_simple_dpram/.generic_simple_dpram
:
\
work/genram_pkg/.genram_pkg
\
work/memory_loader_pkg/.memory_loader_pkg
work/generic_spram/.generic_spram_vhd
:
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_spram/.generic_spram
:
\
work/genram_pkg/.genram_pkg
work/gc_shiftreg/.gc_shiftreg_vhd
:
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gc_shiftreg/.gc_shiftreg
:
\
work/genram_pkg/.genram_pkg
work/generic_async_fifo/.generic_async_fifo_vhd
:
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_async_fifo/.generic_async_fifo
:
\
work/genram_pkg/.genram_pkg
work/generic_sync_fifo/.generic_sync_fifo_vhd
:
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/generic_sync_fifo/.generic_sync_fifo
:
\
work/genram_pkg/.genram_pkg
work/wb_async_bridge/.wb_async_bridge_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_async_bridge/.wb_async_bridge
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
work/xwb_async_bridge/.xwb_async_bridge_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_async_bridge/.xwb_async_bridge
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_onewire_master/.wb_onewire_master_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_onewire_master/.wb_onewire_master
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
work/xwb_onewire_master/.xwb_onewire_master_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_onewire_master/.xwb_onewire_master
:
\
work/wishbone_pkg/.wishbone_pkg
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/i2c_master_top/.i2c_master_top_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_i2c_master/.wb_i2c_master_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_i2c_master/.wb_i2c_master
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_i2c_master/.xwb_i2c_master_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_i2c_master/.xwb_i2c_master
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_bus_fanout/.xwb_bus_fanout_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_bus_fanout/.xwb_bus_fanout
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_dpram/.xwb_dpram_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_dpram/.xwb_dpram
:
\
work/genram_pkg/.genram_pkg
\
work/wishbone_pkg/.wishbone_pkg
work/wb_gpio_port/.wb_gpio_port_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_gpio_port/.wb_gpio_port
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
work/xwb_gpio_port/.xwb_gpio_port_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_gpio_port/.xwb_gpio_port
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_tics/.wb_tics_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_tics/.wb_tics
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_tics/.xwb_tics_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_tics/.xwb_tics
:
\
work/wishbone_pkg/.wishbone_pkg
work/uart_async_rx/.uart_async_rx_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/uart_async_tx/.uart_async_tx_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/uart_baud_gen/.uart_baud_gen_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/simple_uart_pkg/.simple_uart_pkg_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/simple_uart_wb/.simple_uart_wb_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/simple_uart_wb/.simple_uart_wb
:
\
work/simple_uart_pkg/.simple_uart_pkg
work/wb_simple_uart/.wb_simple_uart_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_simple_uart/.wb_simple_uart
:
\
work/genram_pkg/.genram_pkg
\
work/wishbone_pkg/.wishbone_pkg
\
work/simple_uart_pkg/.simple_uart_pkg
work/xwb_simple_uart/.xwb_simple_uart_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_simple_uart/.xwb_simple_uart
:
\
work/wishbone_pkg/.wishbone_pkg
work/vic_prio_enc/.vic_prio_enc_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_slave_vic/.wb_slave_vic_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_slave_vic/.wb_slave_vic
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/wb_vic/.wb_vic_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_vic/.wb_vic
:
\
work/genram_pkg/.genram_pkg
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_vic/.xwb_vic_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_vic/.xwb_vic
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_spi/.wb_spi_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_spi/.wb_spi
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_spi/.xwb_spi_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_spi/.xwb_spi
:
\
work/wishbone_pkg/.wishbone_pkg
work/sdb_rom/.sdb_rom_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/sdb_rom/.sdb_rom
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_crossbar/.xwb_crossbar_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_crossbar/.xwb_crossbar
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_sdb_crossbar/.xwb_sdb_crossbar
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_irq_pkg/.wb_irq_pkg_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_irq_pkg/.wb_irq_pkg
:
\
work/wishbone_pkg/.wishbone_pkg
work/irqm_core/.irqm_core_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/irqm_core/.irqm_core
:
\
work/wb_irq_pkg/.wb_irq_pkg
\
work/genram_pkg/.genram_pkg
\
work/wishbone_pkg/.wishbone_pkg
work/wb_irq_lm32/.wb_irq_lm32_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_irq_lm32/.wb_irq_lm32
:
\
work/wb_irq_pkg/.wb_irq_pkg
\
work/wishbone_pkg/.wishbone_pkg
work/wb_irq_slave/.wb_irq_slave_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_irq_slave/.wb_irq_slave
:
\
work/wb_irq_pkg/.wb_irq_pkg
\
work/genram_pkg/.genram_pkg
\
work/wishbone_pkg/.wishbone_pkg
work/wb_irq_master/.wb_irq_master_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_irq_master/.wb_irq_master
:
\
work/wb_irq_pkg/.wb_irq_pkg
\
work/genram_pkg/.genram_pkg
\
work/wishbone_pkg/.wishbone_pkg
work/wb_irq_timer/.wb_irq_timer_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_irq_timer/.wb_irq_timer
:
\
work/wb_irq_pkg/.wb_irq_pkg
\
work/genram_pkg/.genram_pkg
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
work/xwb_lm32/.xwb_lm32_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_lm32/.xwb_lm32
:
\
work/wishbone_pkg/.wishbone_pkg
work/lm32_dp_ram/.lm32_dp_ram_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_dp_ram/.lm32_dp_ram
:
\
work/genram_pkg/.genram_pkg
work/lm32_ram/.lm32_ram_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/lm32_ram/.lm32_ram
:
\
work/genram_pkg/.genram_pkg
work/wb_slave_adapter/.wb_slave_adapter_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_slave_adapter/.wb_slave_adapter
:
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_clock_crossing/.xwb_clock_crossing_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_clock_crossing/.xwb_clock_crossing
:
\
work/genram_pkg/.genram_pkg
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_dma/.xwb_dma_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_dma/.xwb_dma
:
\
work/genram_pkg/.genram_pkg
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_streamer/.xwb_streamer_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_streamer/.xwb_streamer
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_serial_lcd/.wb_serial_lcd_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_serial_lcd/.wb_serial_lcd
:
\
work/genram_pkg/.genram_pkg
\
work/wishbone_pkg/.wishbone_pkg
work/wb_spi_flash/.wb_spi_flash_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_spi_flash/.wb_spi_flash
:
\
work/genram_pkg/.genram_pkg
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/simple_pwm_wb/.simple_pwm_wb_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/simple_pwm_wb/.simple_pwm_wb
:
\
work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg
work/wb_simple_pwm/.wb_simple_pwm_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_simple_pwm/.wb_simple_pwm
:
\
work/simple_pwm_wbgen2_pkg/.simple_pwm_wbgen2_pkg
\
work/wishbone_pkg/.wishbone_pkg
work/xwb_simple_pwm/.xwb_simple_pwm_vhd
:
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_simple_pwm/.xwb_simple_pwm
:
\
work/wishbone_pkg/.wishbone_pkg
work/wbgen2_dpssram/.wbgen2_dpssram_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_dpssram/.wbgen2_dpssram
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_eic/.wbgen2_eic_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_eic/.wbgen2_eic
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_fifo_async/.wbgen2_fifo_async
:
\
work/wbgen2_pkg/.wbgen2_pkg
\
work/genram_pkg/.genram_pkg
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd
:
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbgen2_fifo_sync/.wbgen2_fifo_sync
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/dma_eic/.dma_eic_vhd
:
../rtl/dma_eic.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/dma_eic/.dma_eic
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/xloader_registers_pkg/.xloader_registers_pkg_vhd
:
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xloader_registers_pkg/.xloader_registers_pkg
:
\
work/wbgen2_pkg/.wbgen2_pkg
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd
:
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader
:
\
work/wishbone_pkg/.wishbone_pkg
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd
:
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader
:
\
work/wishbone_pkg/.wishbone_pkg
\
work/gencores_pkg/.gencores_pkg
\
work/xloader_registers_pkg/.xloader_registers_pkg
work/xloader_wb/.xloader_wb_vhd
:
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/xloader_wb/.xloader_wb
:
\
work/wbgen2_pkg/.wbgen2_pkg
\
work/xloader_registers_pkg/.xloader_registers_pkg
work/ddr3_ctrl/.ddr3_ctrl_vhd
:
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/ddr3_ctrl_wb/.ddr3_ctrl_wb_vhd
:
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/ddr3_ctrl_wb/.ddr3_ctrl_wb
:
\
work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg
work/ddr3_ctrl_wrapper_pkg/.ddr3_ctrl_wrapper_pkg_vhd
:
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/ddr3_ctrl_wrapper/.ddr3_ctrl_wrapper_vhd
:
../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/ddr3_ctrl_wrapper/.ddr3_ctrl_wrapper
:
\
work/ddr3_ctrl_wrapper_pkg/.ddr3_ctrl_wrapper_pkg
work/gn4124_core_pkg/.gn4124_core_pkg_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/ddr3_ctrl_spec_bank3_64b_32b/.ddr3_ctrl_spec_bank3_64b_32b_vhd
:
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/memc3_infrastructure/.memc3_infrastructure_vhd
:
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/memc3_wrapper/.memc3_wrapper_vhd
:
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/iodrp_controller/.iodrp_controller_vhd
:
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/iodrp_mcb_controller/.iodrp_mcb_controller_vhd
:
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/mcb_raw_wrapper/.mcb_raw_wrapper_vhd
:
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/mcb_soft_calibration_top/.mcb_soft_calibration_top_vhd
:
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/mcb_soft_calibration/.mcb_soft_calibration_vhd
:
../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/dma_controller/.dma_controller_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/dma_controller/.dma_controller
:
\
work/gn4124_core_pkg/.gn4124_core_pkg
work/dma_controller_wb_slave/.dma_controller_wb_slave_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/l2p_arbiter/.l2p_arbiter_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/l2p_arbiter/.l2p_arbiter
:
\
work/gn4124_core_pkg/.gn4124_core_pkg
work/l2p_dma_master/.l2p_dma_master_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/l2p_dma_master/.l2p_dma_master
:
\
work/gn4124_core_pkg/.gn4124_core_pkg
\
work/genram_pkg/.genram_pkg
work/p2l_decode32/.p2l_decode32_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/p2l_decode32/.p2l_decode32
:
\
work/gn4124_core_pkg/.gn4124_core_pkg
work/p2l_dma_master/.p2l_dma_master_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/p2l_dma_master/.p2l_dma_master
:
\
work/gn4124_core_pkg/.gn4124_core_pkg
\
work/genram_pkg/.genram_pkg
work/wbmaster32/.wbmaster32_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/wbmaster32/.wbmaster32
:
\
work/gn4124_core_pkg/.gn4124_core_pkg
\
work/genram_pkg/.genram_pkg
work/gn4124_core/.gn4124_core_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/gn4124_core/.gn4124_core
:
\
work/gn4124_core_pkg/.gn4124_core_pkg
work/spec_top_fmc_adc_100Ms/.spec_top_fmc_adc_100Ms_vhd
:
../rtl/spec_top_fmc_adc_100Ms.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/spec_top_fmc_adc_100Ms/.spec_top_fmc_adc_100Ms
:
\
work/gn4124_core_pkg/.gn4124_core_pkg
\
work/wishbone_pkg/.wishbone_pkg
\
work/timetag_core_pkg/.timetag_core_pkg
\
work/fmc_adc_mezzanine_pkg/.fmc_adc_mezzanine_pkg
\
work/sdb_meta_pkg/.sdb_meta_pkg
\
work/ddr3_ctrl_pkg/.ddr3_ctrl_pkg
\
work/gencores_pkg/.gencores_pkg
work/l2p_ser/.l2p_ser_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/l2p_ser/.l2p_ser
:
\
work/gn4124_core_pkg/.gn4124_core_pkg
work/p2l_des/.p2l_des_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/p2l_des/.p2l_des
:
\
work/gn4124_core_pkg/.gn4124_core_pkg
work/serdes_1_to_n_clk_pll_s2_diff/.serdes_1_to_n_clk_pll_s2_diff_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/serdes_1_to_n_data_s2_se/.serdes_1_to_n_data_s2_se_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/serdes_n_to_1_s2_diff/.serdes_n_to_1_s2_diff_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/serdes_n_to_1_s2_se/.serdes_n_to_1_s2_se_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
work/pulse_sync_rtl/.pulse_sync_rtl_vhd
:
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd
vcom
$(VCOM_FLAGS)
-work
work
$<
@
mkdir
-p
$
(
dir
$@
)
&&
touch
$@
hdl/spec/sim/Manifest.py
View file @
4da0fe72
sim_tool
=
"modelsim"
top_module
=
"main"
target
=
"xilinx"
action
=
"simulation"
syn_device
=
"xc6slx45t"
ctrls
=
[
"bank3_64b_32b"
]
files
=
[
"testbench/gn412x_bfm.vhd"
,
"testbench/cmd_router.vhd"
,
...
...
@@ -20,8 +25,8 @@ modules = { "local" : ["../rtl",
"../../ip_cores/timetag_core/rtl"
,
"testbench"
,
"sim_models/2048Mb_ddr3"
],
"git"
:
[
"git://ohwr.org/hdl-core-lib/general-cores.git
::proposed_master
"
,
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git
::spec_bank3_64b_32b
"
,
"git://ohwr.org/hdl-core-lib/gn4124-core.git
::master
"
]}
"git"
:
[
"git://ohwr.org/hdl-core-lib/general-cores.git
@@c26ee857158e4a65fd9d2add8b63fcb6fb4691ea
"
,
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git
@@e4d6755cc9c9c5cb005ce12eb82b12552922b882
"
,
"git://ohwr.org/hdl-core-lib/gn4124-core.git
@@e0dcb3f9a3e6804f64c544743bdf46b5fcbbefab
"
]}
fetchto
=
"../../ip_cores"
hdl/spec/sim/hdlmake.sh
deleted
100755 → 0
View file @
2213467d
~/projects/hdl-make/hdlmake
\ No newline at end of file
hdl/spec/sim/sim_models/2048Mb_ddr3/ddr3_parameters.vh
View file @
4da0fe72
...
...
@@ -559,7 +559,8 @@
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
`else
`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
...
...
hdl/spec/sim/spec.do
View file @
4da0fe72
vsim -novopt -t 1ps tb_spec
log -r /*
##do wave_serdes.do
##do wave_wb_buses.do
##do wave_datapath.do
##do wave_multishot.do
##do wave_onewire.do
##do wave_adc_core.do
##do wave_gnum.do
##do wave_end_acq_irq.do
##do wave_ddr_wb.do
do wave_trig_tag.do
do wave.do
do wave_reset.do
do wave_serdes.do
do wave_wb_buses.do
do wave_datapath.do
do wave_multishot.do
do wave_onewire.do
do wave_adc_core.do
do wave_gnum.do
do wave_end_acq_irq.do
do wave_ddr_wb.do
view wave
view transcript
...
...
hdl/spec/sim/wave.do
View file @
4da0fe72
...
...
@@ -12,11 +12,11 @@ add wave -noupdate /tb_spec/adc_outa_p_i
add wave -noupdate /tb_spec/adc_outb_n_i
add wave -noupdate /tb_spec/adc_outb_p_i
add wave -noupdate -divider serdes
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/bitslip_sreg
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/serdes_bitslip
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/serdes_synced
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/serdes_clk
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/fs_clk
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/bitslip_sreg
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/serdes_bitslip
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/serdes_synced
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/serdes_clk
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/fs_clk
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {510000 ps} 0}
configure wave -namecolwidth 464
...
...
hdl/spec/sim/wave_adc_core.do
View file @
4da0fe72
...
...
@@ -3,169 +3,167 @@ quietly WaveActivateNextPane {} 0
add wave -noupdate /tb_spec/RSTOUT18n
add wave -noupdate -radix hexadecimal -childformat {{/tb_spec/ADC_DATA(0) -radix hexadecimal} {/tb_spec/ADC_DATA(1) -radix hexadecimal} {/tb_spec/ADC_DATA(2) -radix hexadecimal} {/tb_spec/ADC_DATA(3) -radix hexadecimal}} -expand -subitemconfig {/tb_spec/ADC_DATA(0) {-height 17 -radix hexadecimal} /tb_spec/ADC_DATA(1) {-height 17 -radix hexadecimal} /tb_spec/ADC_DATA(2) {-height 17 -radix hexadecimal} /tb_spec/ADC_DATA(3) {-height 17 -radix hexadecimal}} /tb_spec/ADC_DATA
add wave -noupdate -divider {adc core}
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sys_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sys_rst_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_adr_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_cyc_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_sel_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_stb_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_we_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_csr_ack_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_adr_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_sel_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stb_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_ack_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stall_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/ext_trigger_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/ext_trigger_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_dco_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_dco_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_fr_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_fr_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_outa_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_outa_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_outb_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/adc_outb_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_dac_clr_n_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_led_acq_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_led_trig_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_ssr_ch1_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_ssr_ch2_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_ssr_ch3_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_ssr_ch4_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gpio_si570_oe_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sys_rst
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_rst
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_rst_n
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dco_clk
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/clk_fb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/locked_in
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/locked_out
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_clk
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_clk
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_clk_buf
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_in_p
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_in_n
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_raw
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_data
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_data_d
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/data_calibr_in
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/offset_calibr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gain_calibr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/data_calibr_out
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_fr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_man_bitslip
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_bitslip
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_synced
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/bitslip_sreg
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/ext_trig_a
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/ext_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/int_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/int_trig_sel
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/int_trig_thres
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/int_trig_data
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/int_trig_over_thres_d
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/int_trig_over_thres
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/hw_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/hw_trig_t
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/hw_trig_sel
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/hw_trig_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sw_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sw_trig_t
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sw_trig_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_delay
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_delay_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_d
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_align
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_factor
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_din
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_empty
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dreq
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/gain_calibr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/offset_calibr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_fsm_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fsm_cmd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fsm_cmd_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_start
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_stop
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_end
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_in_pre_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_in_post_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/samples_wr_en
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/pre_trig_value
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/pre_trig_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/pre_trig_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/post_trig_value
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/post_trig_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/post_trig_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/samples_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_value
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_done
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_decr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/single_shot
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sys_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sys_rst_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_csr_adr_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_csr_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_csr_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_csr_cyc_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_csr_sel_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_csr_stb_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_csr_we_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_csr_ack_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_adr_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_sel_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_stb_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_ack_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_stall_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trigger_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trigger_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/adc_dco_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/adc_dco_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/adc_fr_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/adc_fr_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/adc_outa_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/adc_outa_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/adc_outb_p_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/adc_outb_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/gpio_dac_clr_n_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/gpio_led_acq_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/gpio_led_trig_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/gpio_ssr_ch1_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/gpio_ssr_ch2_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/gpio_ssr_ch3_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/gpio_ssr_ch4_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/gpio_si570_oe_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sys_rst
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_rst
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_rst_n
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dco_clk
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/clk_fb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/locked_in
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/locked_out
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_clk
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk_buf
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_in_p
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_in_n
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_out_raw
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_out_data
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_in
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/offset_calibr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/gain_calibr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_out_fr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_man_bitslip
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_bitslip
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_synced
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/bitslip_sreg
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_a
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_sel
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_thres
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_data
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_over_thres_d
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_over_thres
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/hw_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/hw_trig_t
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/hw_trig_sel
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/hw_trig_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig_t
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_delay
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_delay_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_d
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_align
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/decim_factor
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/decim_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/decim_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_din
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_empty
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/gain_calibr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/offset_calibr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fsm_cmd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fsm_cmd_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_start
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_stop
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_end
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_in_pre_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_in_post_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/samples_wr_en
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/pre_trig_value
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/pre_trig_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/pre_trig_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/post_trig_value
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/post_trig_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/post_trig_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/samples_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/shots_value
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/shots_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/shots_done
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/shots_decr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/single_shot
add wave -noupdate -divider {dpram wr}
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/multishot_buffer_sel
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_addra_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_addra_trig
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_addra_post_done
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/multishot_buffer_sel
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram_addra_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram_addra_trig
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram_addra_post_done
add wave -noupdate -divider {dpram 0}
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_dina
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_addra
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_wea
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_addrb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_doutb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram0_dina
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram0_addra
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram0_wea
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram0_addrb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram0_doutb
add wave -noupdate -divider {dpram 1}
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_dina
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_addra
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_wea
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_addrb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_doutb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram1_dina
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram1_addra
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram1_wea
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram1_addrb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram1_doutb
add wave -noupdate -divider {dpram rd}
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_valid_t
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram_valid_t
add wave -noupdate -divider {ddr fifo}
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_addr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_din
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_empty
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dreq
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/ram_addr_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/test_data_en
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/trig_addr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_wr_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_din
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_empty
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_dreq
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/ram_addr_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/test_data_en
add wave -noupdate -divider {ddr wb}
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stall_t
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_we_o
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stb_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_dat_o
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_adr_o
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_ack_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_led
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_led_man
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_led_man
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_stall_t
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_we_o
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_stb_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_dat_o
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_adr_o
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_ack_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/trig_led
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/trig_led_man
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/acq_led_man
add wave -noupdate /tb_spec/RSTOUT18n
add wave -noupdate -radix hexadecimal -childformat {{/tb_spec/ADC_DATA(0) -radix hexadecimal} {/tb_spec/ADC_DATA(1) -radix hexadecimal} {/tb_spec/ADC_DATA(2) -radix hexadecimal} {/tb_spec/ADC_DATA(3) -radix hexadecimal}} -expand -subitemconfig {/tb_spec/ADC_DATA(0) {-radix hexadecimal} /tb_spec/ADC_DATA(1) {-radix hexadecimal} /tb_spec/ADC_DATA(2) {-radix hexadecimal} /tb_spec/ADC_DATA(3) {-radix hexadecimal}} /tb_spec/ADC_DATA
TreeUpdate [SetDefaultTree]
...
...
hdl/spec/sim/wave_datapath.do
View file @
4da0fe72
...
...
@@ -3,63 +3,62 @@ quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {Wishbone CSR interface}
add wave -noupdate /tb_spec/U1/sys_clk_125
add wave -noupdate -divider trigger
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/sw_trig_en
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/sw_trig
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/trig
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/trig_d
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/trig_align
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/sw_trig_en
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/sw_trig
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/trig
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/trig_d
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/trig_align
add wave -noupdate -divider {acq fsm}
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/post_trig_done
add wave -noupdate -radix hexadecimal /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/shots_cnt
add wave -noupdate -radix hexadecimal /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/shots_value
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/shots_decr
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/shots_done
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/post_trig_done
add wave -noupdate -radix hexadecimal /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/shots_cnt
add wave -noupdate -radix hexadecimal /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/shots_value
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/shots_decr
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/shots_done
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
add wave -noupdate -divider datapath
add wave -noupdate -radix hexadecimal /tb_spec/ADC_DATA
add wave -noupdate /tb_spec/U1/adc_dco_n_i
add wave -noupdate /tb_spec/U1/adc_dco_p_i
add wave -noupdate /tb_spec/U1/adc_fr_p_i
add wave -noupdate /tb_spec/U1/adc_outa_p_i(0)
add wave -noupdate /tb_spec/U1/adc_outb_p_i(0)
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_fr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_data
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/locked_out
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_clk
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/fs_rst_n
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_synced
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_cnt
add wave -noupdate -radix decimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_factor
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_din
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_full
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dreq
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_dout(48)
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_empty
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_rd
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/serdes_out_data
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_din
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_full
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dreq
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dout
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_empty
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/ram_addr_cnt
add wave -noupdate /tb_spec/U1/adc0_dco_n_i
add wave -noupdate /tb_spec/U1/adc0_dco_p_i
add wave -noupdate /tb_spec/U1/adc0_fr_p_i
add wave -noupdate /tb_spec/U1/adc0_outa_p_i(0)
add wave -noupdate /tb_spec/U1/adc0_outb_p_i(0)
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_out_fr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_out_data
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/locked_out
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_clk
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/fs_rst_n
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_synced
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/decim_cnt
add wave -noupdate -radix decimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/decim_factor
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/decim_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_din
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_dout(48)
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_empty
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_rd
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_out_data
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr_en
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_din
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_full
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dreq
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dout
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_empty
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ram_addr_cnt
add wave -noupdate -divider {adc to ddr WB}
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/wb_ddr_ack_i
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/wb_ddr_clk_i
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/wb_ddr_dat_o
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/wb_ddr_stb_o
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/wb_ddr_adr_o
add wave -noupdate /tb_spec/
U1
/cmp_fmc_adc_100Ms_core/wb_ddr_stall_i
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/wb_ddr_ack_i
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/wb_ddr_clk_i
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/wb_ddr_dat_o
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/wb_ddr_stb_o
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/wb_ddr_adr_o
add wave -noupdate /tb_spec/
u1/cmp_fmc_adc_mezzanine_0
/cmp_fmc_adc_100Ms_core/wb_ddr_stall_i
add wave -noupdate -divider {ddr controller}
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/status_o(0)
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/wb0_clk_i
...
...
hdl/spec/sim/wave_end_acq_irq.do
View file @
4da0fe72
...
...
@@ -3,93 +3,89 @@ quietly WaveActivateNextPane {} 0
add wave -noupdate /tb_spec/RSTOUT18n
add wave -noupdate -radix hexadecimal -childformat {{/tb_spec/ADC_DATA(0) -radix hexadecimal} {/tb_spec/ADC_DATA(1) -radix hexadecimal} {/tb_spec/ADC_DATA(2) -radix hexadecimal} {/tb_spec/ADC_DATA(3) -radix hexadecimal}} -expand -subitemconfig {/tb_spec/ADC_DATA(0) {-height 17 -radix hexadecimal} /tb_spec/ADC_DATA(1) {-height 17 -radix hexadecimal} /tb_spec/ADC_DATA(2) {-height 17 -radix hexadecimal} /tb_spec/ADC_DATA(3) {-height 17 -radix hexadecimal}} /tb_spec/ADC_DATA
add wave -noupdate -divider {adc core}
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sys_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sys_rst_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_adr_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_sel_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stb_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_ack_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stall_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_d
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_align
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_factor
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_fsm_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fsm_cmd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fsm_cmd_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_start
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_stop
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_in_pre_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_in_post_trig
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_end
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_end_p_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/samples_wr_en
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_value
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_done
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_decr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/single_shot
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/sync_fifo_valid
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/pre_trig_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/pre_trig_cnt
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/post_trig_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/post_trig_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_addr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_din
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_empty
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dreq
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr_en
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/ram_addr_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/sys_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/sys_rst_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_adr_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_sel_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_stb_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_ack_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_stall_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/trig_d
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/trig_align
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/decim_factor
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/decim_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/decim_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/acq_fsm_current_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/acq_fsm_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/fsm_cmd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/fsm_cmd_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/acq_start
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/acq_stop
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/acq_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/acq_in_pre_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/acq_in_post_trig
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/acq_end
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/acq_end_p_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/samples_wr_en
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/shots_value
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/shots_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/shots_done
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/shots_decr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/single_shot
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/sync_fifo_valid
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/pre_trig_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/pre_trig_cnt
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/post_trig_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/post_trig_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/trig_addr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_din
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_empty
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_dreq
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_fifo_wr_en
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/ram_addr_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_count_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_wr_full_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_rd_full_i
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/cmp_ddr3_ctrl_wb_0/ddr_cmd_full_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stall_t
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/wb_ddr_stall_t
add wave -noupdate -divider Multi-shot
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/samples_wr_en
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/multishot_buffer_sel
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_addra_cnt
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_wea
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_addra
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_dina
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_wea
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_addra
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_dina
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_addra_trig
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_addra_post_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_addrb_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_addrb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram0_doutb
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_addrb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram1_doutb
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_valid_t
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/dpram_dout
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/samples_wr_en
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/multishot_buffer_sel
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram_addra_cnt
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram0_wea
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram0_addra
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram0_dina
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram1_wea
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram1_addra
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram1_dina
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram_addra_trig
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram_addra_post_done
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram_addrb_cnt
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram0_addrb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram0_doutb
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram1_addrb
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram1_doutb
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram_valid_t
add wave -noupdate /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_
100Ms_core/dpram_dout
add wave -noupdate -divider {ddr core}
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_full
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_en
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_empty
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_count
add wave -noupdate -divider irq
add wave -noupdate /tb_spec/U1/trigger_p
add wave -noupdate /tb_spec/U1/acq_end_p
add wave -noupdate /tb_spec/U1/adc0_ext_trigger_p_i
add wave -noupdate /tb_spec/U1/acq_end_irq_p
add wave -noupdate /tb_spec/U1/acq_end
add wave -noupdate /tb_spec/U1/ddr_wr_fifo_empty_p
add wave -noupdate /tb_spec/U1/ddr_wr_fifo_empty_d
add wave -noupdate /tb_spec/U1/ddr_wr_fifo_empty
add wave -noupdate /tb_spec/U1/irq_sources(3)
add wave -noupdate /tb_spec/U1/irq_to_gn4124
...
...
hdl/spec/sim/wave_multishot.do
View file @
4da0fe72
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider {ACQ FSM}
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/acq_fsm_current_state
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/acq_start
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/acq_trig
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/acq_in_pre_trig
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/acq_in_post_trig
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/acq_end
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/acq_stop
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/samples_wr_en
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/acq_fsm_current_state
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/acq_start
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/acq_trig
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/acq_in_pre_trig
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/acq_in_post_trig
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/acq_end
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/acq_stop
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/samples_wr_en
add wave -noupdate -divider {SYNC FIFO}
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/sync_fifo_dout
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/sync_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/sync_fifo_dout
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/sync_fifo_valid
add wave -noupdate -divider {PRE-TRIG COUNTER}
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/pre_trig_cnt
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/pre_trig_done
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
100m
s_core/pre_trig_value
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/pre_trig_cnt
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/pre_trig_done
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/pre_trig_value
add wave -noupdate -divider {POST-TRIG COUNTER}
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/post_trig_cnt
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/post_trig_done
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
100m
s_core/post_trig_value
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/post_trig_cnt
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/post_trig_done
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/post_trig_value
add wave -noupdate -divider {SHOT COUNTER}
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/shots_value
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/single_shot
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/shots_decr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/shots_cnt
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/multishot_buffer_sel
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/shots_done
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/shots_value
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/single_shot
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/shots_decr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/shots_cnt
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/multishot_buffer_sel
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/shots_done
add wave -noupdate -divider MULTISHOT
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram_addra_cnt
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram0_addra
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram0_wea
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram0_dina
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram1_addra
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram1_wea
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram1_dina
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram_addra_post_done
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram_addra_trig
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram0_addrb
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram0_doutb
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram1_addrb
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram1_doutb
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram_addrb_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram_dout
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram_valid
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/dpram_valid_t
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram_addra_cnt
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram0_addra
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram0_wea
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram0_dina
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram1_addra
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram1_wea
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram1_dina
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram_addra_post_done
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram_addra_trig
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram0_addrb
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram0_doutb
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram1_addrb
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram1_doutb
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram_addrb_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram_dout
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram_valid
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/dpram_valid_t
add wave -noupdate -divider {WB FIFO}
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_fifo_wr_en
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_fifo_din
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_fifo_full
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_stall_t
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_fifo_dout
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_fifo_valid
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_fifo_empty
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_fifo_wr_en
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_fifo_din
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_fifo_full
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_stall_t
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_fifo_dout
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_fifo_valid
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_fifo_empty
add wave -noupdate -divider {WB BUS}
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_clk_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_cyc_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_stb_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_adr_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_dat_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_ack_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/wb_ddr_stall_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_clk_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_cyc_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_stb_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_adr_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_dat_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_ack_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/wb_ddr_stall_i
add wave -noupdate -divider {DDR CTRL}
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p0_cmd_bl
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_ddr_ctrl/p0_cmd_byte_addr
...
...
hdl/spec/sim/wave_onewire.do
View file @
4da0fe72
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_ack
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_adr
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_cyc
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_sel
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_stall
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_stb
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_we
add wave -noupdate -radix hexadecimal /tb_spec/u1/cnx_master_out
add wave -noupdate -radix hexadecimal /tb_spec/u1/cnx_master_in
add wave -noupdate -divider {Wishbone CSR interface}
add wave -noupdate /tb_spec/u1/sys_clk_125
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_adr
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_dat_o
add wave -noupdate /tb_spec/u1/wb_dat_i
add wave -noupdate /tb_spec/u1/wb_stb
add wave -noupdate /tb_spec/u1/wb_we
add wave -noupdate /tb_spec/u1/wb_sel
add wave -noupdate /tb_spec/u1/wb_cyc(10)
add wave -noupdate /tb_spec/u1/wb_stall(10)
add wave -noupdate /tb_spec/u1/wb_ack(10)
add wave -noupdate -radix hexadecimal /tb_spec/u1/cnx_slave_out
add wave -noupdate -radix hexadecimal /tb_spec/u1/cnx_slave_in
add wave -noupdate -divider onewire
add wave -noupdate -radix unsigned -subitemconfig {{/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[7]} {-radix unsigned} {/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[6]} {-radix unsigned} {/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[5]} {-radix unsigned} {/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[4]} {-radix unsigned} {/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[3]} {-radix unsigned} {/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[2]} {-radix unsigned} {/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[1]} {-radix unsigned} {/tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst[0]} {-radix unsigned}} /tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/t_rst
add wave -noupdate -radix unsigned /tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/cnt
add wave -noupdate /tb_spec/u1/one_wire_b
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/owr_pwren_o(0)
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/owr_en_o(0)
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/owr_i(0)
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/clk_sys_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/rst_n_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_cyc_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_sel_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_stb_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_we_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_adr_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_ack_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/wb_int_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/bus_wen
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/bus_ren
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_onewire/rst
add wave -noupdate /tb_spec/u1/cmp_fmc_onewire/wrapped_1wire/pls
add wave -noupdate /tb_spec/u1/adc0_one_wire_b
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_onewire/owr_pwren_o(0)
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_onewire/owr_en_o(0)
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_onewire/owr_i(0)
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_onewire/clk_sys_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_onewire/rst_n_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_onewire/slave_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_onewire/slave_o
add wave -noupdate -divider l2p
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/wb_ack_cnt
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_gn4124_core/cmp_l2p_dma_master/wb_read_cnt
...
...
hdl/spec/sim/wave_reset.do
View file @
4da0fe72
...
...
@@ -4,7 +4,6 @@ add wave -noupdate /tb_spec/u1/sys_clk_in
add wave -noupdate /tb_spec/u1/sys_clk_125
add wave -noupdate /tb_spec/u1/sys_clk_250
add wave -noupdate /tb_spec/u1/sys_clk_pll_locked
add wave -noupdate /tb_spec/u1/sys_rst
add wave -noupdate /tb_spec/u1/sys_rst_n
add wave -noupdate /tb_spec/u1/l_rst_n
TreeUpdate [SetDefaultTree]
...
...
hdl/spec/sim/wave_serdes.do
View file @
4da0fe72
...
...
@@ -12,15 +12,15 @@ add wave -noupdate /tb_spec/adc_outb_p_i(2)
add wave -noupdate /tb_spec/adc_outa_p_i
add wave -noupdate /tb_spec/adc_outb_p_i
add wave -noupdate -divider serdes
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/serdes_in_p
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/serdes_clk
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/fs_clk
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/serdes_out_raw
add wave -noupdate -radix binary /tb_spec/u1/cmp_fmc_adc_
100m
s_core/serdes_out_fr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
100m
s_core/serdes_out_data
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/bitslip_sreg
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/serdes_bitslip
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
100m
s_core/serdes_synced
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/serdes_in_p
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/serdes_clk
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/fs_clk
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/serdes_out_raw
add wave -noupdate -radix binary /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/serdes_out_fr
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/serdes_out_data
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/bitslip_sreg
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/serdes_bitslip
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_
mezzanine_0/cmp_fmc_adc_100M
s_core/serdes_synced
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {760625 ps} 0}
configure wave -namecolwidth 366
...
...
hdl/spec/sim/wave_wb_buses.do
View file @
4da0fe72
...
...
@@ -49,53 +49,12 @@ add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_ddr_we
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_ddr_ack
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_ddr_stall
add wave -noupdate -divider {Wishbone CSR master}
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_ack
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_adr
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_cyc
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_sel
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_stall
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_stb
add wave -noupdate -radix hexadecimal /tb_spec/u1/wbm_we
add wave -noupdate /tb_spec/u1/cnx_master_out
add wave -noupdate /tb_spec/u1/cnx_master_in
add wave -noupdate -divider {Wishbone CSR slaves}
add wave -noupdate -radix hexadecimal /tb_spec/u1/sys_clk_125
add wave -noupdate /tb_spec/u1/wb_cyc(9)
add wave -noupdate /tb_spec/u1/wb_cyc(8)
add wave -noupdate /tb_spec/u1/wb_cyc(7)
add wave -noupdate /tb_spec/u1/wb_cyc(6)
add wave -noupdate /tb_spec/u1/wb_cyc(5)
add wave -noupdate /tb_spec/u1/wb_cyc(4)
add wave -noupdate /tb_spec/u1/wb_cyc(3)
add wave -noupdate /tb_spec/u1/wb_cyc(2)
add wave -noupdate /tb_spec/u1/wb_cyc(1)
add wave -noupdate /tb_spec/u1/wb_cyc(0)
add wave -noupdate /tb_spec/u1/wb_ack(9)
add wave -noupdate /tb_spec/u1/wb_ack(8)
add wave -noupdate /tb_spec/u1/wb_ack(7)
add wave -noupdate /tb_spec/u1/wb_ack(6)
add wave -noupdate /tb_spec/u1/wb_ack(5)
add wave -noupdate /tb_spec/u1/wb_ack(4)
add wave -noupdate /tb_spec/u1/wb_ack(3)
add wave -noupdate /tb_spec/u1/wb_ack(2)
add wave -noupdate /tb_spec/u1/wb_ack(1)
add wave -noupdate /tb_spec/u1/wb_ack(0)
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_adr
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_dat_i
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_stb
add wave -noupdate -radix hexadecimal /tb_spec/u1/wb_we
add wave -noupdate -radix hexadecimal -subitemconfig {/tb_spec/u1/wb_sel(3) {-radix hexadecimal} /tb_spec/u1/wb_sel(2) {-radix hexadecimal} /tb_spec/u1/wb_sel(1) {-radix hexadecimal} /tb_spec/u1/wb_sel(0) {-radix hexadecimal}} /tb_spec/u1/wb_sel
add wave -noupdate /tb_spec/u1/wb_stall(9)
add wave -noupdate /tb_spec/u1/wb_stall(8)
add wave -noupdate /tb_spec/u1/wb_stall(7)
add wave -noupdate /tb_spec/u1/wb_stall(6)
add wave -noupdate /tb_spec/u1/wb_stall(5)
add wave -noupdate /tb_spec/u1/wb_stall(4)
add wave -noupdate /tb_spec/u1/wb_stall(3)
add wave -noupdate /tb_spec/u1/wb_stall(2)
add wave -noupdate /tb_spec/u1/wb_stall(1)
add wave -noupdate /tb_spec/u1/wb_stall(0)
add wave -noupdate /tb_spec/u1/cnx_slave_out
add wave -noupdate /tb_spec/u1/cnx_slave_in
add wave -noupdate -divider IOs
add wave -noupdate /tb_spec/led_red
add wave -noupdate /tb_spec/led_green
...
...
@@ -109,8 +68,12 @@ add wave -noupdate /tb_spec/spi_cs_dac2_n_o
add wave -noupdate /tb_spec/spi_cs_dac3_n_o
add wave -noupdate /tb_spec/spi_cs_dac4_n_o
add wave -noupdate -divider {FMC I2C}
add wave -noupdate -radix hexadecimal /tb_spec/u1/cmp_fmc_i2c/wb_dat_i
add wave -noupdate /tb_spec/u1/cmp_fmc_i2c/wb_adr_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/scl_pad_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/scl_pad_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/scl_padoen_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/sda_pad_i
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/sda_pad_o
add wave -noupdate /tb_spec/u1/cmp_fmc_adc_mezzanine_0/cmp_fmc_sys_i2c/sda_padoen_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {13971949 ps} 0}
configure wave -namecolwidth 464
...
...
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