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FMC ADC 100M 14b 4cha
Commit 09563ffb authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Add spexi top hdl design (Note that it's not compliant to the latest… 

hdl: Add spexi top hdl design (Note that it's not compliant to the latest architecture and gnum core, yet).
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hdl/spexi/rtl/Manifest.py 0 → 100644
View file @ 09563ffb
files = [
"spexi_top_fmc_adc_100Ms.vhd",
"carrier_csr.vhd",
"utc_core_regs.vhd",
"utc_core.vhd",
"irq_controller_regs.vhd",
"irq_controller.vhd"];
hdl/spexi/rtl/carrier_csr.vhd 0 → 100644
View file @ 09563ffb
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Wed Nov 23 09:30:44 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity carrier_csr is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_reserved_i : in std_logic_vector(11 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'Bitstream type' in reg: 'Bitstream type'
carrier_csr_bitstream_type_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Bitstream date' in reg: 'Bitstream date'
carrier_csr_bitstream_date_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'FMC presence' in reg: 'Status'
carrier_csr_stat_fmc_pres_i : in std_logic;
-- Port for BIT field: 'GN4142 core P2L PLL status' in reg: 'Status'
carrier_csr_stat_p2l_pll_lck_i : in std_logic;
-- Port for BIT field: 'System clock PLL status' in reg: 'Status'
carrier_csr_stat_sys_pll_lck_i : in std_logic;
-- Port for BIT field: 'DDR3 calibration status' in reg: 'Status'
carrier_csr_stat_ddr3_cal_done_i : in std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status'
carrier_csr_stat_reserved_i : in std_logic_vector(27 downto 0);
-- Port for BIT field: 'Green LED' in reg: 'Control'
carrier_csr_ctrl_led_green_o : out std_logic;
-- Port for BIT field: 'Red LED' in reg: 'Control'
carrier_csr_ctrl_led_red_o : out std_logic;
-- Port for BIT field: 'DAC clear' in reg: 'Control'
carrier_csr_ctrl_dac_clr_n_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0)
);
end carrier_csr;
architecture syn of carrier_csr is
signal carrier_csr_ctrl_led_green_int : std_logic ;
signal carrier_csr_ctrl_led_red_int : std_logic ;
signal carrier_csr_ctrl_dac_clr_n_int : std_logic ;
signal carrier_csr_ctrl_reserved_int : std_logic_vector(28 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_csr_ctrl_led_green_int <= '0';
carrier_csr_ctrl_led_red_int <= '0';
carrier_csr_ctrl_dac_clr_n_int <= '0';
carrier_csr_ctrl_reserved_int <= "00000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
else
rddata_reg(3 downto 0) <= carrier_csr_carrier_pcb_rev_i;
rddata_reg(15 downto 4) <= carrier_csr_carrier_reserved_i;
rddata_reg(31 downto 16) <= carrier_csr_carrier_type_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= carrier_csr_bitstream_type_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= carrier_csr_bitstream_date_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (wb_we_i = '1') then
else
rddata_reg(0) <= carrier_csr_stat_fmc_pres_i;
rddata_reg(1) <= carrier_csr_stat_p2l_pll_lck_i;
rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_csr_stat_ddr3_cal_done_i;
rddata_reg(31 downto 4) <= carrier_csr_stat_reserved_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
carrier_csr_ctrl_led_green_int <= wrdata_reg(0);
carrier_csr_ctrl_led_red_int <= wrdata_reg(1);
carrier_csr_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_csr_ctrl_reserved_int <= wrdata_reg(31 downto 3);
else
rddata_reg(0) <= carrier_csr_ctrl_led_green_int;
rddata_reg(1) <= carrier_csr_ctrl_led_red_int;
rddata_reg(2) <= carrier_csr_ctrl_dac_clr_n_int;
rddata_reg(31 downto 3) <= carrier_csr_ctrl_reserved_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- PCB revision
-- Reserved register
-- Carrier type
-- Bitstream type
-- Bitstream date
-- FMC presence
-- GN4142 core P2L PLL status
-- System clock PLL status
-- DDR3 calibration status
-- Reserved
-- Green LED
carrier_csr_ctrl_led_green_o <= carrier_csr_ctrl_led_green_int;
-- Red LED
carrier_csr_ctrl_led_red_o <= carrier_csr_ctrl_led_red_int;
-- DAC clear
carrier_csr_ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
-- Reserved
carrier_csr_ctrl_reserved_o <= carrier_csr_ctrl_reserved_int;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/spexi/rtl/irq_controller.vhd 0 → 100644
View file @ 09563ffb
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- IRQ controller
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: irq_controller (irq_controller.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 18-11-2011
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity irq_controller is
port (
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Interrupt sources input, must be 1 clk_i tick long
irq_src_p_i : in std_logic_vector(31 downto 0);
-- IRQ pulse output
irq_p_o : out std_logic;
-- Wishbone interface
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end irq_controller;
architecture rtl of irq_controller is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component irq_controller_regs
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
irq_ctrl_multi_irq_o : out std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_i : in std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_load_o : out std_logic;
irq_ctrl_src_o : out std_logic_vector(31 downto 0);
irq_ctrl_src_i : in std_logic_vector(31 downto 0);
irq_ctrl_src_load_o : out std_logic;
irq_ctrl_en_mask_o : out std_logic_vector(31 downto 0)
);
end component irq_controller_regs;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal irq_en_mask : std_logic_vector(31 downto 0);
signal irq_pending : std_logic_vector(31 downto 0);
signal irq_pending_d : std_logic_vector(31 downto 0);
signal irq_pending_re : std_logic_vector(31 downto 0);
signal irq_src_rst : std_logic_vector(31 downto 0);
signal irq_src_rst_en : std_logic;
signal multi_irq : std_logic_vector(31 downto 0);
signal multi_irq_rst : std_logic_vector(31 downto 0);
signal multi_irq_rst_en : std_logic;
signal irq_p_or : std_logic_vector(32 downto 0);
begin
------------------------------------------------------------------------------
-- Wishbone interface to IRQ controller registers
------------------------------------------------------------------------------
cmp_irq_controller_regs : irq_controller_regs
port map(
rst_n_i => rst_n_i,
wb_clk_i => clk_i,
wb_addr_i => wb_adr_i,
wb_data_i => wb_dat_i,
wb_data_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
irq_ctrl_multi_irq_o => multi_irq_rst,
irq_ctrl_multi_irq_load_o => multi_irq_rst_en,
irq_ctrl_multi_irq_i => multi_irq,
irq_ctrl_src_o => irq_src_rst,
irq_ctrl_src_i => irq_pending,
irq_ctrl_src_load_o => irq_src_rst_en,
irq_ctrl_en_mask_o => irq_en_mask
);
------------------------------------------------------------------------------
-- Register interrupt sources
-- IRQ is pending until a '1' is written to the corresponding bit
------------------------------------------------------------------------------
p_irq_src : process (clk_i)
begin
if rising_edge(clk_i) then
for I in 0 to irq_pending'length-1 loop
if rst_n_i = '0' then
irq_pending(I) <= '0';
elsif irq_src_p_i(I) = '1' then
irq_pending(I) <= '1';
elsif irq_src_rst_en = '1' and irq_src_rst(I) = '1' then
irq_pending(I) <= '0';
end if;
end loop; -- I
end if;
end process p_irq_src;
------------------------------------------------------------------------------
-- Multiple interrupt detection
-- Rise a flag if an interrupt occurs while an irq is still pending
-- Write '1' to the flag to clear it
------------------------------------------------------------------------------
p_multi_irq_detect : process (clk_i)
begin
if rising_edge(clk_i) then
for I in 0 to multi_irq'length-1 loop
if rst_n_i = '0' then
multi_irq(I) <= '0';
elsif irq_src_p_i(I) = '1' and irq_pending(I) = '1' then
multi_irq(I) <= '1';
elsif multi_irq_rst_en = '1' and multi_irq_rst(I) = '1' then
multi_irq(I) <= '0';
end if;
end loop; -- I
end if;
end process p_multi_irq_detect;
------------------------------------------------------------------------------
-- Generate IRQ output pulse
------------------------------------------------------------------------------
irq_p_or(0) <= '0';
l_irq_out_pulse : for I in 0 to irq_src_p_i'length-1 generate
irq_p_or(I+1) <= irq_p_or(I) or (irq_src_p_i(I) and irq_en_mask(I));
end generate l_irq_out_pulse;
p_irq_out_pulse : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
irq_p_o <= '0';
else
irq_p_o <= irq_p_or(32);
end if;
end if;
end process p_irq_out_pulse;
end rtl;
hdl/spexi/rtl/irq_controller_regs.vhd 0 → 100644
View file @ 09563ffb
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for IRQ controller registers
---------------------------------------------------------------------------------------
-- File : ../rtl/irq_controller_regs.vhd
-- Author : auto-generated by wbgen2 from irq_controller_regs.wb
-- Created : Wed Jan 18 09:43:55 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity irq_controller_regs is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Port for std_logic_vector field: 'Multiple interrupt' in reg: 'Multiple interrupt register'
irq_ctrl_multi_irq_o : out std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_i : in std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_load_o : out std_logic;
-- Port for std_logic_vector field: 'Interrupt sources' in reg: 'Interrupt sources register '
irq_ctrl_src_o : out std_logic_vector(31 downto 0);
irq_ctrl_src_i : in std_logic_vector(31 downto 0);
irq_ctrl_src_load_o : out std_logic;
-- Port for std_logic_vector field: 'Interrupt enable mask' in reg: 'Interrupt enable mask register'
irq_ctrl_en_mask_o : out std_logic_vector(31 downto 0)
);
end irq_controller_regs;
architecture syn of irq_controller_regs is
signal irq_ctrl_en_mask_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
irq_ctrl_multi_irq_load_o <= '0';
irq_ctrl_src_load_o <= '0';
irq_ctrl_en_mask_int <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
irq_ctrl_multi_irq_load_o <= '0';
irq_ctrl_src_load_o <= '0';
ack_in_progress <= '0';
else
irq_ctrl_multi_irq_load_o <= '0';
irq_ctrl_src_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
irq_ctrl_multi_irq_load_o <= '1';
else
rddata_reg(31 downto 0) <= irq_ctrl_multi_irq_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
irq_ctrl_src_load_o <= '1';
else
rddata_reg(31 downto 0) <= irq_ctrl_src_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
irq_ctrl_en_mask_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= irq_ctrl_en_mask_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- Multiple interrupt
irq_ctrl_multi_irq_o <= wrdata_reg(31 downto 0);
-- Interrupt sources
irq_ctrl_src_o <= wrdata_reg(31 downto 0);
-- Interrupt enable mask
irq_ctrl_en_mask_o <= irq_ctrl_en_mask_int;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/spexi/rtl/spexi_top_fmc_adc_100Ms.vhd 0 → 100644
View file @ 09563ffb
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity for Simple PXIe FMC Carrier
-- http://www.ohwr.org/projects/spexi
--------------------------------------------------------------------------------
--
-- unit name: spexi_top_fmc_adc_100Ms (spexi_top_fmc_adc_100Ms.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 04-10-2012
--
-- version: 1.0
--
-- description: Top entity of FMC ADC 100Ms/s design for SPEXI board.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.gn4124_core_pkg.all;
use work.ddr3_ctrl_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity spexi_top_fmc_adc_100Ms is
generic(
g_SIMULATION : string := "FALSE";
g_CALIB_SOFT_IP : string := "TRUE");
port
(
-- Local oscillator
clk20_vcxo_i : in std_logic; -- 20MHz VCXO clock
-- Carrier font panel LEDs
led_red_o : out std_logic;
led_green_o : out std_logic;
-- Auxiliary pins
aux_leds_o : out std_logic_vector(3 downto 0);
aux_buttons_i : in std_logic_vector(1 downto 0);
-- PCB version
pcb_ver_i : in std_logic_vector(3 downto 0);
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
carrier_one_wire_b : inout std_logic;
-- GN4124 interface
lclk_p_i : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
lclk_n_i : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
gn4124_fpga_rst_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_edb_o : out std_logic; -- Packet termination and discard
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
gpio_irq : inout std_logic_vector(1 downto 0); -- gpio_irq[0] -> GN4124 GPIO8
-- gpio_irq[1] -> GN4124 GPIO9
-- DDR3 interface
ddr3_cas_n_o : out std_logic;
ddr3_ck_n_o : out std_logic;
ddr3_ck_p_o : out std_logic;
ddr3_cke_o : out std_logic;
ddr3_ldm_o : out std_logic;
ddr3_ldqs_n_b : inout std_logic;
ddr3_ldqs_p_b : inout std_logic;
ddr3_odt_o : out std_logic;
ddr3_ras_n_o : out std_logic;
ddr3_reset_n_o : out std_logic;
ddr3_udm_o : out std_logic;
ddr3_udqs_n_b : inout std_logic;
ddr3_udqs_p_b : inout std_logic;
ddr3_we_n_o : out std_logic;
ddr3_dq_b : inout std_logic_vector(15 downto 0);
ddr3_a_o : out std_logic_vector(13 downto 0);
ddr3_ba_o : out std_logic_vector(2 downto 0);
ddr3_zio_b : inout std_logic;
ddr3_rzq_b : inout std_logic;
-- FMC slot
ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic;
adc_dco_p_i : in std_logic; -- ADC data clock
adc_dco_n_i : in std_logic;
adc_fr_p_i : in std_logic; -- ADC frame start
adc_fr_n_i : in std_logic;
adc_outa_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (odd bits)
adc_outa_n_i : in std_logic_vector(3 downto 0);
adc_outb_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (even bits)
adc_outb_n_i : in std_logic_vector(3 downto 0);
spi_din_i : in std_logic; -- SPI data from FMC
spi_dout_o : out std_logic; -- SPI data to FMC
spi_sck_o : out std_logic; -- SPI clock
spi_cs_adc_n_o : out std_logic; -- SPI ADC chip select (active low)
spi_cs_dac1_n_o : out std_logic; -- SPI channel 1 offset DAC chip select (active low)
spi_cs_dac2_n_o : out std_logic; -- SPI channel 2 offset DAC chip select (active low)
spi_cs_dac3_n_o : out std_logic; -- SPI channel 3 offset DAC chip select (active low)
spi_cs_dac4_n_o : out std_logic; -- SPI channel 4 offset DAC chip select (active low)
gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low)
gpio_led_power_o : out std_logic; -- Mezzanine front panel power LED (PWR)
gpio_led_trigger_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control
gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control
gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control
gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
gpio_si570_oe_o : out std_logic; -- Si570 (programmable oscillator) output enable
si570_scl_b : inout std_logic; -- I2C bus clock (Si570)
si570_sda_b : inout std_logic; -- I2C bus data (Si570)
mezz_one_wire_b : inout std_logic; -- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
prsnt_m2c_n_i : in std_logic; -- Mezzanine present (active low)
sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
sys_sda_b : inout std_logic -- Mezzanine system I2C data (EEPROM)
);
end spexi_top_fmc_adc_100Ms;
architecture rtl of spexi_top_fmc_adc_100Ms is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component wb_addr_decoder
generic
(
g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address)
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i : in std_logic_vector(31 downto 0); -- Address
wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out
wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wbm_stb_i : in std_logic; -- Strobe
wbm_we_i : in std_logic; -- Write
wbm_cyc_i : in std_logic; -- Cycle
wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in
wbm_ack_o : out std_logic; -- Acknowledge
wbm_stall_o : out std_logic; -- Stall
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o : out std_logic_vector(31 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge
wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall
);
end component wb_addr_decoder;
component carrier_csr
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(2 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
carrier_csr_carrier_reserved_i : in std_logic_vector(11 downto 0);
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
carrier_csr_bitstream_type_i : in std_logic_vector(31 downto 0);
carrier_csr_bitstream_date_i : in std_logic_vector(31 downto 0);
carrier_csr_stat_fmc_pres_i : in std_logic;
carrier_csr_stat_p2l_pll_lck_i : in std_logic;
carrier_csr_stat_sys_pll_lck_i : in std_logic;
carrier_csr_stat_ddr3_cal_done_i : in std_logic;
carrier_csr_stat_reserved_i : in std_logic_vector(27 downto 0);
carrier_csr_ctrl_led_green_o : out std_logic;
carrier_csr_ctrl_led_red_o : out std_logic;
carrier_csr_ctrl_dac_clr_n_o : out std_logic;
carrier_csr_ctrl_reserved_o : out std_logic_vector(28 downto 0)
);
end component carrier_csr;
component utc_core
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
trigger_p_i : in std_logic;
acq_start_p_i : in std_logic;
acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end component utc_core;
component irq_controller
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
irq_src_p_i : in std_logic_vector(31 downto 0);
irq_p_o : out std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end component irq_controller;
component fmc_adc_100Ms_core
port (
-- Clock, reset
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(4 downto 0);
wb_csr_dat_i : in std_logic_vector(31 downto 0);
wb_csr_dat_o : out std_logic_vector(31 downto 0);
wb_csr_cyc_i : in std_logic;
wb_csr_sel_i : in std_logic_vector(3 downto 0);
wb_csr_stb_i : in std_logic;
wb_csr_we_i : in std_logic;
wb_csr_ack_o : out std_logic;
-- DDR wishbone interface
wb_ddr_clk_i : in std_logic;
wb_ddr_adr_o : out std_logic_vector(31 downto 0);
wb_ddr_dat_o : out std_logic_vector(63 downto 0);
wb_ddr_sel_o : out std_logic_vector(7 downto 0);
wb_ddr_stb_o : out std_logic;
wb_ddr_we_o : out std_logic;
wb_ddr_cyc_o : out std_logic;
wb_ddr_ack_i : in std_logic;
wb_ddr_stall_i : in std_logic;
-- Events output pulses
trigger_p_o : out std_logic;
acq_start_p_o : out std_logic;
acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
ext_trigger_n_i : in std_logic;
adc_dco_p_i : in std_logic; -- ADC data clock
adc_dco_n_i : in std_logic;
adc_fr_p_i : in std_logic; -- ADC frame start
adc_fr_n_i : in std_logic;
adc_outa_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (odd bits)
adc_outa_n_i : in std_logic_vector(3 downto 0);
adc_outb_p_i : in std_logic_vector(3 downto 0); -- ADC serial data (even bits)
adc_outb_n_i : in std_logic_vector(3 downto 0);
gpio_dac_clr_n_o : out std_logic; -- offset DACs clear (active low)
gpio_led_acq_o : out std_logic; -- Mezzanine front panel power LED (PWR)
gpio_led_trig_o : out std_logic; -- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o : out std_logic_vector(6 downto 0); -- Channel 1 solid state relays control
gpio_ssr_ch2_o : out std_logic_vector(6 downto 0); -- Channel 2 solid state relays control
gpio_ssr_ch3_o : out std_logic_vector(6 downto 0); -- Channel 3 solid state relays control
gpio_ssr_ch4_o : out std_logic_vector(6 downto 0); -- Channel 4 solid state relays control
gpio_si570_oe_o : out std_logic -- Si570 (programmable oscillator) output enable
);
end component fmc_adc_100Ms_core;
component test_dpram
port (
clka : in std_logic;
wea : in std_logic_vector(0 downto 0);
addra : in std_logic_vector(9 downto 0);
dina : in std_logic_vector(31 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(9 downto 0);
doutb : out std_logic_vector(31 downto 0));
end component test_dpram;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
constant c_BITSTREAM_TYPE : std_logic_vector(31 downto 0) := X"00000001";
constant c_BITSTREAM_DATE : std_logic_vector(31 downto 0) := X"4D6BBE3E"; -- UTC time
constant c_BAR0_APERTURE : integer := 18; -- nb of bits for 32-bit word address (= byte aperture - 2)
constant c_CSR_WB_SLAVES_NB : integer := 11;
constant c_CSR_WB_DMA_CONFIG : integer := 0;
constant c_CSR_WB_CARRIER_SPI : integer := 1;
constant c_CSR_WB_CARRIER_ONE_WIRE : integer := 2;
constant c_CSR_WB_CARRIER_CSR : integer := 3;
constant c_CSR_WB_UTC_CORE : integer := 4;
constant c_CSR_WB_IRQ_CTRL : integer := 5;
constant c_CSR_WB_FMC_SYS_I2C : integer := 6;
constant c_CSR_WB_FMC_SPI : integer := 7;
constant c_CSR_WB_FMC_I2C : integer := 8;
constant c_CSR_WB_FMC_ADC_CORE : integer := 9;
constant c_CSR_WB_FMC_ONE_WIRE : integer := 10;
constant c_FMC_ONE_WIRE_NB : integer := 1;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- System clock
signal sys_clk_in : std_logic;
signal sys_clk_125_buf : std_logic;
signal sys_clk_250_buf : std_logic;
signal sys_clk_125 : std_logic;
signal sys_clk_250 : std_logic;
signal sys_clk_fb : std_logic;
signal sys_clk_pll_locked : std_logic;
-- DDR3 clock
signal ddr_clk : std_logic;
signal ddr_clk_buf : std_logic;
-- LCLK from GN4124 used as system clock
signal l_clk : std_logic;
-- Reset
signal rst : std_logic;
signal sys_rst : std_logic;
signal sys_rst_n : std_logic;
-- CSR wishbone bus (master)
signal wbm_adr : std_logic_vector(31 downto 0);
signal wbm_dat_i : std_logic_vector(31 downto 0);
signal wbm_dat_o : std_logic_vector(31 downto 0);
signal wbm_sel : std_logic_vector(3 downto 0);
signal wbm_cyc : std_logic;
signal wbm_stb : std_logic;
signal wbm_we : std_logic;
signal wbm_ack : std_logic;
signal wbm_stall : std_logic;
-- CSR wishbone bus (slaves)
signal wb_adr : std_logic_vector(31 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
-- GN4124 DMA to DDR wishbone bus
signal wb_dma_adr : std_logic_vector(31 downto 0);
signal wb_dma_dat_i : std_logic_vector(31 downto 0);
signal wb_dma_dat_o : std_logic_vector(31 downto 0);
signal wb_dma_sel : std_logic_vector(3 downto 0);
signal wb_dma_cyc : std_logic;
signal wb_dma_stb : std_logic;
signal wb_dma_we : std_logic;
signal wb_dma_ack : std_logic;
signal wb_dma_stall : std_logic;
-- FMC ADC core to DDR wishbone bus
signal wb_ddr_adr : std_logic_vector(31 downto 0);
signal wb_ddr_dat_o : std_logic_vector(63 downto 0);
signal wb_ddr_sel : std_logic_vector(7 downto 0);
signal wb_ddr_cyc : std_logic;
signal wb_ddr_stb : std_logic;
signal wb_ddr_we : std_logic;
signal wb_ddr_ack : std_logic;
signal wb_ddr_stall : std_logic;
-- Interrupts stuff
signal dma_irq : std_logic_vector(1 downto 0);
signal dma_irq_p : std_logic_vector(1 downto 0);
signal irq_sources : std_logic_vector(31 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_sources_2_led : std_logic_vector(1 downto 0);
signal ddr_wr_fifo_empty : std_logic;
signal ddr_wr_fifo_empty_d : std_logic;
signal ddr_wr_fifo_empty_p : std_logic;
signal acq_end_irq_p : std_logic;
signal acq_end : std_logic;
-- Mezzanine I2C for Si570
signal si570_scl_in : std_logic;
signal si570_scl_out : std_logic;
signal si570_scl_oe_n : std_logic;
signal si570_sda_in : std_logic;
signal si570_sda_out : std_logic;
signal si570_sda_oe_n : std_logic;
-- Mezzanine system I2C for EEPROM
signal sys_scl_in : std_logic;
signal sys_scl_out : std_logic;
signal sys_scl_oe_n : std_logic;
signal sys_sda_in : std_logic;
signal sys_sda_out : std_logic;
signal sys_sda_oe_n : std_logic;
-- LED control from carrier CSR register
signal led_red : std_logic;
signal led_green : std_logic;
-- CSR whisbone slaves for test
signal gpio_stat : std_logic_vector(31 downto 0);
signal gpio_ctrl_1 : std_logic_vector(31 downto 0);
signal gpio_ctrl_2 : std_logic_vector(31 downto 0);
signal gpio_ctrl_3 : std_logic_vector(31 downto 0);
signal gpio_led_ctrl : std_logic_vector(31 downto 0);
-- GN4124
signal gn4124_status : std_logic_vector(31 downto 0);
signal p2l_pll_locked : std_logic;
-- DDR3
signal ddr3_status : std_logic_vector(31 downto 0);
signal ddr3_calib_done : std_logic;
-- SPI
signal spi_din_t : std_logic_vector(3 downto 0);
signal spi_ss_t : std_logic_vector(7 downto 0);
-- Mezzanine 1-wire
signal mezz_owr_pwren : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal mezz_owr_en : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal mezz_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
-- Carrier 1-wire
signal carrier_owr_pwren : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal carrier_owr_en : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal carrier_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
-- UTC core
signal trigger_p : std_logic;
signal acq_start_p : std_logic;
signal acq_stop_p : std_logic;
signal acq_end_p : std_logic;
-- Tests
signal test_dpram_we : std_logic;
signal led_cnt : unsigned(26 downto 0);
signal led_pps : std_logic;
begin
------------------------------------------------------------------------------
-- Clocks distribution from 20MHz TCXO
-- 125.000 MHz system clock
-- 250.000 MHz fast system clock
-- 333.333 MHz DDR3 clock
------------------------------------------------------------------------------
cmp_sys_clk_buf : IBUFG
port map (
I => clk20_vcxo_i,
O => sys_clk_in);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => sys_clk_fb,
CLKOUT0 => sys_clk_125_buf,
CLKOUT1 => sys_clk_250_buf,
CLKOUT2 => ddr_clk_buf,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_clk_pll_locked,
RST => '0',
CLKFBIN => sys_clk_fb,
CLKIN => sys_clk_in);
cmp_clk_125_buf : BUFG
port map (
O => sys_clk_125,
I => sys_clk_125_buf);
cmp_clk_250_buf : BUFG
port map (
O => sys_clk_250,
I => sys_clk_250_buf);
cmp_ddr_clk_buf : BUFG
port map (
O => ddr_clk,
I => ddr_clk_buf);
------------------------------------------------------------------------------
-- Local clock from gennum LCLK
------------------------------------------------------------------------------
cmp_l_clk_buf : IBUFDS
generic map (
DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => l_clk, -- Buffer output
I => lclk_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => lclk_n_i -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- System reset
------------------------------------------------------------------------------
sys_rst_n <= gn4124_fpga_rst_i and sys_clk_pll_locked;
sys_rst <= not(sys_rst_n);
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map(
rst_n_a_i => gn4124_fpga_rst_i,
status_o => gn4124_status,
-- P2L Direction Source Sync DDR related signals
p2l_clk_p_i => p2l_clk_p_i,
p2l_clk_n_i => p2l_clk_n_i,
p2l_data_i => p2l_data_i,
p2l_dframe_i => p2l_dframe_i,
p2l_valid_i => p2l_valid_i,
-- P2L Control
p2l_rdy_o => p2l_rdy_o,
p_wr_req_i => p_wr_req_i,
p_wr_rdy_o => p_wr_rdy_o,
rx_error_o => rx_error_o,
-- L2P Direction Source Sync DDR related signals
l2p_clk_p_o => l2p_clk_p_o,
l2p_clk_n_o => l2p_clk_n_o,
l2p_data_o => l2p_data_o,
l2p_dframe_o => l2p_dframe_o,
l2p_valid_o => l2p_valid_o,
l2p_edb_o => l2p_edb_o,
-- L2P Control
l2p_rdy_i => l2p_rdy_i,
l_wr_rdy_i => l_wr_rdy_i,
p_rd_d_rdy_i => p_rd_d_rdy_i,
tx_error_i => tx_error_i,
vc_rdy_i => vc_rdy_i,
-- Interrupt interface
dma_irq_o => dma_irq,
irq_p_i => irq_to_gn4124,
irq_p_o => gpio_irq(0),
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => sys_clk_125,
dma_reg_adr_i => wb_adr,
dma_reg_dat_i => wb_dat_o,
dma_reg_sel_i => wb_sel,
dma_reg_stb_i => wb_stb,
dma_reg_we_i => wb_we,
dma_reg_cyc_i => wb_cyc(c_CSR_WB_DMA_CONFIG),
dma_reg_dat_o => wb_dat_i(c_CSR_WB_DMA_CONFIG * 32 + 31 downto c_CSR_WB_DMA_CONFIG * 32),
dma_reg_ack_o => wb_ack(c_CSR_WB_DMA_CONFIG),
dma_reg_stall_o => wb_stall(c_CSR_WB_DMA_CONFIG),
-- CSR wishbone interface (master pipelined)
csr_clk_i => sys_clk_125,
csr_adr_o => wbm_adr,
csr_dat_o => wbm_dat_o,
csr_sel_o => wbm_sel,
csr_stb_o => wbm_stb,
csr_we_o => wbm_we,
csr_cyc_o => wbm_cyc,
csr_dat_i => wbm_dat_i,
csr_ack_i => wbm_ack,
csr_stall_i => wbm_stall,
-- DMA wishbone interface (pipelined)
dma_clk_i => sys_clk_125,
dma_adr_o => wb_dma_adr,
dma_dat_o => wb_dma_dat_o,
dma_sel_o => wb_dma_sel,
dma_stb_o => wb_dma_stb,
dma_we_o => wb_dma_we,
dma_cyc_o => wb_dma_cyc,
dma_dat_i => wb_dma_dat_i,
dma_ack_i => wb_dma_ack,
dma_stall_i => wb_dma_stall
);
p2l_pll_locked <= gn4124_status(0);
------------------------------------------------------------------------------
-- CSR wishbone address decoder
-- 0x00000 -> DMA configuration
-- 0x10000 -> Carrier SPI master
-- 0x20000 -> Carrier 1-wire master
-- 0x30000 -> Carrier CSR
-- 0x40000 -> UTC core
-- 0x50000 -> Interrupt controller
-- 0x60000 -> Mezzanine system managment I2C master
-- 0x70000 -> Mezzanine SPI master
-- 0x80000 -> Mezzanine I2C master
-- 0x90000 -> Mezzanine ADC core
-- 0xA0000 -> Mezzanine 1-wire master
------------------------------------------------------------------------------
cmp_csr_wb_addr_decoder : wb_addr_decoder
generic map (
g_WINDOW_SIZE => c_BAR0_APERTURE,
g_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB
)
port map (
-- GN4124 core clock and reset
clk_i => sys_clk_125,
rst_n_i => gn4124_fpga_rst_i,
-- wishbone master interface
wbm_adr_i => wbm_adr,
wbm_dat_i => wbm_dat_o,
wbm_sel_i => wbm_sel,
wbm_stb_i => wbm_stb,
wbm_we_i => wbm_we,
wbm_cyc_i => wbm_cyc,
wbm_dat_o => wbm_dat_i,
wbm_ack_o => wbm_ack,
wbm_stall_o => wbm_stall,
-- wishbone slaves interface
wb_adr_o => wb_adr,
wb_dat_o => wb_dat_o,
wb_sel_o => wb_sel,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_cyc_o => wb_cyc,
wb_dat_i => wb_dat_i,
wb_ack_i => wb_ack,
wb_stall_i => wb_stall
);
------------------------------------------------------------------------------
-- Carrier SPI master
-- VCXO DAC control
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Carrier 1-wire master
-- DS18B20 (thermometer + unique ID)
------------------------------------------------------------------------------
cmp_carrier_onewire : wb_onewire_master
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
)
port map(
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_cyc_i => wb_cyc(c_CSR_WB_CARRIER_ONE_WIRE),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_adr_i => wb_adr(2 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_CARRIER_ONE_WIRE * 32 + 31 downto 32 * c_CSR_WB_CARRIER_ONE_WIRE),
wb_ack_o => wb_ack(c_CSR_WB_CARRIER_ONE_WIRE),
wb_int_o => open,
owr_pwren_o => carrier_owr_pwren,
owr_en_o => carrier_owr_en,
owr_i => carrier_owr_i
);
carrier_one_wire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
carrier_owr_i(0) <= carrier_one_wire_b;
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_CARRIER_ONE_WIRE) <= '0';
------------------------------------------------------------------------------
-- Carrier CSR
-- Carrier type and PCB version
-- Bitstream (firmware) type and date
-- Release tag
-- VCXO DAC control (CLR_N)
------------------------------------------------------------------------------
cmp_carrier_csr : carrier_csr
port map(
rst_n_i => sys_rst_n,
wb_clk_i => sys_clk_125,
wb_addr_i => wb_adr(2 downto 0),
wb_data_i => wb_dat_o,
wb_data_o => wb_dat_i(c_CSR_WB_CARRIER_CSR * 32 + 31 downto c_CSR_WB_CARRIER_CSR * 32),
wb_cyc_i => wb_cyc(c_CSR_WB_CARRIER_CSR),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(c_CSR_WB_CARRIER_CSR),
carrier_csr_carrier_pcb_rev_i => pcb_ver_i,
carrier_csr_carrier_reserved_i => X"000",
carrier_csr_carrier_type_i => c_CARRIER_TYPE,
carrier_csr_bitstream_type_i => c_BITSTREAM_TYPE,
carrier_csr_bitstream_date_i => c_BITSTREAM_DATE,
carrier_csr_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_csr_stat_p2l_pll_lck_i => p2l_pll_locked,
carrier_csr_stat_sys_pll_lck_i => sys_clk_pll_locked,
carrier_csr_stat_ddr3_cal_done_i => ddr3_calib_done,
carrier_csr_stat_reserved_i => (others => '0'),
carrier_csr_ctrl_led_green_o => led_green,
carrier_csr_ctrl_led_red_o => led_red,
carrier_csr_ctrl_dac_clr_n_o => open,
carrier_csr_ctrl_reserved_o => open
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_CARRIER_CSR) <= '0';
gen_irq_led : for I in 0 to 1 generate
cmp_irq_led : gc_extend_pulse
generic map (
g_width => 5000000)
port map (
clk_i => sys_clk_125,
rst_n_i => sys_rst_n,
pulse_i => irq_sources(I),
extended_o => irq_sources_2_led(I));
end generate gen_irq_led;
led_red_o <= led_red or irq_sources_2_led(0);
led_green_o <= led_green or irq_sources_2_led(1);
------------------------------------------------------------------------------
-- UTC core
------------------------------------------------------------------------------
cmp_utc_core : utc_core
port map(
clk_i => sys_clk_125,
rst_n_i => sys_rst_n,
trigger_p_i => trigger_p,
acq_start_p_i => acq_start_p,
acq_stop_p_i => acq_stop_p,
acq_end_p_i => acq_end_p,
wb_adr_i => wb_adr(4 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_UTC_CORE * 32 + 31 downto c_CSR_WB_UTC_CORE * 32),
wb_cyc_i => wb_cyc(c_CSR_WB_UTC_CORE),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(c_CSR_WB_UTC_CORE)
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_UTC_CORE) <= '0';
------------------------------------------------------------------------------
-- Interrupt controller
------------------------------------------------------------------------------
cmp_irq_controller : irq_controller
port map(
clk_i => sys_clk_125,
rst_n_i => sys_rst_n,
irq_src_p_i => irq_sources,
irq_p_o => irq_to_gn4124,
wb_adr_i => wb_adr(1 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_IRQ_CTRL * 32 + 31 downto c_CSR_WB_IRQ_CTRL * 32),
wb_cyc_i => wb_cyc(c_CSR_WB_IRQ_CTRL),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(c_CSR_WB_IRQ_CTRL)
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_IRQ_CTRL) <= '0';
-- IRQ sources
-- 0 -> End of DMA transfer
-- 1 -> DMA transfer error
-- 2 -> Trigger
-- 3 -> End of acquisition (data written to DDR)
-- 4-31 -> Unused
irq_sources(1 downto 0) <= dma_irq;
irq_sources(2) <= trigger_p;
irq_sources(3) <= acq_end_irq_p;
irq_sources(31 downto 4) <= (others => '0');
-- End of acquisition interrupt generation
p_ddr_wr_fifo_empty : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
ddr_wr_fifo_empty_d <= ddr_wr_fifo_empty;
end if;
end process p_ddr_wr_fifo_empty;
ddr_wr_fifo_empty_p <= ddr_wr_fifo_empty and not(ddr_wr_fifo_empty_d);
p_acq_end : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
acq_end <= '0';
elsif acq_end_p = '1' then
acq_end <= '1';
elsif ddr_wr_fifo_empty_p = '1' then
acq_end <= '0';
end if;
end if;
end process p_acq_end;
acq_end_irq_p <= ddr_wr_fifo_empty_p and acq_end;
-- just forward irq pulses for test
--irq_to_gn4124 <= dma_irq(1) or dma_irq(0);
------------------------------------------------------------------------------
-- Mezzanine system managment I2C master
-- Access to mezzanine EEPROM
------------------------------------------------------------------------------
cmp_fmc_sys_i2c : wb_i2c_master
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
)
port map (
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_adr_i => wb_adr(4 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_FMC_SYS_I2C * 32 + 31 downto 32 * c_CSR_WB_FMC_SYS_I2C),
wb_we_i => wb_we,
wb_stb_i => wb_stb,
wb_sel_i => wb_sel,
wb_cyc_i => wb_cyc(c_CSR_WB_FMC_SYS_I2C),
wb_ack_o => wb_ack(c_CSR_WB_FMC_SYS_I2C),
wb_int_o => open,
scl_pad_i => sys_scl_in,
scl_pad_o => sys_scl_out,
scl_padoen_o => sys_scl_oe_n,
sda_pad_i => sys_sda_in,
sda_pad_o => sys_sda_out,
sda_padoen_o => sys_sda_oe_n
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_FMC_SYS_I2C) <= '0';
-- Tri-state buffer for SDA and SCL
sys_scl_b <= sys_scl_out when sys_scl_oe_n = '0' else 'Z';
sys_scl_in <= sys_scl_b;
sys_sda_b <= sys_sda_out when sys_sda_oe_n = '0' else 'Z';
sys_sda_in <= sys_sda_b;
------------------------------------------------------------------------------
-- Mezzanine SPI master
-- Offset DACs control
-- ADC control
------------------------------------------------------------------------------
cmp_fmc_spi : wb_spi
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
)
port map (
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_adr_i => wb_adr(4 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_FMC_SPI * 32 + 31 downto c_CSR_WB_FMC_SPI * 32),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_cyc_i => wb_cyc(c_CSR_WB_FMC_SPI),
wb_we_i => wb_we,
wb_ack_o => wb_ack(c_CSR_WB_FMC_SPI),
wb_err_o => open,
wb_int_o => open,
pad_cs_o => spi_ss_t,
pad_sclk_o => spi_sck_o,
pad_mosi_o => spi_dout_o,
pad_miso_i => spi_din_t(spi_din_t'left)
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_FMC_SPI) <= '0';
-- Assign slave select lines
spi_cs_adc_n_o <= spi_ss_t(0);
spi_cs_dac1_n_o <= spi_ss_t(1);
spi_cs_dac2_n_o <= spi_ss_t(2);
spi_cs_dac3_n_o <= spi_ss_t(3);
spi_cs_dac4_n_o <= spi_ss_t(4);
-- Add some FF after the input pin to solve timing problem
p_fmc_spi : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
spi_din_t <= (others => '0');
else
spi_din_t <= spi_din_t(spi_din_t'left-1 downto 0) & spi_din_i;
end if;
end if;
end process p_fmc_spi;
------------------------------------------------------------------------------
-- Mezzanine I2C
-- Si570 control
--
-- Note: I2C registers are 8-bit wide, but accessed as 32-bit registers
------------------------------------------------------------------------------
cmp_fmc_i2c : wb_i2c_master
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
)
port map (
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_adr_i => wb_adr(4 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_FMC_I2C * 32 + 31 downto 32 * c_CSR_WB_FMC_I2C),
wb_we_i => wb_we,
wb_stb_i => wb_stb,
wb_sel_i => wb_sel,
wb_cyc_i => wb_cyc(c_CSR_WB_FMC_I2C),
wb_ack_o => wb_ack(c_CSR_WB_FMC_I2C),
wb_int_o => open,
scl_pad_i => si570_scl_in,
scl_pad_o => si570_scl_out,
scl_padoen_o => si570_scl_oe_n,
sda_pad_i => si570_sda_in,
sda_pad_o => si570_sda_out,
sda_padoen_o => si570_sda_oe_n
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_FMC_I2C) <= '0';
-- Tri-state buffer for SDA and SCL
si570_scl_b <= si570_scl_out when si570_scl_oe_n = '0' else 'Z';
si570_scl_in <= si570_scl_b;
si570_sda_b <= si570_sda_out when si570_sda_oe_n = '0' else 'Z';
si570_sda_in <= si570_sda_b;
------------------------------------------------------------------------------
-- ADC core
-- Solid State Relays control
-- Si570 output enable
-- Offset DACs control (CLR_N)
-- ADC core control and status
------------------------------------------------------------------------------
cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core
port map(
sys_clk_i => sys_clk_125,
sys_rst_n_i => sys_rst_n,
wb_csr_adr_i => wb_adr(4 downto 0),
wb_csr_dat_i => wb_dat_o,
wb_csr_dat_o => wb_dat_i(c_CSR_WB_FMC_ADC_CORE * 32 + 31 downto c_CSR_WB_FMC_ADC_CORE * 32),
wb_csr_cyc_i => wb_cyc(c_CSR_WB_FMC_ADC_CORE),
wb_csr_sel_i => wb_sel,
wb_csr_stb_i => wb_stb,
wb_csr_we_i => wb_we,
wb_csr_ack_o => wb_ack(c_CSR_WB_FMC_ADC_CORE),
wb_ddr_clk_i => sys_clk_125,
wb_ddr_adr_o => wb_ddr_adr,
wb_ddr_dat_o => wb_ddr_dat_o,
wb_ddr_sel_o => wb_ddr_sel,
wb_ddr_stb_o => wb_ddr_stb,
wb_ddr_we_o => wb_ddr_we,
wb_ddr_cyc_o => wb_ddr_cyc,
wb_ddr_ack_i => wb_ddr_ack,
wb_ddr_stall_i => wb_ddr_stall,
trigger_p_o => trigger_p,
acq_start_p_o => acq_start_p,
acq_stop_p_o => acq_stop_p,
acq_end_p_o => acq_end_p,
ext_trigger_p_i => ext_trigger_p_i,
ext_trigger_n_i => ext_trigger_n_i,
adc_dco_p_i => adc_dco_p_i,
adc_dco_n_i => adc_dco_n_i,
adc_fr_p_i => adc_fr_p_i,
adc_fr_n_i => adc_fr_n_i,
adc_outa_p_i => adc_outa_p_i,
adc_outa_n_i => adc_outa_n_i,
adc_outb_p_i => adc_outb_p_i,
adc_outb_n_i => adc_outb_n_i,
gpio_dac_clr_n_o => gpio_dac_clr_n_o,
gpio_led_acq_o => gpio_led_power_o,
gpio_led_trig_o => gpio_led_trigger_o,
gpio_ssr_ch1_o => gpio_ssr_ch1_o,
gpio_ssr_ch2_o => gpio_ssr_ch2_o,
gpio_ssr_ch3_o => gpio_ssr_ch3_o,
gpio_ssr_ch4_o => gpio_ssr_ch4_o,
gpio_si570_oe_o => gpio_si570_oe_o
);
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_FMC_ADC_CORE) <= '0';
------------------------------------------------------------------------------
-- Mezzanine 1-wire master
-- DS18B20 (thermometer + unique ID)
------------------------------------------------------------------------------
cmp_fmc_onewire : wb_onewire_master
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
)
port map(
clk_sys_i => sys_clk_125,
rst_n_i => sys_rst_n,
wb_cyc_i => wb_cyc(c_CSR_WB_FMC_ONE_WIRE),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_adr_i => wb_adr(2 downto 0),
wb_dat_i => wb_dat_o,
wb_dat_o => wb_dat_i(c_CSR_WB_FMC_ONE_WIRE * 32 + 31 downto 32 * c_CSR_WB_FMC_ONE_WIRE),
wb_ack_o => wb_ack(c_CSR_WB_FMC_ONE_WIRE),
wb_int_o => open,
owr_pwren_o => mezz_owr_pwren,
owr_en_o => mezz_owr_en,
owr_i => mezz_owr_i
);
mezz_one_wire_b <= '0' when mezz_owr_en(0) = '1' else 'Z';
mezz_owr_i(0) <= mezz_one_wire_b;
-- Classic slave supporting single pipelined accesses, stall isn't used
wb_stall(c_CSR_WB_FMC_ONE_WIRE) <= '0';
------------------------------------------------------------------------------
-- DMA wishbone bus slaves
-- -> DDR3 controller
------------------------------------------------------------------------------
cmp_ddr_ctrl : ddr3_ctrl
generic map(
g_BANK_PORT_SELECT => "SPEC_BANK3_64B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => g_SIMULATION,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 8,
g_P0_DATA_PORT_SIZE => 64,
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => ddr_clk,
rst_n_i => sys_rst_n,
status_o => ddr3_status,
ddr3_dq_b => ddr3_dq_b,
ddr3_a_o => ddr3_a_o,
ddr3_ba_o => ddr3_ba_o,
ddr3_ras_n_o => ddr3_ras_n_o,
ddr3_cas_n_o => ddr3_cas_n_o,
ddr3_we_n_o => ddr3_we_n_o,
ddr3_odt_o => ddr3_odt_o,
ddr3_rst_n_o => ddr3_reset_n_o,
ddr3_cke_o => ddr3_cke_o,
ddr3_dm_o => ddr3_ldm_o,
ddr3_udm_o => ddr3_udm_o,
ddr3_dqs_p_b => ddr3_ldqs_p_b,
ddr3_dqs_n_b => ddr3_ldqs_n_b,
ddr3_udqs_p_b => ddr3_udqs_p_b,
ddr3_udqs_n_b => ddr3_udqs_n_b,
ddr3_clk_p_o => ddr3_ck_p_o,
ddr3_clk_n_o => ddr3_ck_n_o,
ddr3_rzq_b => ddr3_rzq_b,
ddr3_zio_b => ddr3_zio_b,
--wb0_clk_i => '0',
--wb0_sel_i => "0000",
--wb0_cyc_i => '0',
--wb0_stb_i => '0',
--wb0_we_i => '0',
--wb0_addr_i => X"0000000",
--wb0_data_i => X"00000000",
--wb0_data_o => open,
--wb0_ack_o => open,
--wb0_stall_o => open,
--wb1_clk_i => '0',
--wb1_sel_i => "0000",
--wb1_cyc_i => '0',
--wb1_stb_i => '0',
--wb1_we_i => '0',
--wb1_addr_i => X"0000000",
--wb1_data_i => X"00000000",
--wb1_data_o => open,
--wb1_ack_o => open,
--wb1_stall_o => open);
wb0_clk_i => sys_clk_125,
wb0_sel_i => wb_ddr_sel,
wb0_cyc_i => wb_ddr_cyc,
wb0_stb_i => wb_ddr_stb,
wb0_we_i => wb_ddr_we,
wb0_addr_i => wb_ddr_adr,
wb0_data_i => wb_ddr_dat_o,
wb0_data_o => open,
wb0_ack_o => wb_ddr_ack,
wb0_stall_o => wb_ddr_stall,
p0_cmd_empty_o => open,
p0_cmd_full_o => open,
p0_rd_full_o => open,
p0_rd_empty_o => open,
p0_rd_count_o => open,
p0_rd_overflow_o => open,
p0_rd_error_o => open,
p0_wr_full_o => open,
p0_wr_empty_o => ddr_wr_fifo_empty,
p0_wr_count_o => open,
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_clk_i => sys_clk_125,
wb1_sel_i => wb_dma_sel,
wb1_cyc_i => wb_dma_cyc,
wb1_stb_i => wb_dma_stb,
wb1_we_i => wb_dma_we,
wb1_addr_i => wb_dma_adr,
wb1_data_i => wb_dma_dat_o,
wb1_data_o => wb_dma_dat_i,
wb1_ack_o => wb_dma_ack,
wb1_stall_o => wb_dma_stall,
p1_cmd_empty_o => open,
p1_cmd_full_o => open,
p1_rd_full_o => open,
p1_rd_empty_o => open,
p1_rd_count_o => open,
p1_rd_overflow_o => open,
p1_rd_error_o => open,
p1_wr_full_o => open,
p1_wr_empty_o => open,
p1_wr_count_o => open,
p1_wr_underrun_o => open,
p1_wr_error_o => open
);
ddr3_calib_done <= ddr3_status(0);
--wb_ddr_stall <= '0';
--test_dpram_we <= wb_ddr_we and wb_ddr_stb and wb_ddr_cyc;
--p_test_dpram_wr_ack : process (sys_clk_250)
--begin
-- if rising_edge(sys_clk_250) then
-- if sys_rst_n = '0' then
-- wb_ddr_ack <= '0';
-- elsif wb_ddr_cyc = '1' and wb_ddr_stb = '1' then
-- wb_ddr_ack <= '1';
-- else
-- wb_ddr_ack <= '0';
-- end if;
-- end if;
--end process p_test_dpram_wr_ack;
--cmp_test_dpram : test_dpram
-- port map(
-- clka => sys_clk_250,
-- wea(0) => test_dpram_we, --: in std_logic_vector(0 downto 0);
-- addra => wb_ddr_adr(9 downto 0), --: in std_logic_vector(9 downto 0);
-- dina => wb_ddr_dat_o, --: in std_logic_vector(31 downto 0);
-- clkb => sys_clk_125,
-- addrb => wb_dma_adr(9 downto 0), --: in std_logic_vector(9 downto 0);
-- doutb => wb_dma_dat_i); --: out std_logic_vector(31 downto 0));
--p_test_dpram_rd_ack : process (sys_clk_125)
--begin
-- if rising_edge(sys_clk_125) then
-- if sys_rst_n = '0' then
-- wb_dma_ack <= '0';
-- elsif wb_dma_cyc = '1' and wb_dma_stb = '1' then
-- wb_dma_ack <= '1';
-- else
-- wb_dma_ack <= '0';
-- end if;
-- end if;
--end process p_test_dpram_rd_ack;
--wb_dma_stall <= '0';
------------------------------------------------------------------------------
-- Assign unused outputs
------------------------------------------------------------------------------
gpio_irq(1) <= '0';
------------------------------------------------------------------------------
-- Blink auxiliary LEDs
------------------------------------------------------------------------------
p_led_cnt : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if (sys_rst_n = '0') then
led_cnt <= (others => '0');
led_pps <= '0';
elsif (led_cnt = X"773593F") then
led_cnt <= (others => '0');
led_pps <= not(led_pps);
else
led_cnt <= led_cnt + 1;
end if;
end if;
end process p_led_cnt;
p_led_blink : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
aux_leds_o <= X"5";
elsif led_pps = '1' then
aux_leds_o <= X"A";
else
aux_leds_o <= X"5";
end if;
end if;
end process p_led_blink;
end rtl;
hdl/spexi/rtl/utc_core.vhd 0 → 100644
View file @ 09563ffb
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- UTC core
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: utc_core (utc_core.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 18-11-2011
--
-- version: 1.0
--
-- description: Implements a UTC seconds counter and a 125MHz system clock ticks
-- counter to time-tag trigger, acquisition start and stop events.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity utc_core is
port (
-- Clock, reset
clk_i : in std_logic; -- Must be 125MHz
rst_n_i : in std_logic;
-- Input pulses to time-tag
trigger_p_i : in std_logic;
acq_start_p_i : in std_logic;
acq_stop_p_i : in std_logic;
acq_end_p_i : in std_logic;
-- Wishbone interface
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end utc_core;
architecture rtl of utc_core is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component utc_core_regs
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
utc_core_seconds_o : out std_logic_vector(31 downto 0);
utc_core_seconds_i : in std_logic_vector(31 downto 0);
utc_core_seconds_load_o : out std_logic;
utc_core_coarse_o : out std_logic_vector(31 downto 0);
utc_core_coarse_i : in std_logic_vector(31 downto 0);
utc_core_coarse_load_o : out std_logic;
utc_core_trig_tag_meta_i : in std_logic_vector(31 downto 0);
utc_core_trig_tag_seconds_i : in std_logic_vector(31 downto 0);
utc_core_trig_tag_coarse_i : in std_logic_vector(31 downto 0);
utc_core_trig_tag_fine_i : in std_logic_vector(31 downto 0);
utc_core_acq_start_tag_meta_i : in std_logic_vector(31 downto 0);
utc_core_acq_start_tag_seconds_i : in std_logic_vector(31 downto 0);
utc_core_acq_start_tag_coarse_i : in std_logic_vector(31 downto 0);
utc_core_acq_start_tag_fine_i : in std_logic_vector(31 downto 0);
utc_core_acq_stop_tag_meta_i : in std_logic_vector(31 downto 0);
utc_core_acq_stop_tag_seconds_i : in std_logic_vector(31 downto 0);
utc_core_acq_stop_tag_coarse_i : in std_logic_vector(31 downto 0);
utc_core_acq_stop_tag_fine_i : in std_logic_vector(31 downto 0);
utc_core_acq_end_tag_meta_i : in std_logic_vector(31 downto 0);
utc_core_acq_end_tag_seconds_i : in std_logic_vector(31 downto 0);
utc_core_acq_end_tag_coarse_i : in std_logic_vector(31 downto 0);
utc_core_acq_end_tag_fine_i : in std_logic_vector(31 downto 0)
);
end component utc_core_regs;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal utc_seconds : std_logic_vector(31 downto 0);
signal utc_seconds_cnt : unsigned(31 downto 0);
signal utc_seconds_load_value : std_logic_vector(31 downto 0);
signal utc_seconds_load_en : std_logic;
signal utc_coarse : std_logic_vector(31 downto 0);
signal utc_coarse_cnt : unsigned(31 downto 0);
signal utc_coarse_load_value : std_logic_vector(31 downto 0);
signal utc_coarse_load_en : std_logic;
signal utc_trig_tag_meta : std_logic_vector(31 downto 0);
signal utc_trig_tag_seconds : std_logic_vector(31 downto 0);
signal utc_trig_tag_coarse : std_logic_vector(31 downto 0);
signal utc_trig_tag_fine : std_logic_vector(31 downto 0);
signal utc_acq_start_tag_meta : std_logic_vector(31 downto 0);
signal utc_acq_start_tag_seconds : std_logic_vector(31 downto 0);
signal utc_acq_start_tag_coarse : std_logic_vector(31 downto 0);
signal utc_acq_start_tag_fine : std_logic_vector(31 downto 0);
signal utc_acq_stop_tag_meta : std_logic_vector(31 downto 0);
signal utc_acq_stop_tag_seconds : std_logic_vector(31 downto 0);
signal utc_acq_stop_tag_coarse : std_logic_vector(31 downto 0);
signal utc_acq_stop_tag_fine : std_logic_vector(31 downto 0);
signal utc_acq_end_tag_meta : std_logic_vector(31 downto 0);
signal utc_acq_end_tag_seconds : std_logic_vector(31 downto 0);
signal utc_acq_end_tag_coarse : std_logic_vector(31 downto 0);
signal utc_acq_end_tag_fine : std_logic_vector(31 downto 0);
signal local_pps : std_logic;
begin
------------------------------------------------------------------------------
-- Wishbone interface to UTC core registers
------------------------------------------------------------------------------
cmp_utc_core_regs : utc_core_regs
port map(
rst_n_i => rst_n_i,
wb_clk_i => clk_i,
wb_addr_i => wb_adr_i,
wb_data_i => wb_dat_i,
wb_data_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
utc_core_seconds_o => utc_seconds_load_value,
utc_core_seconds_i => utc_seconds,
utc_core_seconds_load_o => utc_seconds_load_en,
utc_core_coarse_o => utc_coarse_load_value,
utc_core_coarse_i => utc_coarse,
utc_core_coarse_load_o => utc_coarse_load_en,
utc_core_trig_tag_meta_i => utc_trig_tag_meta,
utc_core_trig_tag_seconds_i => utc_trig_tag_seconds,
utc_core_trig_tag_coarse_i => utc_trig_tag_coarse,
utc_core_trig_tag_fine_i => utc_trig_tag_fine,
utc_core_acq_start_tag_meta_i => utc_acq_start_tag_meta,
utc_core_acq_start_tag_seconds_i => utc_acq_start_tag_seconds,
utc_core_acq_start_tag_coarse_i => utc_acq_start_tag_coarse,
utc_core_acq_start_tag_fine_i => utc_acq_start_tag_fine,
utc_core_acq_stop_tag_meta_i => utc_acq_stop_tag_meta,
utc_core_acq_stop_tag_seconds_i => utc_acq_stop_tag_seconds,
utc_core_acq_stop_tag_coarse_i => utc_acq_stop_tag_coarse,
utc_core_acq_stop_tag_fine_i => utc_acq_stop_tag_fine,
utc_core_acq_end_tag_meta_i => utc_acq_end_tag_meta,
utc_core_acq_end_tag_seconds_i => utc_acq_end_tag_seconds,
utc_core_acq_end_tag_coarse_i => utc_acq_end_tag_coarse,
utc_core_acq_end_tag_fine_i => utc_acq_end_tag_fine
);
------------------------------------------------------------------------------
-- UTC seconds counter
------------------------------------------------------------------------------
p_utc_seconds_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
utc_seconds_cnt <= (others => '0');
elsif utc_seconds_load_en = '1' then
utc_seconds_cnt <= unsigned(utc_seconds_load_value);
elsif local_pps = '1' then
utc_seconds_cnt <= utc_seconds_cnt + 1;
end if;
end if;
end process p_utc_seconds_cnt;
utc_seconds <= std_logic_vector(utc_seconds_cnt);
------------------------------------------------------------------------------
-- UTC 125MHz clock ticks counter
------------------------------------------------------------------------------
p_utc_coarse_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
utc_coarse_cnt <= (others => '0');
local_pps <= '0';
elsif utc_coarse_load_en = '1' then
utc_coarse_cnt <= unsigned(utc_coarse_load_value);
local_pps <= '0';
elsif utc_coarse_cnt = to_unsigned(124999999, utc_coarse_cnt'length) then
utc_coarse_cnt <= (others => '0');
local_pps <= '1';
else
utc_coarse_cnt <= utc_coarse_cnt + 1;
local_pps <= '0';
end if;
end if;
end process p_utc_coarse_cnt;
utc_coarse <= std_logic_vector(utc_coarse_cnt);
------------------------------------------------------------------------------
-- Last trigger event time-tag
------------------------------------------------------------------------------
p_trig_tag : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
utc_trig_tag_seconds <= (others => '0');
utc_trig_tag_coarse <= (others => '0');
utc_trig_tag_fine <= (others => '0');
elsif trigger_p_i = '1' then
utc_trig_tag_seconds <= utc_seconds;
utc_trig_tag_coarse <= utc_coarse;
end if;
end if;
end process p_trig_tag;
utc_trig_tag_meta <= X"00000000";
------------------------------------------------------------------------------
-- Last acquisition start event time-tag
------------------------------------------------------------------------------
p_acq_start_tag : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
utc_acq_start_tag_seconds <= (others => '0');
utc_acq_start_tag_coarse <= (others => '0');
utc_acq_start_tag_fine <= (others => '0');
elsif acq_start_p_i = '1' then
utc_acq_start_tag_seconds <= utc_seconds;
utc_acq_start_tag_coarse <= utc_coarse;
end if;
end if;
end process p_acq_start_tag;
utc_acq_start_tag_meta <= X"00000000";
------------------------------------------------------------------------------
-- Last acquisition stop event time-tag
------------------------------------------------------------------------------
p_acq_stop_tag : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
utc_acq_stop_tag_seconds <= (others => '0');
utc_acq_stop_tag_coarse <= (others => '0');
utc_acq_stop_tag_fine <= (others => '0');
elsif acq_stop_p_i = '1' then
utc_acq_stop_tag_seconds <= utc_seconds;
utc_acq_stop_tag_coarse <= utc_coarse;
end if;
end if;
end process p_acq_stop_tag;
utc_acq_stop_tag_meta <= X"00000000";
------------------------------------------------------------------------------
-- Last acquisition end event time-tag
------------------------------------------------------------------------------
p_acq_end_tag : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
utc_acq_end_tag_seconds <= (others => '0');
utc_acq_end_tag_coarse <= (others => '0');
utc_acq_end_tag_fine <= (others => '0');
elsif acq_end_p_i = '1' then
utc_acq_end_tag_seconds <= utc_seconds;
utc_acq_end_tag_coarse <= utc_coarse;
end if;
end if;
end process p_acq_end_tag;
utc_acq_end_tag_meta <= X"00000000";
end rtl;
hdl/spexi/rtl/utc_core_regs.vhd 0 → 100644
View file @ 09563ffb
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for UTC core registers
---------------------------------------------------------------------------------------
-- File : ../rtl/utc_core_regs.vhd
-- Author : auto-generated by wbgen2 from utc_core_regs.wb
-- Created : Tue Nov 22 10:20:36 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE utc_core_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity utc_core_regs is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(4 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Port for std_logic_vector field: 'UTC seconds' in reg: 'UTC seconds register'
utc_core_seconds_o : out std_logic_vector(31 downto 0);
utc_core_seconds_i : in std_logic_vector(31 downto 0);
utc_core_seconds_load_o : out std_logic;
-- Port for std_logic_vector field: 'UTC coarse time' in reg: 'UTC coarse time register, system clock ticks (125MHz)'
utc_core_coarse_o : out std_logic_vector(31 downto 0);
utc_core_coarse_i : in std_logic_vector(31 downto 0);
utc_core_coarse_load_o : out std_logic;
-- Port for std_logic_vector field: 'Trigger time-tag metadata' in reg: 'Trigger time-tag metadata register'
utc_core_trig_tag_meta_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Trigger time-tag UTC seconds' in reg: 'Trigger time-tag UTC seconds register'
utc_core_trig_tag_seconds_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Trigger time-tag coarse time' in reg: 'Trigger time-tag coarse time (system clock ticks 125MHz) register'
utc_core_trig_tag_coarse_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Trigger time-tag fine time' in reg: 'Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)'
utc_core_trig_tag_fine_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition start time-tag metadata' in reg: 'Acquisition start time-tag metadata register'
utc_core_acq_start_tag_meta_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition start time-tag UTC seconds' in reg: 'Acquisition start time-tag UTC seconds register'
utc_core_acq_start_tag_seconds_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition start time-tag coarse time' in reg: 'Acquisition start time-tag coarse time (system clock ticks 125MHz) register'
utc_core_acq_start_tag_coarse_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition start time-tag fine time' in reg: 'Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)'
utc_core_acq_start_tag_fine_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag metadata' in reg: 'Acquisition stop time-tag metadata register'
utc_core_acq_stop_tag_meta_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag UTC seconds' in reg: 'Acquisition stop time-tag UTC seconds register'
utc_core_acq_stop_tag_seconds_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag coarse time' in reg: 'Acquisition stop time-tag coarse time (system clock ticks 125MHz) register'
utc_core_acq_stop_tag_coarse_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition stop time-tag fine time' in reg: 'Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)'
utc_core_acq_stop_tag_fine_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition end time-tag metadata' in reg: 'Acquisition end time-tag metadata register'
utc_core_acq_end_tag_meta_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition end time-tag UTC seconds' in reg: 'Acquisition end time-tag UTC seconds register'
utc_core_acq_end_tag_seconds_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition end time-tag coarse time' in reg: 'Acquisition end time-tag coarse time (system clock ticks 125MHz) register'
utc_core_acq_end_tag_coarse_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Acquisition end time-tag fine time' in reg: 'Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility)'
utc_core_acq_end_tag_fine_i : in std_logic_vector(31 downto 0)
);
end utc_core_regs;
architecture syn of utc_core_regs is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
utc_core_seconds_load_o <= '0';
utc_core_coarse_load_o <= '0';
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
utc_core_seconds_load_o <= '0';
utc_core_coarse_load_o <= '0';
ack_in_progress <= '0';
else
utc_core_seconds_load_o <= '0';
utc_core_coarse_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
utc_core_seconds_load_o <= '1';
else
rddata_reg(31 downto 0) <= utc_core_seconds_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
utc_core_coarse_load_o <= '1';
else
rddata_reg(31 downto 0) <= utc_core_coarse_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_meta_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_seconds_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_coarse_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_trig_tag_fine_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_meta_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_seconds_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_coarse_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_start_tag_fine_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_meta_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_seconds_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_coarse_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_stop_tag_fine_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_meta_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_seconds_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_coarse_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= utc_core_acq_end_tag_fine_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- UTC seconds
utc_core_seconds_o <= wrdata_reg(31 downto 0);
-- UTC coarse time
utc_core_coarse_o <= wrdata_reg(31 downto 0);
-- Trigger time-tag metadata
-- Trigger time-tag UTC seconds
-- Trigger time-tag coarse time
-- Trigger time-tag fine time
-- Acquisition start time-tag metadata
-- Acquisition start time-tag UTC seconds
-- Acquisition start time-tag coarse time
-- Acquisition start time-tag fine time
-- Acquisition stop time-tag metadata
-- Acquisition stop time-tag UTC seconds
-- Acquisition stop time-tag coarse time
-- Acquisition stop time-tag fine time
-- Acquisition end time-tag metadata
-- Acquisition end time-tag UTC seconds
-- Acquisition end time-tag coarse time
-- Acquisition end time-tag fine time
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/spexi/spexi_v0_1.ucf 0 → 100644
View file @ 09563ffb
#===============================================================================
# The IO Location Constraints
#===============================================================================
#----------------------------------------
# Clock inputs
#----------------------------------------
NET "clk20_vcxo_i" LOC = W28;
NET "clk20_vcxo_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_clk_n" LOC = AB30;
#NET "fpga_clk_n" IOSTANDARD = "LVDS_33";
#NET "fpga_clk_p" LOC = AB28;
#NET "fpga_clk_p" IOSTANDARD = "LVDS_33";
#----------------------------------------
# SFP slot
#----------------------------------------
#NET "sfptx_p" LOC = AJ23;
#NET "sfptx_n" LOC = AK23;
#NET "sfprx_p" LOC = AG22;
#NET "sfprx_n" LOC = AH22;
#NET "sfp_los" LOC = AA30;
#NET "sfp_tx_fault" LOC = AA29;
#NET "sfp_tx_fault" IOSTANDARD = "LVCMOS33";
#NET "sfp_tx_disable" LOC = Y26;
#NET "sfp_tx_disable" IOSTANDARD = "LVCMOS33";
#NET "sfp_rate_select" LOC = Y28;
#NET "sfp_rate_select" IOSTANDARD = "LVCMOS33";
#NET "sfp_mod_def2" LOC = AA28;
#NET "sfp_mod_def2" IOSTANDARD = "LVCMOS33";
#NET "sfp_mod_def1" LOC = AA27;
#NET "sfp_mod_def1" IOSTANDARD = "LVCMOS33";
#NET "sfp_mod_def0" LOC = Y30;
#NET "sfp_mod_def0" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# DAC interface (for VCXO)
#----------------------------------------
#NET "pll25dac1_sync_n" LOC = N28;
#NET "pll25dac1_sync_n" IOSTANDARD = "LVCMOS33";
#NET "pll25dac2_sync_n" LOC = N27;
#NET "pll25dac2_sync_n" IOSTANDARD = "LVCMOS33";
#NET "pll25dac_din" LOC = N29;
#NET "pll25dac_din" IOSTANDARD = "LVCMOS33";
#NET "pll25dac_sclk" LOC = N30;
#NET "pll25dac_sclk" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# 1-wire thermometer w/ ID
#----------------------------------------
NET "carrier_one_wire_b" LOC = V28;
NET "carrier_one_wire_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "gpio_irq[1]" LOC = M23;
NET "gpio_irq[1]" IOSTANDARD = "LVCMOS33";
NET "gpio_irq[0]" LOC = M24;
NET "gpio_irq[0]" IOSTANDARD = "LVCMOS33";
NET "gn4124_fpga_rst_i" LOC = E21;
NET "gn4124_fpga_rst_i" IOSTANDARD = "LVCMOS18";
NET "vc_rdy_i[1]" LOC = E6;
NET "vc_rdy_i[1]" IOSTANDARD = "SSTL18_I";
NET "vc_rdy_i[0]" LOC = F6;
NET "vc_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "p_wr_req_i[1]" LOC = H13;
NET "p_wr_req_i[1]" IOSTANDARD = "SSTL18_I";
NET "p_wr_req_i[0]" LOC = D7;
NET "p_wr_req_i[0]" IOSTANDARD = "SSTL18_I";
NET "p_wr_rdy_o[1]" LOC = D8;
NET "p_wr_rdy_o[1]" IOSTANDARD = "SSTL18_I";
NET "p_wr_rdy_o[0]" LOC = L13;
NET "p_wr_rdy_o[0]" IOSTANDARD = "SSTL18_I";
NET "p_rd_d_rdy_i[1]" LOC = F17;
NET "p_rd_d_rdy_i[1]" IOSTANDARD = "SSTL18_I";
NET "p_rd_d_rdy_i[0]" LOC = F19;
NET "p_rd_d_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "p2l_valid_i" LOC = A7;
NET "p2l_valid_i" IOSTANDARD = "SSTL18_I";
NET "p2l_rdy_o" LOC = B7;
NET "p2l_rdy_o" IOSTANDARD = "SSTL18_I";
NET "p2l_dframe_i" LOC = E9;
NET "p2l_dframe_i" IOSTANDARD = "SSTL18_I";
NET "p2l_clk_p_i" LOC = B15;
NET "p2l_clk_p_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_clk_n_i" LOC = A15;
NET "p2l_clk_n_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "tx_error_i" LOC = G17;
NET "tx_error_i" IOSTANDARD = "SSTL18_I";
NET "rx_error_o" LOC = E7;
NET "rx_error_o" IOSTANDARD = "SSTL18_I";
NET "lclk_p_i" LOC = C16;
NET "lclk_p_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "lclk_n_i" LOC = A16;
NET "lclk_n_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "l_wr_rdy_i[1]" LOC = G16;
NET "l_wr_rdy_i[1]" IOSTANDARD = "SSTL18_I";
NET "l_wr_rdy_i[0]" LOC = B17;
NET "l_wr_rdy_i[0]" IOSTANDARD = "SSTL18_I";
NET "l2p_valid_o" LOC = A25;
NET "l2p_valid_o" IOSTANDARD = "SSTL18_I";
NET "l2p_rdy_i" LOC = D24;
NET "l2p_rdy_i" IOSTANDARD = "SSTL18_I";
NET "l2p_edb_o" LOC = F20;
NET "l2p_edb_o" IOSTANDARD = "SSTL18_I";
NET "l2p_dframe_o" LOC = F21;
NET "l2p_dframe_o" IOSTANDARD = "SSTL18_I";
NET "l2p_clk_p_o" LOC = E16;
NET "l2p_clk_p_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "l2p_clk_n_o" LOC = D16;
NET "l2p_clk_n_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "p2l_data_i[15]" LOC = H11;
NET "p2l_data_i[15]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[14]" LOC = H7;
NET "p2l_data_i[14]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[13]" LOC = E8;
NET "p2l_data_i[13]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[12]" LOC = F8;
NET "p2l_data_i[12]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[11]" LOC = B6;
NET "p2l_data_i[11]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[10]" LOC = F9;
NET "p2l_data_i[10]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[9]" LOC = F13;
NET "p2l_data_i[9]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[8]" LOC = F14;
NET "p2l_data_i[8]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[7]" LOC = D6;
NET "p2l_data_i[7]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[6]" LOC = C6;
NET "p2l_data_i[6]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[5]" LOC = H8;
NET "p2l_data_i[5]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[4]" LOC = F11;
NET "p2l_data_i[4]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[3]" LOC = C8;
NET "p2l_data_i[3]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[2]" LOC = E11;
NET "p2l_data_i[2]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[1]" LOC = F12;
NET "p2l_data_i[1]" IOSTANDARD = "SSTL18_I";
NET "p2l_data_i[0]" LOC = E13;
NET "p2l_data_i[0]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[15]" LOC = E25;
NET "l2p_data_o[15]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[14]" LOC = G21;
NET "l2p_data_o[14]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[13]" LOC = D25;
NET "l2p_data_o[13]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[12]" LOC = B25;
NET "l2p_data_o[12]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[11]" LOC = E23;
NET "l2p_data_o[11]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[10]" LOC = G22;
NET "l2p_data_o[10]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[9]" LOC = G20;
NET "l2p_data_o[9]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[8]" LOC = E19;
NET "l2p_data_o[8]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[7]" LOC = C24;
NET "l2p_data_o[7]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[6]" LOC = F24;
NET "l2p_data_o[6]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[5]" LOC = F22;
NET "l2p_data_o[5]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[4]" LOC = F23;
NET "l2p_data_o[4]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[3]" LOC = G19;
NET "l2p_data_o[3]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[2]" LOC = G18;
NET "l2p_data_o[2]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[1]" LOC = F18;
NET "l2p_data_o[1]" IOSTANDARD = "SSTL18_I";
NET "l2p_data_o[0]" LOC = E17;
NET "l2p_data_o[0]" IOSTANDARD = "SSTL18_I";
#----------------------------------------
# FMC slot
#----------------------------------------
NET "ext_trigger_p_i" LOC = AJ17; # la17_cc_p
NET "ext_trigger_p_i" IOSTANDARD = "LVDS_25";
NET "ext_trigger_n_i" LOC = AK17; # la17_cc_n
NET "ext_trigger_n_i" IOSTANDARD = "LVDS_25";
NET "adc_dco_p_i" LOC = AF16; # la00_cc_p
NET "adc_dco_p_i" IOSTANDARD = "LVDS_25";
NET "adc_dco_n_i" LOC = AG16; # la00_cc_n
NET "adc_dco_n_i" IOSTANDARD = "LVDS_25";
NET "adc_fr_p_i" LOC = AG6; # la01_p
NET "adc_fr_p_i" IOSTANDARD = "LVDS_25";
NET "adc_fr_n_i" LOC = AH6; # la01_n
NET "adc_fr_n_i" IOSTANDARD = "LVDS_25";
NET "adc_outa_p_i[0]" LOC = AD12; # la14_p
NET "adc_outa_p_i[0]" IOSTANDARD = "LVDS_25";
NET "adc_outa_n_i[0]" LOC = AE12; # la14_n
NET "adc_outa_n_i[0]" IOSTANDARD = "LVDS_25";
NET "adc_outb_p_i[0]" LOC = AC15; # la15_p
NET "adc_outb_p_i[0]" IOSTANDARD = "LVDS_25";
NET "adc_outb_n_i[0]" LOC = AD15; # la15_n
NET "adc_outb_n_i[0]" IOSTANDARD = "LVDS_25";
NET "adc_outa_p_i[1]" LOC = AE15; # la16_p
NET "adc_outa_p_i[1]" IOSTANDARD = "LVDS_25";
NET "adc_outa_n_i[1]" LOC = AF15; # la16_n
NET "adc_outa_n_i[1]" IOSTANDARD = "LVDS_25";
NET "adc_outb_p_i[1]" LOC = AE13; # la13_p
NET "adc_outb_p_i[1]" IOSTANDARD = "LVDS_25";
NET "adc_outb_n_i[1]" LOC = AF13; # la13_n
NET "adc_outb_n_i[1]" IOSTANDARD = "LVDS_25";
NET "adc_outa_p_i[2]" LOC = AD10; # la10_p
NET "adc_outa_p_i[2]" IOSTANDARD = "LVDS_25";
NET "adc_outa_n_i[2]" LOC = AE10; # la10_n
NET "adc_outa_n_i[2]" IOSTANDARD = "LVDS_25";
NET "adc_outb_p_i[2]" LOC = AB12; # la09_p
NET "adc_outb_p_i[2]" IOSTANDARD = "LVDS_25";
NET "adc_outb_n_i[2]" LOC = AC12; # la09_n
NET "adc_outb_n_i[2]" IOSTANDARD = "LVDS_25";
NET "adc_outa_p_i[3]" LOC = AE9; # la07_p
NET "adc_outa_p_i[3]" IOSTANDARD = "LVDS_25";
NET "adc_outa_n_i[3]" LOC = AF9; # la07_n
NET "adc_outa_n_i[3]" IOSTANDARD = "LVDS_25";
NET "adc_outb_p_i[3]" LOC = AF7; # la05_p
NET "adc_outb_p_i[3]" IOSTANDARD = "LVDS_25";
NET "adc_outb_n_i[3]" LOC = AG7; # la05_n
NET "adc_outb_n_i[3]" IOSTANDARD = "LVDS_25";
NET "spi_din_i" LOC = AC19; # la25_p
NET "spi_din_i" IOSTANDARD = "LVCMOS25";
NET "spi_dout_o" LOC = AF23; # la31_n
NET "spi_dout_o" IOSTANDARD = "LVCMOS25";
NET "spi_sck_o" LOC = AE23; # la31_p
NET "spi_sck_o" IOSTANDARD = "LVCMOS25";
NET "spi_cs_adc_n_o" LOC = AB21; # la30_p
NET "spi_cs_adc_n_o" IOSTANDARD = "LVCMOS25";
NET "spi_cs_dac1_n_o" LOC = AA22; # la32_p
NET "spi_cs_dac1_n_o" IOSTANDARD = "LVCMOS25";
NET "spi_cs_dac2_n_o" LOC = AC22; # la32_n
NET "spi_cs_dac2_n_o" IOSTANDARD = "LVCMOS25";
NET "spi_cs_dac3_n_o" LOC = AE24; # la33_p
NET "spi_cs_dac3_n_o" IOSTANDARD = "LVCMOS25";
NET "spi_cs_dac4_n_o" LOC = AF24; # la33_n
NET "spi_cs_dac4_n_o" IOSTANDARD = "LVCMOS25";
NET "gpio_dac_clr_n_o" LOC = AC21; # la30_n
NET "gpio_dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "gpio_led_power_o" LOC = AA21; # la28_n
NET "gpio_led_power_o" IOSTANDARD = "LVCMOS25";
NET "gpio_led_trigger_o" LOC = Y21; # la28_p
NET "gpio_led_trigger_o" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch1_o[0]" LOC = AB20; # la26_p
NET "gpio_ssr_ch1_o[0]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch1_o[1]" LOC = AC20; # la26_n
NET "gpio_ssr_ch1_o[1]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch1_o[2]" LOC = AG25; # la27_n
NET "gpio_ssr_ch1_o[2]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch1_o[3]" LOC = AD19; # la25_n
NET "gpio_ssr_ch1_o[3]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch1_o[4]" LOC = AE21; # la24_p
NET "gpio_ssr_ch1_o[4]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch1_o[5]" LOC = AF21; # la24_n
NET "gpio_ssr_ch1_o[5]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch1_o[6]" LOC = AD22; # la29_p
NET "gpio_ssr_ch1_o[6]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch2_o[0]" LOC = AA19; # la20_p
NET "gpio_ssr_ch2_o[0]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch2_o[1]" LOC = AE18; # la19_n
NET "gpio_ssr_ch2_o[1]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch2_o[2]" LOC = W20; # la22_p
NET "gpio_ssr_ch2_o[2]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch2_o[3]" LOC = Y20; # la22_n
NET "gpio_ssr_ch2_o[3]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch2_o[4]" LOC = AE19; # la21_p
NET "gpio_ssr_ch2_o[4]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch2_o[5]" LOC = AF25; # la27_p
NET "gpio_ssr_ch2_o[5]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch2_o[6]" LOC = AF19; # la21_n
NET "gpio_ssr_ch2_o[6]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch3_o[0]" LOC = AG8; # la08_p
NET "gpio_ssr_ch3_o[0]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch3_o[1]" LOC = AH8; # la08_n
NET "gpio_ssr_ch3_o[1]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch3_o[2]" LOC = AE11; # la12_p
NET "gpio_ssr_ch3_o[2]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch3_o[3]" LOC = AF11; # la12_n
NET "gpio_ssr_ch3_o[3]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch3_o[4]" LOC = AC11; # la11_p
NET "gpio_ssr_ch3_o[4]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch3_o[5]" LOC = AD11; # la11_n
NET "gpio_ssr_ch3_o[5]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch3_o[6]" LOC = AB19; # la20_n
NET "gpio_ssr_ch3_o[6]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch4_o[0]" LOC = AD8; # la02_p
NET "gpio_ssr_ch4_o[0]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch4_o[1]" LOC = AE8; # la02_n
NET "gpio_ssr_ch4_o[1]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch4_o[2]" LOC = AH7; # la03_p
NET "gpio_ssr_ch4_o[2]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch4_o[3]" LOC = AK7; # la03_n
NET "gpio_ssr_ch4_o[3]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch4_o[4]" LOC = AB10; # la04_p
NET "gpio_ssr_ch4_o[4]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch4_o[5]" LOC = AA11; # la06_p
NET "gpio_ssr_ch4_o[5]" IOSTANDARD = "LVCMOS25";
NET "gpio_ssr_ch4_o[6]" LOC = AB9; # la04_n
NET "gpio_ssr_ch4_o[6]" IOSTANDARD = "LVCMOS25";
NET "gpio_si570_oe_o" LOC = AB11; # la06_n
NET "gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
NET "si570_scl_b" LOC = W19; # la18_p
NET "si570_scl_b" IOSTANDARD = "LVCMOS25";
NET "si570_sda_b" LOC = Y19; # la18_n
NET "si570_sda_b" IOSTANDARD = "LVCMOS25";
NET "mezz_one_wire_b" LOC = AE22; # la29_n
NET "mezz_one_wire_b" IOSTANDARD = "LVCMOS25";
NET "prsnt_m2c_n_i" LOC = AK15; # prsnt_m2c_l
NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "sys_scl_b" LOC = R27; # scl
NET "sys_scl_b" IOSTANDARD = "LVCMOS33";
NET "sys_sda_b" LOC = R30; # sda
NET "sys_sda_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# FMC slot (unused pins)
#----------------------------------------
#NET "" LOC = AD18; # la19_p
#NET "" IOSTANDARD = "LVCMOS25";
#NET "" LOC = AD20; # la23_p
#NET "" IOSTANDARD = "LVCMOS25";
#NET "" LOC = AE20; # la23_n
#NET "" IOSTANDARD = "LVCMOS25";
#NET "pg_c2m" LOC = AC14;
#NET "pg_c2m" IOSTANDARD = "LVCMOS25";
#NET "tck_to_fmc" LOC = AD28;
#NET "tck_to_fmc" IOSTANDARD = "LVCMOS25";
#NET "tdi_to_fmc" LOC = AC29;
#NET "tdi_to_fmc" IOSTANDARD = "LVCMOS25";
#NET "tms_to_fmc" LOC = AD30;
#NET "tms_to_fmc" IOSTANDARD = "LVCMOS25";
#NET "trst_to_fmc" LOC = AC27;
#NET "trst_to_fmc" IOSTANDARD = "LVCMOS25";
#NET "tdo_from_fmc" LOC = AC28;
#NET "tdo_from_fmc" IOSTANDARD = "LVCMOS25";
#NET "clk1_m2c_p" LOC = AH16;
#NET "clk1_m2c_p" IOSTANDARD = "LVCMOS25";
#NET "clk1_m2c_n" LOC = AK16;
#NET "clk1_m2c_n" IOSTANDARD = "LVCMOS25";
#NET "clk0_m2c_p" LOC = AC16;
#NET "clk0_m2c_p" IOSTANDARD = "LVCMOS25";
#NET "clk0_m2c_n" LOC = AD16;
#NET "clk0_m2c_n" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# SI57x interface
#----------------------------------------
#NET "si57x_clk_n" LOC = W30;
#NET "si57x_clk_n" IOSTANDARD = "LVDS_33";
#NET "si57x_clk_p" LOC = W29;
#NET "si57x_clk_p" IOSTANDARD = "LVDS_33";
#NET "si57x_oe" LOC = P30;
#NET "si57x_oe" IOSTANDARD = "LVCMOS33";
#NET "si57x_scl" LOC = P28;
#NET "si57x_scl" IOSTANDARD = "LVCMOS33";
#NET "si57x_sda" LOC = P27;
#NET "si57x_sda" IOSTANDARD = "LVCMOS33";
#NET "si57x_tune" LOC = P26;
#NET "si57x_tune" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Carrier front panel LEDs
#----------------------------------------
NET "led_green_o" LOC = AE30;
NET "led_green_o" IOSTANDARD = "LVCMOS33";
NET "led_red_o" LOC = AE29;
NET "led_red_o" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
NET "pcb_ver_i[3]" LOC = P1;
NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS33";
NET "pcb_ver_i[2]" LOC = N1;
NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS33";
NET "pcb_ver_i[1]" LOC = N3;
NET "pcb_ver_i[1]" IOSTANDARD = "LVCMOS33";
NET "pcb_ver_i[0]" LOC = P2;
NET "pcb_ver_i[0]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# DDR3 interface
#----------------------------------------
NET "ddr3_zio_b" LOC = N24;
NET "ddr3_zio_b" IOSTANDARD = "SSTL15_II";
NET "ddr3_rzq_b" LOC = G25;
NET "ddr3_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr3_we_n_o" LOC = E26;
NET "ddr3_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr3_udqs_p_b" LOC = K28;
NET "ddr3_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr3_udqs_n_b" LOC = K30;
NET "ddr3_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr3_udm_o" LOC = J27;
NET "ddr3_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr3_reset_n_o" LOC = C26;
NET "ddr3_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr3_ras_n_o" LOC = K26;
NET "ddr3_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr3_odt_o" LOC = E30;
NET "ddr3_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr3_ldqs_p_b" LOC = J29;
NET "ddr3_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr3_ldqs_n_b" LOC = J30;
NET "ddr3_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr3_ldm_o" LOC = J28;
NET "ddr3_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr3_cke_o" LOC = B29;
NET "ddr3_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr3_ck_p_o" LOC = E27;
NET "ddr3_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr3_ck_n_o" LOC = E28;
NET "ddr3_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr3_cas_n_o" LOC = K27;
NET "ddr3_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[15]" LOC = M30;
NET "ddr3_dq_b[15]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[14]" LOC = M28;
NET "ddr3_dq_b[14]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[13]" LOC = M27;
NET "ddr3_dq_b[13]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[12]" LOC = M26;
NET "ddr3_dq_b[12]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[11]" LOC = L30;
NET "ddr3_dq_b[11]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[10]" LOC = L29;
NET "ddr3_dq_b[10]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[9]" LOC = L28;
NET "ddr3_dq_b[9]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[8]" LOC = L27;
NET "ddr3_dq_b[8]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[7]" LOC = F30;
NET "ddr3_dq_b[7]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[6]" LOC = F28;
NET "ddr3_dq_b[6]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[5]" LOC = G28;
NET "ddr3_dq_b[5]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[4]" LOC = G27;
NET "ddr3_dq_b[4]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[3]" LOC = G30;
NET "ddr3_dq_b[3]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[2]" LOC = G29;
NET "ddr3_dq_b[2]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[1]" LOC = H30;
NET "ddr3_dq_b[1]" IOSTANDARD = "SSTL15_II";
NET "ddr3_dq_b[0]" LOC = H28;
NET "ddr3_dq_b[0]" IOSTANDARD = "SSTL15_II";
NET "ddr3_ba_o[2]" LOC = D26;
NET "ddr3_ba_o[2]" IOSTANDARD = "SSTL15_II";
NET "ddr3_ba_o[1]" LOC = C27;
NET "ddr3_ba_o[1]" IOSTANDARD = "SSTL15_II";
NET "ddr3_ba_o[0]" LOC = D27;
NET "ddr3_ba_o[0]" IOSTANDARD = "SSTL15_II";
#NET "ddr3_a_o[14]" LOC = A29;
#NET "ddr3_a_o[14]" IOSTANDARD = "SSTL15_II";
NET "ddr3_a_o[13]" LOC = A28;
NET "ddr3_a_o[13]" IOSTANDARD = "SSTL15_II";
NET "ddr3_a_o[12]" LOC = B30;
NET "ddr3_a_o[12]" IOSTANDARD = "SSTL15_II";
NET "ddr3_a_o[11]" LOC = A26;
NET "ddr3_a_o[11]" IOSTANDARD = "SSTL15_II";
NET "ddr3_a_o[10]" LOC = F26;
NET "ddr3_a_o[10]" IOSTANDARD = "SSTL15_II";
NET "ddr3_a_o[9]" LOC = A27;
NET "ddr3_a_o[9]" IOSTANDARD = "SSTL15_II";
NET "ddr3_a_o[8]" LOC = B27;
NET "ddr3_a_o[8]" IOSTANDARD = "SSTL15_II";
NET "ddr3_a_o[7]" LOC = C29;
NET "ddr3_a_o[7]" IOSTANDARD = "SSTL15_II";
NET "ddr3_a_o[6]" LOC = H27;
NET "ddr3_a_o[6]" IOSTANDARD = "SSTL15_II";
NET "ddr3_a_o[5]" LOC = H26;
NET "ddr3_a_o[5]" IOSTANDARD = "SSTL15_II";
NET "ddr3_a_o[4]" LOC = F27;
NET "ddr3_a_o[4]" IOSTANDARD = "SSTL15_II";
NET "ddr3_a_o[3]" LOC = E29;
NET "ddr3_a_o[3]" IOSTANDARD = "SSTL15_II";
NET "ddr3_a_o[2]" LOC = C30;
NET "ddr3_a_o[2]" IOSTANDARD = "SSTL15_II";
NET "ddr3_a_o[1]" LOC = D30;
NET "ddr3_a_o[1]" IOSTANDARD = "SSTL15_II";
NET "ddr3_a_o[0]" LOC = D28;
NET "ddr3_a_o[0]" IOSTANDARD = "SSTL15_II";
#----------------------------------------
# UART
#----------------------------------------
#NET "uart_rxd" LOC = V30;
#NET "uart_rxd" IOSTANDARD = "LVCMOS33";
#NET "uart_txd" LOC = V26;
#NET "uart_txd" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Buttons and LEDs
#----------------------------------------
NET "aux_leds_o[3]" LOC = T2;
NET "aux_leds_o[3]" IOSTANDARD = "LVCMOS33";
NET "aux_leds_o[2]" LOC = U1;
NET "aux_leds_o[2]" IOSTANDARD = "LVCMOS33";
NET "aux_leds_o[1]" LOC = V1;
NET "aux_leds_o[1]" IOSTANDARD = "LVCMOS33";
NET "aux_leds_o[0]" LOC = U3;
NET "aux_leds_o[0]" IOSTANDARD = "LVCMOS33";
NET "aux_buttons_i[1]" LOC = R1;
NET "aux_buttons_i[1]" IOSTANDARD = "LVCMOS33";
NET "aux_buttons_i[0]" LOC = T1;
NET "aux_buttons_i[0]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# PXI
#----------------------------------------
#NET "pxie_clk100_p" LOC = V4;
#NET "pxie_clk100_p" IOSTANDARD = "LVDS_33";
#NET "pxie_clk100_n" LOC = V3;
#NET "pxie_clk100_n" IOSTANDARD = "LVDS_33";
#NET "pxie_sync100_p" LOC = W5;
#NET "pxie_sync100_p" IOSTANDARD = "LVDS_33";
#NET "pxie_sync100_n" LOC = W4;
#NET "pxie_sync100_n" IOSTANDARD = "LVDS_33";
#NET "pxie_dstarc_p" LOC = J3;
#NET "pxie_dstarc_p" IOSTANDARD = "LVDS_33";
#NET "pxie_dstarc_n" LOC = J1;
#NET "pxie_dstarc_n" IOSTANDARD = "LVDS_33";
#NET "pxie_dstarb_p" LOC = B2;
#NET "pxie_dstarb_p" IOSTANDARD = "LVDS_33";
#NET "pxie_dstarb_n" LOC = A2;
#NET "pxie_dstarb_n" IOSTANDARD = "LVDS_33";
#NET "pxie_dstara_p" LOC = H2;
#NET "pxie_dstara_p" IOSTANDARD = "LVDS_33";
#NET "pxie_dstara_n" LOC = H1;
#NET "pxie_dstara_n" IOSTANDARD = "LVDS_33";
#NET "trig7" LOC = AA1;
#NET "trig7" IOSTANDARD = "LVCMOS33";
#NET "trig6" LOC = K4;
#NET "trig6" IOSTANDARD = "LVCMOS33";
#NET "trig5" LOC = K3;
#NET "trig5" IOSTANDARD = "LVCMOS33";
#NET "trig4" LOC = H3;
#NET "trig4" IOSTANDARD = "LVCMOS33";
#NET "trig3" LOC = F2;
#NET "trig3" IOSTANDARD = "LVCMOS33";
#NET "trig2" LOC = H4;
#NET "trig2" IOSTANDARD = "LVCMOS33";
#NET "trig1" LOC = G1;
#NET "trig1" IOSTANDARD = "LVCMOS33";
#NET "trig0" LOC = F4;
#NET "trig0" IOSTANDARD = "LVCMOS33";
#NET "star" LOC = D1;
#NET "star" IOSTANDARD = "LVCMOS33";
#NET "lbr6" LOC = H6;
#NET "lbr6" IOSTANDARD = "LVCMOS33";
#NET "lbl6" LOC = E1;
#NET "lbl6" IOSTANDARD = "LVCMOS33";
#NET "ga4" LOC = M3;
#NET "ga4" IOSTANDARD = "LVCMOS33";
#NET "ga3" LOC = L5;
#NET "ga3" IOSTANDARD = "LVCMOS33";
#NET "ga2" LOC = L7;
#NET "ga2" IOSTANDARD = "LVCMOS33";
#NET "ga1" LOC = F1;
#NET "ga1" IOSTANDARD = "LVCMOS33";
#NET "ga0" LOC = L3;
#NET "ga0" IOSTANDARD = "LVCMOS33";
#NET "clk10" LOC = AA3;
#NET "clk10" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Unused FPGA pins
#----------------------------------------
#NET "fpga_tms" LOC = K25;
#NET "fpga_tdo" LOC = H25;
#NET "fpga_tdi" LOC = J24;
#NET "fpga_tck" LOC = H23;
#NET "gbtclk0_m2c_p" LOC = AJ13;
#NET "gbtclk0_m2c_n" LOC = AK13;
#NET "dp0_m2c_p" LOC = AG10;
#NET "dp0_m2c_n" LOC = AH10;
#NET "dp0_c2m_p" LOC = AJ9;
#NET "dp0_c2m_n" LOC = AK9;
#NET "r_267_p" LOC = AG18;
#NET "r_267_n" LOC = AH18;
#NET "r_245_p" LOC = AG14;
#NET "r_245_n" LOC = AH14;
#===============================================================================
# IOBs
#===============================================================================
INST "cmp_gn4124_core/l2p_rdy_t" IOB=FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t*" IOB=FALSE;
INST "cmp_fmc_spi/Wrapped_SPI/shift/s_out" IOB=FALSE;
INST "cmp_fmc_spi/Wrapped_SPI/clgen/clk_out" IOB=FALSE;
#===============================================================================
# Terminations
#===============================================================================
# DDR3
NET "ddr3_dq_b[*]" IN_TERM = NONE;
NET "ddr3_ldqs_p_b" IN_TERM = NONE;
NET "ddr3_ldqs_n_b" IN_TERM = NONE;
NET "ddr3_udqs_p_b" IN_TERM = NONE;
NET "ddr3_udqs_n_b" IN_TERM = NONE;
#===============================================================================
# Clock constraints
#===============================================================================
# GN4124
NET "lclk_p_i" TNM_NET = "l_clkp_grp";
TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 5 ns HIGH 50%;
NET "p2l_clk_p_i" TNM_NET = "p2l_clkp_grp";
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 5 ns HIGH 50%;
NET "p2l_clk_n_i" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 5 ns HIGH 50%;
# System clock
NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i_grp";
TIMESPEC TS_clk20_vcxo_i = PERIOD "clk20_vcxo_i_grp" 50 ns HIGH 50%;
# DDR3
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5" 3.0 ns HIGH 50 %;
# ADC
NET "adc_dco_n_i" TNM_NET = adc_dco_n_i;
TIMESPEC TS_adc_dco_n_i = PERIOD "adc_dco_n_i" 2 ns HIGH 50%;
#===============================================================================
# False Path
#===============================================================================
# GN4124
NET "gn4124_fpga_rst_i" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
# DDR3
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_pll_lock" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
\ No newline at end of file
hdl/spexi/syn/Makefile 0 → 100644
View file @ 09563ffb
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := spexi_fmc_adc_100Ms.xise
ISE_CRAP := *.b spexi_top_fmc_adc_100Ms_summary.html *.tcl spexi_top_fmc_adc_100Ms.bld spexi_top_fmc_adc_100Ms.cmd_log *.drc spexi_top_fmc_adc_100Ms.lso *.ncd spexi_top_fmc_adc_100Ms.ngc spexi_top_fmc_adc_100Ms.ngd spexi_top_fmc_adc_100Ms.ngr spexi_top_fmc_adc_100Ms.pad spexi_top_fmc_adc_100Ms.par spexi_top_fmc_adc_100Ms.pcf spexi_top_fmc_adc_100Ms.prj spexi_top_fmc_adc_100Ms.ptwx spexi_top_fmc_adc_100Ms.stx spexi_top_fmc_adc_100Ms.syr spexi_top_fmc_adc_100Ms.twr spexi_top_fmc_adc_100Ms.twx spexi_top_fmc_adc_100Ms.gise spexi_top_fmc_adc_100Ms.unroutes spexi_top_fmc_adc_100Ms.ut spexi_top_fmc_adc_100Ms.xpi spexi_top_fmc_adc_100Ms.xst spexi_top_fmc_adc_100Ms_bitgen.xwbt spexi_top_fmc_adc_100Ms_envsettings.html spexi_top_fmc_adc_100Ms_guide.ncd spexi_top_fmc_adc_100Ms_map.map spexi_top_fmc_adc_100Ms_map.mrp spexi_top_fmc_adc_100Ms_map.ncd spexi_top_fmc_adc_100Ms_map.ngm spexi_top_fmc_adc_100Ms_map.xrpt spexi_top_fmc_adc_100Ms_ngdbuild.xrpt spexi_top_fmc_adc_100Ms_pad.csv spexi_top_fmc_adc_100Ms_pad.txt spexi_top_fmc_adc_100Ms_par.xrpt spexi_top_fmc_adc_100Ms_summary.xml spexi_top_fmc_adc_100Ms_usage.xml spexi_top_fmc_adc_100Ms_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
hdl/spexi/syn/Manifest.py 0 → 100644
View file @ 09563ffb
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "spexi_top_fmc_adc_100Ms"
syn_project = "spexi_fmc_adc_100Ms.xise"
files = ["../spexi_v0_1.ucf",
"../../ip_cores/adc_sync_fifo.ngc",
"../../ip_cores/multishot_dpram.ngc",
"../../ip_cores/wb_ddr_fifo.ngc",
"../../ip_cores/adc_serdes.vhd",
"../../ip_cores/monostable/monostable_rtl.vhd",
"../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd",
"../../ip_cores/utils/utils_pkg.vhd"]
modules = { "local" : ["../rtl",
"../../adc/rtl",
"../../ip_cores/timetag_core/rtl"],
"git" : ["git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::spec_bank3_64b_32b",
"git://ohwr.org/hdl-core-lib/gn4124-core.git::master"]}
fetchto="../../ip_cores"
hdl/spexi/wb_gen/Makefile 0 → 100644
View file @ 09563ffb
WBGEN2=~/projects/wbgen2/wbgen2
RTL=../rtl/
carrier_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -D $@.htm -C $@.h $@.wb
utc_core_regs:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -D $@.htm -C $@.h $@.wb
irq_controller_regs:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -D $@.htm -C $@.h $@.wb
hdl/spexi/wb_gen/carrier_csr.h 0 → 100644
View file @ 09563ffb
/*
Register definitions for slave core: Carrier control and status registers
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : Wed Nov 23 09:30:44 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CARRIER_CSR_WB
#define __WBGEN2_REGDEFS_CARRIER_CSR_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Carrier type and PCB version */
/* definitions for field: PCB revision in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_PCB_REV_MASK WBGEN2_GEN_MASK(0, 4)
#define CARRIER_CSR_CARRIER_PCB_REV_SHIFT 0
#define CARRIER_CSR_CARRIER_PCB_REV_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define CARRIER_CSR_CARRIER_PCB_REV_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for field: Reserved register in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_RESERVED_MASK WBGEN2_GEN_MASK(4, 12)
#define CARRIER_CSR_CARRIER_RESERVED_SHIFT 4
#define CARRIER_CSR_CARRIER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 12)
#define CARRIER_CSR_CARRIER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 12)
/* definitions for field: Carrier type in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_TYPE_MASK WBGEN2_GEN_MASK(16, 16)
#define CARRIER_CSR_CARRIER_TYPE_SHIFT 16
#define CARRIER_CSR_CARRIER_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define CARRIER_CSR_CARRIER_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Bitstream type */
/* definitions for register: Bitstream date */
/* definitions for register: Status */
/* definitions for field: FMC presence in reg: Status */
#define CARRIER_CSR_STAT_FMC_PRES WBGEN2_GEN_MASK(0, 1)
/* definitions for field: GN4142 core P2L PLL status in reg: Status */
#define CARRIER_CSR_STAT_P2L_PLL_LCK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: System clock PLL status in reg: Status */
#define CARRIER_CSR_STAT_SYS_PLL_LCK WBGEN2_GEN_MASK(2, 1)
/* definitions for field: DDR3 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR3_CAL_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Reserved in reg: Status */
#define CARRIER_CSR_STAT_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define CARRIER_CSR_STAT_RESERVED_SHIFT 4
#define CARRIER_CSR_STAT_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define CARRIER_CSR_STAT_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Control */
/* definitions for field: Green LED in reg: Control */
#define CARRIER_CSR_CTRL_LED_GREEN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Red LED in reg: Control */
#define CARRIER_CSR_CTRL_LED_RED WBGEN2_GEN_MASK(1, 1)
/* definitions for field: DAC clear in reg: Control */
#define CARRIER_CSR_CTRL_DAC_CLR_N WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Reserved in reg: Control */
#define CARRIER_CSR_CTRL_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define CARRIER_CSR_CTRL_RESERVED_SHIFT 3
#define CARRIER_CSR_CTRL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define CARRIER_CSR_CTRL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)
PACKED struct CARRIER_CSR_WB {
/* [0x0]: REG Carrier type and PCB version */
uint32_t CARRIER;
/* [0x4]: REG Bitstream type */
uint32_t BITSTREAM_TYPE;
/* [0x8]: REG Bitstream date */
uint32_t BITSTREAM_DATE;
/* [0xc]: REG Status */
uint32_t STAT;
/* [0x10]: REG Control */
uint32_t CTRL;
};
#endif
hdl/spexi/wb_gen/carrier_csr.htm 0 → 100644
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<BODY>
<h1 class="heading">carrier_csr</h1>
<h3>Carrier control and status registers</h3>
<p>Wishbone slave for control and status registers related to the FMC carrier</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Carrier type and PCB version</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Bitstream type</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Bitstream date</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Status</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Control</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#CARRIER">Carrier type and PCB version</a>
</td>
<td class="td_code">
carrier_csr_carrier
</td>
<td class="td_code">
CARRIER
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#BITSTREAM_TYPE">Bitstream type</a>
</td>
<td class="td_code">
carrier_csr_bitstream_type
</td>
<td class="td_code">
BITSTREAM_TYPE
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#BITSTREAM_DATE">Bitstream date</a>
</td>
<td class="td_code">
carrier_csr_bitstream_date
</td>
<td class="td_code">
BITSTREAM_DATE
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#STAT">Status</a>
</td>
<td class="td_code">
carrier_csr_stat
</td>
<td class="td_code">
STAT
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x4
</td>
<td >
REG
</td>
<td >
<A href="#CTRL">Control</a>
</td>
<td class="td_code">
carrier_csr_ctrl
</td>
<td class="td_code">
CTRL
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Carrier type and PCB version:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_clk_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_carrier_pcb_rev_i[3:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_addr_i[2:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_carrier_reserved_i[11:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_data_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_carrier_type_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_data_o[31:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Bitstream type:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_bitstream_type_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Bitstream date:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_bitstream_date_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Status:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_stat_fmc_pres_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_stat_p2l_pll_lck_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_stat_sys_pll_lck_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_stat_ddr3_cal_done_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_stat_reserved_i[27:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Control:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_ctrl_led_green_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_ctrl_led_red_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_ctrl_dac_clr_n_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
carrier_csr_ctrl_reserved_o[28:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="CARRIER"></a>
<h3><a name="sect_3_1">3.1. Carrier type and PCB version</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
carrier_csr_carrier
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CARRIER
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TYPE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TYPE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[11:4]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=4 class="td_field">
RESERVED[3:0]
</td>
<td style="border: solid 1px black;" colspan=4 class="td_field">
PCB_REV[3:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
PCB_REV
</b>[<i>read-only</i>]: PCB revision
<br>Binary coded PCB layout revision.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved register
<br>Ignore on read, write with 0's.
<li><b>
TYPE
</b>[<i>read-only</i>]: Carrier type
<br>Carrier type identifier
</ul>
<a name="BITSTREAM_TYPE"></a>
<h3><a name="sect_3_2">3.2. Bitstream type</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
carrier_csr_bitstream_type
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
BITSTREAM_TYPE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_TYPE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_TYPE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_TYPE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_TYPE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
BITSTREAM_TYPE
</b>[<i>read-only</i>]: Bitstream type
<br>Bitstream (firmware) type, unsigned 32-bit number.
</ul>
<a name="BITSTREAM_DATE"></a>
<h3><a name="sect_3_3">3.3. Bitstream date</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
carrier_csr_bitstream_date
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
BITSTREAM_DATE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_DATE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_DATE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_DATE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BITSTREAM_DATE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
BITSTREAM_DATE
</b>[<i>read-only</i>]: Bitstream date
<br>Bitstream generation date, unsigned 32-bit UTC time.
</ul>
<a name="STAT"></a>
<h3><a name="sect_3_4">3.4. Status</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
carrier_csr_stat
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
STAT
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[27:20]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[19:12]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[11:4]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=4 class="td_field">
RESERVED[3:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DDR3_CAL_DONE
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SYS_PLL_LCK
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
P2L_PLL_LCK
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_PRES
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
FMC_PRES
</b>[<i>read-only</i>]: FMC presence
<br>0: FMC slot is populated<br>1: FMC slot is not populated.
<li><b>
P2L_PLL_LCK
</b>[<i>read-only</i>]: GN4142 core P2L PLL status
<br>0: not locked<br>1: locked.
<li><b>
SYS_PLL_LCK
</b>[<i>read-only</i>]: System clock PLL status
<br>0: not locked<br>1: locked.
<li><b>
DDR3_CAL_DONE
</b>[<i>read-only</i>]: DDR3 calibration status
<br>0: not done<br>1: done.
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's.
</ul>
<a name="CTRL"></a>
<h3><a name="sect_3_5">3.5. Control</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
carrier_csr_ctrl
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CTRL
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x10
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[28:21]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[20:13]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[12:5]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=5 class="td_field">
RESERVED[4:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DAC_CLR_N
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
LED_RED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
LED_GREEN
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
LED_GREEN
</b>[<i>read/write</i>]: Green LED
<br>Front panel green LED control
<li><b>
LED_RED
</b>[<i>read/write</i>]: Red LED
<br>Front panel red LED control
<li><b>
DAC_CLR_N
</b>[<i>read/write</i>]: DAC clear
<br>Active low clear signal for VCXO DACs
<li><b>
RESERVED
</b>[<i>read/write</i>]: Reserved
<br>Ignore on read, write with 0's
</ul>
</BODY>
</HTML>
hdl/spexi/wb_gen/carrier_csr.wb 0 → 100644
View file @ 09563ffb
peripheral {
name = "Carrier control and status registers";
description = "Wishbone slave for control and status registers related to the FMC carrier";
hdl_entity = "carrier_csr";
prefix = "carrier_csr";
reg {
name = "Carrier type and PCB version";
prefix = "carrier";
field {
name = "PCB revision";
description = "Binary coded PCB layout revision.";
prefix = "pcb_rev";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved register";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 12;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Carrier type";
description = "Carrier type identifier";
prefix = "type";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Bitstream type";
prefix = "bitstream_type";
field {
name = "Bitstream type";
description = "Bitstream (firmware) type, unsigned 32-bit number.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Bitstream date";
prefix = "bitstream_date";
field {
name = "Bitstream date";
description = "Bitstream generation date, unsigned 32-bit UTC time.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Status";
prefix = "stat";
field {
name = "FMC presence";
description = "0: FMC slot is populated\n1: FMC slot is not populated.";
prefix = "fmc_pres";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "GN4142 core P2L PLL status";
description = "0: not locked\n1: locked.";
prefix = "p2l_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "System clock PLL status";
description = "0: not locked\n1: locked.";
prefix = "sys_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "DDR3 calibration status";
description = "0: not done\n1: done.";
prefix = "ddr3_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Control";
prefix = "ctrl";
field {
name = "Green LED";
description = "Front panel green LED control";
prefix = "led_green";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Red LED";
description = "Front panel red LED control";
prefix = "led_red";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "DAC clear";
description = "Active low clear signal for VCXO DACs";
prefix = "dac_clr_n";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 29;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- ram {
-- name = "Release tag";
-- description = "256-byte ASCII area for text generated by versionning tool";
-- prefix = "rel_tag";
-- size = 64;
-- width = 32;
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
-- };
};
hdl/spexi/wb_gen/irq_controller_regs.h 0 → 100644
View file @ 09563ffb
/*
Register definitions for slave core: IRQ controller registers
* File : irq_controller_regs.h
* Author : auto-generated by wbgen2 from irq_controller_regs.wb
* Created : Wed Jan 18 09:43:55 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_IRQ_CONTROLLER_REGS_WB
#define __WBGEN2_REGDEFS_IRQ_CONTROLLER_REGS_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Multiple interrupt register */
/* definitions for register: Interrupt sources register */
/* definitions for register: Interrupt enable mask register */
PACKED struct IRQ_CTRL_WB {
/* [0x0]: REG Multiple interrupt register */
uint32_t MULTI_IRQ;
/* [0x4]: REG Interrupt sources register */
uint32_t SRC;
/* [0x8]: REG Interrupt enable mask register */
uint32_t EN_MASK;
};
#endif
hdl/spexi/wb_gen/irq_controller_regs.htm 0 → 100644
View file @ 09563ffb
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<HEAD>
<TITLE>irq_controller_regs</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
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th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
</STYLE>
</HEAD>
<BODY>
<h1 class="heading">irq_controller_regs</h1>
<h3>IRQ controller registers</h3>
<p>Wishbone slave for registers related to IRQ controller</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Multiple interrupt register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Interrupt sources register </a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Interrupt enable mask register</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#MULTI_IRQ">Multiple interrupt register</a>
</td>
<td class="td_code">
irq_ctrl_multi_irq
</td>
<td class="td_code">
MULTI_IRQ
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#SRC">Interrupt sources register </a>
</td>
<td class="td_code">
irq_ctrl_src
</td>
<td class="td_code">
SRC
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#EN_MASK">Interrupt enable mask register</a>
</td>
<td class="td_code">
irq_ctrl_en_mask
</td>
<td class="td_code">
EN_MASK
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Multiple interrupt register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_clk_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_ctrl_multi_irq_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_addr_i[1:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_ctrl_multi_irq_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_data_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_ctrl_multi_irq_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_data_o[31:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Interrupt sources register :</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_ctrl_src_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_ctrl_src_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_ctrl_src_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Interrupt enable mask register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
irq_ctrl_en_mask_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="MULTI_IRQ"></a>
<h3><a name="sect_3_1">3.1. Multiple interrupt register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
irq_ctrl_multi_irq
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
MULTI_IRQ
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<p>
Multiple interrupts occurs before irq source is read.<br>Write '1' to clear a bit.<br><br>Bit 0: DMA done.<br>Bit 1: DMA error.<br>Bit 2: Trigger.<br>Bit 3: Acquisition end.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
MULTI_IRQ[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
MULTI_IRQ[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
MULTI_IRQ[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
MULTI_IRQ[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
MULTI_IRQ
</b>[<i>read/write</i>]: Multiple interrupt
</ul>
<a name="SRC"></a>
<h3><a name="sect_3_2">3.2. Interrupt sources register </a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
irq_ctrl_src
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
SRC
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<p>
Indicates the interrupt source.<br>Write '1' to clear a bit.<br><br>Bit 0: DMA done.<br>Bit 1: DMA error.<br>Bit 2: Trigger.<br>Bit 3: Acquisition end.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SRC[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SRC[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SRC[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SRC[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
SRC
</b>[<i>read/write</i>]: Interrupt sources
</ul>
<a name="EN_MASK"></a>
<h3><a name="sect_3_3">3.3. Interrupt enable mask register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
irq_ctrl_en_mask
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
EN_MASK
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<p>
Bit mask to independently enable interrupt sources.<br><br>Bit 0: DMA done.<br>Bit 1: DMA error.<br>Bit 2: Trigger.<br>Bit 3: Acquisition end.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
EN_MASK[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
EN_MASK[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
EN_MASK[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
EN_MASK[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
EN_MASK
</b>[<i>read/write</i>]: Interrupt enable mask
</ul>
</BODY>
</HTML>
hdl/spexi/wb_gen/irq_controller_regs.wb 0 → 100644
View file @ 09563ffb
peripheral {
name = "IRQ controller registers";
description = "Wishbone slave for registers related to IRQ controller";
hdl_entity = "irq_controller_regs";
prefix = "irq_ctrl";
reg {
name = "Multiple interrupt register";
description = "Multiple interrupts occurs before irq source is read.\nWrite '1' to clear a bit.\n\nBit 0: DMA done.\nBit 1: DMA error.\nBit 2: Trigger.\nBit 3: Acquisition end.";
prefix = "multi_irq";
field {
name = "Multiple interrupt";
type = SLV;
size = 32;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Interrupt sources register ";
description = "Indicates the interrupt source.\nWrite '1' to clear a bit.\n\nBit 0: DMA done.\nBit 1: DMA error.\nBit 2: Trigger.\nBit 3: Acquisition end.";
prefix = "src";
field {
name = "Interrupt sources";
type = SLV;
load = LOAD_EXT;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Interrupt enable mask register";
description = "Bit mask to independently enable interrupt sources.\n\nBit 0: DMA done.\nBit 1: DMA error.\nBit 2: Trigger.\nBit 3: Acquisition end.";
prefix = "en_mask";
field {
name = "Interrupt enable mask";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
hdl/spexi/wb_gen/utc_core_regs.h 0 → 100644
View file @ 09563ffb
/*
Register definitions for slave core: UTC core registers
* File : utc_core_regs.h
* Author : auto-generated by wbgen2 from utc_core_regs.wb
* Created : Tue Nov 22 10:20:36 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE utc_core_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_UTC_CORE_REGS_WB
#define __WBGEN2_REGDEFS_UTC_CORE_REGS_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: UTC seconds register */
/* definitions for register: UTC coarse time register, system clock ticks (125MHz) */
/* definitions for register: Trigger time-tag metadata register */
/* definitions for register: Trigger time-tag UTC seconds register */
/* definitions for register: Trigger time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Trigger time-tag fine time register, always 0 (used for time-tag format compatibility) */
/* definitions for register: Acquisition start time-tag metadata register */
/* definitions for register: Acquisition start time-tag UTC seconds register */
/* definitions for register: Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility) */
/* definitions for register: Acquisition stop time-tag metadata register */
/* definitions for register: Acquisition stop time-tag UTC seconds register */
/* definitions for register: Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility) */
/* definitions for register: Acquisition end time-tag metadata register */
/* definitions for register: Acquisition end time-tag UTC seconds register */
/* definitions for register: Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility) */
PACKED struct UTC_CORE_WB {
/* [0x0]: REG UTC seconds register */
uint32_t SECONDS;
/* [0x4]: REG UTC coarse time register, system clock ticks (125MHz) */
uint32_t COARSE;
/* [0x8]: REG Trigger time-tag metadata register */
uint32_t TRIG_TAG_META;
/* [0xc]: REG Trigger time-tag UTC seconds register */
uint32_t TRIG_TAG_SECONDS;
/* [0x10]: REG Trigger time-tag coarse time (system clock ticks 125MHz) register */
uint32_t TRIG_TAG_COARSE;
/* [0x14]: REG Trigger time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t TRIG_TAG_FINE;
/* [0x18]: REG Acquisition start time-tag metadata register */
uint32_t ACQ_START_TAG_META;
/* [0x1c]: REG Acquisition start time-tag UTC seconds register */
uint32_t ACQ_START_TAG_SECONDS;
/* [0x20]: REG Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_START_TAG_COARSE;
/* [0x24]: REG Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t ACQ_START_TAG_FINE;
/* [0x28]: REG Acquisition stop time-tag metadata register */
uint32_t ACQ_STOP_TAG_META;
/* [0x2c]: REG Acquisition stop time-tag UTC seconds register */
uint32_t ACQ_STOP_TAG_SECONDS;
/* [0x30]: REG Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_STOP_TAG_COARSE;
/* [0x34]: REG Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t ACQ_STOP_TAG_FINE;
/* [0x38]: REG Acquisition end time-tag metadata register */
uint32_t ACQ_END_TAG_META;
/* [0x3c]: REG Acquisition end time-tag UTC seconds register */
uint32_t ACQ_END_TAG_SECONDS;
/* [0x40]: REG Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_END_TAG_COARSE;
/* [0x44]: REG Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility) */
uint32_t ACQ_END_TAG_FINE;
};
#endif
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<h1 class="heading">utc_core_regs</h1>
<h3>UTC core registers</h3>
<p>Wishbone slave for registers related to UTC core</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">UTC seconds register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">UTC coarse time register, system clock ticks (125MHz)</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Trigger time-tag metadata register</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Trigger time-tag UTC seconds register</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Trigger time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Acquisition start time-tag metadata register</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Acquisition start time-tag UTC seconds register</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Acquisition start time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">Acquisition stop time-tag metadata register</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">Acquisition stop time-tag UTC seconds register</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">Acquisition end time-tag metadata register</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">Acquisition end time-tag UTC seconds register</a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">Acquisition end time-tag coarse time (system clock ticks 125MHz) register</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility)</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#SECONDS">UTC seconds register</a>
</td>
<td class="td_code">
utc_core_seconds
</td>
<td class="td_code">
SECONDS
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#COARSE">UTC coarse time register, system clock ticks (125MHz)</a>
</td>
<td class="td_code">
utc_core_coarse
</td>
<td class="td_code">
COARSE
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#TRIG_TAG_META">Trigger time-tag metadata register</a>
</td>
<td class="td_code">
utc_core_trig_tag_meta
</td>
<td class="td_code">
TRIG_TAG_META
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#TRIG_TAG_SECONDS">Trigger time-tag UTC seconds register</a>
</td>
<td class="td_code">
utc_core_trig_tag_seconds
</td>
<td class="td_code">
TRIG_TAG_SECONDS
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x4
</td>
<td >
REG
</td>
<td >
<A href="#TRIG_TAG_COARSE">Trigger time-tag coarse time (system clock ticks 125MHz) register</a>
</td>
<td class="td_code">
utc_core_trig_tag_coarse
</td>
<td class="td_code">
TRIG_TAG_COARSE
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x5
</td>
<td >
REG
</td>
<td >
<A href="#TRIG_TAG_FINE">Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)</a>
</td>
<td class="td_code">
utc_core_trig_tag_fine
</td>
<td class="td_code">
TRIG_TAG_FINE
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x6
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_START_TAG_META">Acquisition start time-tag metadata register</a>
</td>
<td class="td_code">
utc_core_acq_start_tag_meta
</td>
<td class="td_code">
ACQ_START_TAG_META
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x7
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_START_TAG_SECONDS">Acquisition start time-tag UTC seconds register</a>
</td>
<td class="td_code">
utc_core_acq_start_tag_seconds
</td>
<td class="td_code">
ACQ_START_TAG_SECONDS
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x8
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_START_TAG_COARSE">Acquisition start time-tag coarse time (system clock ticks 125MHz) register</a>
</td>
<td class="td_code">
utc_core_acq_start_tag_coarse
</td>
<td class="td_code">
ACQ_START_TAG_COARSE
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x9
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_START_TAG_FINE">Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)</a>
</td>
<td class="td_code">
utc_core_acq_start_tag_fine
</td>
<td class="td_code">
ACQ_START_TAG_FINE
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0xa
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_STOP_TAG_META">Acquisition stop time-tag metadata register</a>
</td>
<td class="td_code">
utc_core_acq_stop_tag_meta
</td>
<td class="td_code">
ACQ_STOP_TAG_META
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0xb
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_STOP_TAG_SECONDS">Acquisition stop time-tag UTC seconds register</a>
</td>
<td class="td_code">
utc_core_acq_stop_tag_seconds
</td>
<td class="td_code">
ACQ_STOP_TAG_SECONDS
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0xc
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_STOP_TAG_COARSE">Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a>
</td>
<td class="td_code">
utc_core_acq_stop_tag_coarse
</td>
<td class="td_code">
ACQ_STOP_TAG_COARSE
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0xd
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_STOP_TAG_FINE">Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)</a>
</td>
<td class="td_code">
utc_core_acq_stop_tag_fine
</td>
<td class="td_code">
ACQ_STOP_TAG_FINE
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0xe
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_END_TAG_META">Acquisition end time-tag metadata register</a>
</td>
<td class="td_code">
utc_core_acq_end_tag_meta
</td>
<td class="td_code">
ACQ_END_TAG_META
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0xf
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_END_TAG_SECONDS">Acquisition end time-tag UTC seconds register</a>
</td>
<td class="td_code">
utc_core_acq_end_tag_seconds
</td>
<td class="td_code">
ACQ_END_TAG_SECONDS
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x10
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_END_TAG_COARSE">Acquisition end time-tag coarse time (system clock ticks 125MHz) register</a>
</td>
<td class="td_code">
utc_core_acq_end_tag_coarse
</td>
<td class="td_code">
ACQ_END_TAG_COARSE
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x11
</td>
<td >
REG
</td>
<td >
<A href="#ACQ_END_TAG_FINE">Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility)</a>
</td>
<td class="td_code">
utc_core_acq_end_tag_fine
</td>
<td class="td_code">
ACQ_END_TAG_FINE
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>UTC seconds register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_clk_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_seconds_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_addr_i[4:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_seconds_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_data_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_seconds_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_data_o[31:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>UTC coarse time register, system clock ticks (125MHz):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_coarse_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_coarse_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_coarse_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Trigger time-tag metadata register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_trig_tag_meta_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Trigger time-tag UTC seconds register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_trig_tag_seconds_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Trigger time-tag coarse time (system clock ticks 125MHz) register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_trig_tag_coarse_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Trigger time-tag fine time register, always 0 (used for time-tag format compatibility):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_trig_tag_fine_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition start time-tag metadata register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_start_tag_meta_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition start time-tag UTC seconds register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_start_tag_seconds_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition start time-tag coarse time (system clock ticks 125MHz) register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_start_tag_coarse_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_start_tag_fine_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition stop time-tag metadata register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_stop_tag_meta_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition stop time-tag UTC seconds register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_stop_tag_seconds_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition stop time-tag coarse time (system clock ticks 125MHz) register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_stop_tag_coarse_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_stop_tag_fine_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition end time-tag metadata register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_end_tag_meta_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition end time-tag UTC seconds register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_end_tag_seconds_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition end time-tag coarse time (system clock ticks 125MHz) register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_end_tag_coarse_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility):</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
utc_core_acq_end_tag_fine_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="SECONDS"></a>
<h3><a name="sect_3_1">3.1. UTC seconds register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_seconds
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
SECONDS
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<p>
UTC seconds counter. Incremented everytime the UTC coarse counter overflows.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SECONDS[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
SECONDS
</b>[<i>read/write</i>]: UTC seconds
</ul>
<a name="COARSE"></a>
<h3><a name="sect_3_2">3.2. UTC coarse time register, system clock ticks (125MHz)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_coarse
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
COARSE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<p>
UTC coarse time counter clocked by 125MHz system clock.<br>Counts from 0 to 125000000.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
COARSE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
COARSE
</b>[<i>read/write</i>]: UTC coarse time
</ul>
<a name="TRIG_TAG_META"></a>
<h3><a name="sect_3_3">3.3. Trigger time-tag metadata register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_trig_tag_meta
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_TAG_META
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_META[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_META[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_META[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_META[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
TRIG_TAG_META
</b>[<i>read-only</i>]: Trigger time-tag metadata
<br>Holds time-tag metadata of the last trigger event
</ul>
<a name="TRIG_TAG_SECONDS"></a>
<h3><a name="sect_3_4">3.4. Trigger time-tag UTC seconds register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_trig_tag_seconds
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_TAG_SECONDS
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_SECONDS[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_SECONDS[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_SECONDS[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_SECONDS[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
TRIG_TAG_SECONDS
</b>[<i>read-only</i>]: Trigger time-tag UTC seconds
<br>Holds time-tag UTC seconds of the last trigger event
</ul>
<a name="TRIG_TAG_COARSE"></a>
<h3><a name="sect_3_5">3.5. Trigger time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_trig_tag_coarse
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_TAG_COARSE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x10
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_COARSE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_COARSE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_COARSE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_COARSE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
TRIG_TAG_COARSE
</b>[<i>read-only</i>]: Trigger time-tag coarse time
<br>Holds time-tag coarse time of the last trigger event
</ul>
<a name="TRIG_TAG_FINE"></a>
<h3><a name="sect_3_6">3.6. Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_trig_tag_fine
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x5
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TRIG_TAG_FINE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x14
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_FINE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_FINE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_FINE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TRIG_TAG_FINE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
TRIG_TAG_FINE
</b>[<i>read-only</i>]: Trigger time-tag fine time
<br>Holds time-tag fine time of the last trigger event
</ul>
<a name="ACQ_START_TAG_META"></a>
<h3><a name="sect_3_7">3.7. Acquisition start time-tag metadata register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_start_tag_meta
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x6
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_START_TAG_META
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x18
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_META[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_META[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_META[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_META[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_START_TAG_META
</b>[<i>read-only</i>]: Acquisition start time-tag metadata
<br>Holds time-tag metadata of the last acquisition start event
</ul>
<a name="ACQ_START_TAG_SECONDS"></a>
<h3><a name="sect_3_8">3.8. Acquisition start time-tag UTC seconds register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_start_tag_seconds
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x7
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_START_TAG_SECONDS
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x1c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_SECONDS[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_SECONDS[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_SECONDS[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_SECONDS[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_START_TAG_SECONDS
</b>[<i>read-only</i>]: Acquisition start time-tag UTC seconds
<br>Holds time-tag UTC seconds of the last acquisition start event
</ul>
<a name="ACQ_START_TAG_COARSE"></a>
<h3><a name="sect_3_9">3.9. Acquisition start time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_start_tag_coarse
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_START_TAG_COARSE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x20
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_COARSE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_COARSE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_COARSE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_COARSE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_START_TAG_COARSE
</b>[<i>read-only</i>]: Acquisition start time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition start event
</ul>
<a name="ACQ_START_TAG_FINE"></a>
<h3><a name="sect_3_10">3.10. Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_start_tag_fine
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x9
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_START_TAG_FINE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x24
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_FINE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_FINE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_FINE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_START_TAG_FINE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_START_TAG_FINE
</b>[<i>read-only</i>]: Acquisition start time-tag fine time
<br>Holds time-tag fine time of the last acquisition start event
</ul>
<a name="ACQ_STOP_TAG_META"></a>
<h3><a name="sect_3_11">3.11. Acquisition stop time-tag metadata register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_stop_tag_meta
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0xa
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_STOP_TAG_META
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x28
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_META[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_META[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_META[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_META[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_STOP_TAG_META
</b>[<i>read-only</i>]: Acquisition stop time-tag metadata
<br>Holds time-tag metadata of the last acquisition stop event
</ul>
<a name="ACQ_STOP_TAG_SECONDS"></a>
<h3><a name="sect_3_12">3.12. Acquisition stop time-tag UTC seconds register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_stop_tag_seconds
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0xb
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_STOP_TAG_SECONDS
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x2c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_SECONDS[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_SECONDS[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_SECONDS[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_SECONDS[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_STOP_TAG_SECONDS
</b>[<i>read-only</i>]: Acquisition stop time-tag UTC seconds
<br>Holds time-tag UTC seconds of the last acquisition stop event
</ul>
<a name="ACQ_STOP_TAG_COARSE"></a>
<h3><a name="sect_3_13">3.13. Acquisition stop time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_stop_tag_coarse
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_STOP_TAG_COARSE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x30
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_COARSE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_COARSE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_COARSE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_COARSE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_STOP_TAG_COARSE
</b>[<i>read-only</i>]: Acquisition stop time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition stop event
</ul>
<a name="ACQ_STOP_TAG_FINE"></a>
<h3><a name="sect_3_14">3.14. Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_stop_tag_fine
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0xd
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_STOP_TAG_FINE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x34
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_FINE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_FINE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_FINE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_STOP_TAG_FINE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_STOP_TAG_FINE
</b>[<i>read-only</i>]: Acquisition stop time-tag fine time
<br>Holds time-tag fine time of the last acquisition stop event
</ul>
<a name="ACQ_END_TAG_META"></a>
<h3><a name="sect_3_15">3.15. Acquisition end time-tag metadata register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_end_tag_meta
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0xe
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_END_TAG_META
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x38
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_META[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_META[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_META[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_META[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_END_TAG_META
</b>[<i>read-only</i>]: Acquisition end time-tag metadata
<br>Holds time-tag metadata of the last acquisition end event
</ul>
<a name="ACQ_END_TAG_SECONDS"></a>
<h3><a name="sect_3_16">3.16. Acquisition end time-tag UTC seconds register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_end_tag_seconds
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0xf
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_END_TAG_SECONDS
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x3c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_SECONDS[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_SECONDS[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_SECONDS[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_SECONDS[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_END_TAG_SECONDS
</b>[<i>read-only</i>]: Acquisition end time-tag UTC seconds
<br>Holds time-tag UTC seconds of the last acquisition end event
</ul>
<a name="ACQ_END_TAG_COARSE"></a>
<h3><a name="sect_3_17">3.17. Acquisition end time-tag coarse time (system clock ticks 125MHz) register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_end_tag_coarse
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x10
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_END_TAG_COARSE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x40
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_COARSE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_COARSE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_COARSE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_COARSE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_END_TAG_COARSE
</b>[<i>read-only</i>]: Acquisition end time-tag coarse time
<br>Holds time-tag coarse time of the last acquisition end event
</ul>
<a name="ACQ_END_TAG_FINE"></a>
<h3><a name="sect_3_18">3.18. Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility)</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
utc_core_acq_end_tag_fine
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x11
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ACQ_END_TAG_FINE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x44
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_FINE[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_FINE[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_FINE[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ACQ_END_TAG_FINE[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ACQ_END_TAG_FINE
</b>[<i>read-only</i>]: Acquisition end time-tag fine time
<br>Holds time-tag fine time of the last acquisition end event
</ul>
</BODY>
</HTML>
hdl/spexi/wb_gen/utc_core_regs.wb 0 → 100644
View file @ 09563ffb
peripheral {
name = "UTC core registers";
description = "Wishbone slave for registers related to UTC core";
hdl_entity = "utc_core_regs";
prefix = "utc_core";
reg {
name = "UTC seconds register";
description = "UTC seconds counter. Incremented everytime the UTC coarse counter overflows.";
prefix = "seconds";
field {
name = "UTC seconds";
type = SLV;
load = LOAD_EXT;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "UTC coarse time register, system clock ticks (125MHz)";
description = "UTC coarse time counter clocked by 125MHz system clock.\nCounts from 0 to 125000000.";
prefix = "coarse";
field {
name = "UTC coarse time";
type = SLV;
load = LOAD_EXT;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
reg {
name = "Trigger time-tag metadata register";
prefix = "trig_tag_meta";
field {
name = "Trigger time-tag metadata";
description = "Holds time-tag metadata of the last trigger event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger time-tag UTC seconds register";
prefix = "trig_tag_seconds";
field {
name = "Trigger time-tag UTC seconds";
description = "Holds time-tag UTC seconds of the last trigger event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger time-tag coarse time (system clock ticks 125MHz) register";
prefix = "trig_tag_coarse";
field {
name = "Trigger time-tag coarse time";
description = "Holds time-tag coarse time of the last trigger event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Trigger time-tag fine time register, always 0 (used for time-tag format compatibility)";
prefix = "trig_tag_fine";
field {
name = "Trigger time-tag fine time";
description = "Holds time-tag fine time of the last trigger event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag metadata register";
prefix = "acq_start_tag_meta";
field {
name = "Acquisition start time-tag metadata";
description = "Holds time-tag metadata of the last acquisition start event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag UTC seconds register";
prefix = "acq_start_tag_seconds";
field {
name = "Acquisition start time-tag UTC seconds";
description = "Holds time-tag UTC seconds of the last acquisition start event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_start_tag_coarse";
field {
name = "Acquisition start time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition start event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition start time-tag fine time register, always 0 (used for time-tag format compatibility)";
prefix = "acq_start_tag_fine";
field {
name = "Acquisition start time-tag fine time";
description = "Holds time-tag fine time of the last acquisition start event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag metadata register";
prefix = "acq_stop_tag_meta";
field {
name = "Acquisition stop time-tag metadata";
description = "Holds time-tag metadata of the last acquisition stop event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag UTC seconds register";
prefix = "acq_stop_tag_seconds";
field {
name = "Acquisition stop time-tag UTC seconds";
description = "Holds time-tag UTC seconds of the last acquisition stop event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_stop_tag_coarse";
field {
name = "Acquisition stop time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition stop event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition stop time-tag fine time register, always 0 (used for time-tag format compatibility)";
prefix = "acq_stop_tag_fine";
field {
name = "Acquisition stop time-tag fine time";
description = "Holds time-tag fine time of the last acquisition stop event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag metadata register";
prefix = "acq_end_tag_meta";
field {
name = "Acquisition end time-tag metadata";
description = "Holds time-tag metadata of the last acquisition end event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag UTC seconds register";
prefix = "acq_end_tag_seconds";
field {
name = "Acquisition end time-tag UTC seconds";
description = "Holds time-tag UTC seconds of the last acquisition end event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag coarse time (system clock ticks 125MHz) register";
prefix = "acq_end_tag_coarse";
field {
name = "Acquisition end time-tag coarse time";
description = "Holds time-tag coarse time of the last acquisition end event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility)";
prefix = "acq_end_tag_fine";
field {
name = "Acquisition end time-tag fine time";
description = "Holds time-tag fine time of the last acquisition end event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
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