hdl/rtl/fmc_adc_mezzanine.vhd · bdfff5ddb2e935bfa9042a2ec265ba4f71fc289e · Projects / FMC ADC 100M 14b 4cha · Open Hardware Repository

Blame History Permalink

hdl: recalibrate trigger delays using WR · 30b96948
Dimitris Lampridis authored Aug 14, 2020
```
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
```
30b96948

fmc_adc_mezzanine.vhd 19.3 KB