FMC ADC 100M 14b 4cha - Gateware Release 3.0 for SPEC
A binary bitstream file is available in the Documents section.
The gateware manual is available in the Documents section.
The sources are in the Git repository and tagged with "spec-fmc-adc-v3.0".
- 16 January 2014
- Increase decimation register width from 16 to 32 bits.
- Change interrupt scheme, now uses eic + vic (changes in memory map).
- Insert trigger time-tag in data, after post-trigger samples.
- Fix sdb bridge offset address.
- Prevent acquisition start if post trigger samples or number of shots is 0 (new "acq config ok" flag).
- Change trigger position register to byte-address (was sample-address).
- Add non-null meta field for timetags (mainly for test).
- Move fmc eic and timetag core to mezzanine (behind the wb bridge).
Matthieu Cattin - January 2014