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Fpga util spec

Last edited by OHWR Gitlab support Mar 27, 2019
Page history

FPGA Resource Utilization (SPEC)


FMC ADC release 4.1 (no WR), Xilinx ISE 14.7

Resource * Used * * Available * * Utilization *
Occupied Slices 2650 6822 38%
Slice LUTs 6077 27288 22%
Slice Registers 6815 54576 12%
MUXCY 1604 13644 11%
IOB 192 296 64%
RAMB16BWER 73 116 62%
RAMB8BWER 5 232 2%
BUFIO2 3 32 9%
BUFIO2FB 2 32 6%
BUFG/BUFGMUX 5 16 31%
ILOGIC2/ISERDES2 38 376 10%
IODELAY2/IODRP2/IODRP2_MCB 25 376 6%
OLOGIC2/OSERDES2 67 376 17%
BUFPLL 2 8 25%
BUFPLL_MCB 1 4 25%
DSP48A1 4 58 6%
MCB 1 2 50%
PLL_ADV 4 4 100%

note:* increase in on-chip RAM due to implementation of Feature #1266


FMC ADC release 4.0 (no WR), Xilinx ISE 14.7

Resource * Used * * Available * * Utilization *
Occupied Slices 2581 6822 37%
Slice LUTs 6033 27288 22%
Slice Registers 6813 54576 12%
MUXCY 1556 13644 11%
IOB 192 296 64%
RAMB16BWER 23 116 19%
RAMB8BWER 7 232 3%
BUFIO2 3 32 9%
BUFIO2FB 2 32 6%
BUFG/BUFGMUX 5 16 31%
ILOGIC2/ISERDES2 38 376 10%
IODELAY2/IODRP2/IODRP2_MCB 25 376 6%
OLOGIC2/OSERDES2 67 376 17%
BUFPLL 2 8 25%
BUFPLL_MCB 1 4 25%
DSP48A1 4 58 6%
MCB 1 2 50%
PLL_ADV 4 4 100%

Dimitris Lampridis - April 2016

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