Memory map for spec-fmc-adc NEXT release (-> points to proposed_master branch)

BAR0 (1MB):*

| | |* SDB version, offset (bytes) *|Description|Peripherals|Internal mapping|Status| |0x00000|SDB header|SDB specification|SDB records|Available| |0x01000|DMA Controller|DMA config. and status|Registers|Available| |0x01100|Carrier 1-wire master|Thermometer + unique ID DS18B20|Registers|Available| |0x01200|Carrier CSR|PLL, DDR status, LED control, etc...|Registers|Available| |0x01300|VIC|Vectored Interrupt Controller|Registers|Available| |0x01400|DMA EIC|Embedded Interrupt Controller for GN4124 interrupts|Registers|Available| |0x02000|Bridge SDB header|SDB specification|SDB records|Available| |0x03000|Mezzanine system management I2C master|0x50) EEPROM (FMC standard) 24AA64T|Registers|Available| |0x03100|Mezzanine SPI master|0) ADC LTC2174, 1->4) DAC (for DC offset) MAX5442|Registers|Available| |0x03200|Mezzanine I2C master|0x55) Oscillator (sampling clock) Si570|Registers|Available| |0x03300|Mezzanine ADC core CSR|ACQ state machine, input range, trigger, etc...|Registers|Available| |0x03400|Mezzanine 1-wire master|Thermometer + unique ID DS18B20|Registers|Available| |0x03500|Mezzanine EIC|Embedded Interrupt Controller for fmc-adc interrupts|Registers|Available| |0x03600|Time-tag core|Trigger, acq time-tags|Registers|Available|