Synchronization through the RF backplane
Introduction
The eRTM modules have been designed to deliver high quality clocks and
RF signals to the RF backplane to be used by AMCs and RTMs. A clock (or
carrier) signal doesn't transport information by definition, therefore
unsynchronized AMCs require a side channel to perform synchronization.
Notably, the RF backplane doesn't provide a deterministic data channel
to provide PPS and time-code information to the AMCs. The only
communication channel from eRTMs to the AMCs is through a (LVDS) SPI
connection, which requires an MCH-RTM equipped with an FPGA. Moreover,
the MCH-RTM's FPGA must re-route the data to the front MCH and then to
the AMC backplane. This solution has been discarded due to unnecessary
complexity.
Deterministic data channel for synchronization
The requirement of a deterministic data channel originates from the
problem of PPS marking.
The clocks synthesized by the eRTM modules can have a frequency as high
as 500 MHz, or 2 ns clock period. The most challenging aspect is to
correctly mark the beginning of a second (i.e. 1-PPS) accordingly to the
related rising edge of the 500 MHz clock. This task requires the use of
a high speed (i.e. rise time less than 1 ns) and deterministic data
channel (i.e. no jitter due to data processing).
Notably, the requirements for UTC/TAI synchronization are very relaxed,
once 1-PPS synchronization is done. Therefore, the time-code can be
retrieved using the same side channel used by 1-PPS or using
non-deterministic channels (e.g. NTP).
The proposed solution
The proposed solution is to modulate the clocks distributed by the RF
backplane to perform 1-PPS synchronization. The additional UTC/TAI
information can be retrieved using the same channel or using NTP
(suggested approach). Notably, the AMCs are connected to a Ethernet
network by the AMC backplane, therefore no additional cabling is
required. The UTC/TAI alignment is a one-off procedure, during cold
start-up.
The eRTM 15 clock distribution scheme use an Analog Devices clock
distribution chip, AD9520-5 (the PLL sections are switched off). The
"CLK" input is an high-frequency clock synthesized by a local PLL. The
output clocks are derived from the high-frequency using the clock
dividers inside
AD9520-5.
The picture above shows the clock distribution using AD9520-5. Notably,
this is the scheme for CLKA, CLKB use an identical scheme.
The clock distributed to the RTM attached to the AMCs (slots 4 to 12)
are divided into three clock groups. Each group share the same clock
divider and therefore the same frequency. However, a clock group can
have some outputs turned off (e.g. when an RTM is not connected to the
RF backplane).
As a clock division introduce an uncertainty, the chip has a "SYNC"
input, used to synchronize the outputs of the (selected) channel
dividers. The effect of the SYNC signal is applied only to the selected
channel dividers. A side effect of the SYNC signal is that the output
clocks have the value "0" till the SYNC signal is deasserted (plus a
deterministic additional delay). The picture below shows this
effect.
Each clock output effect of a SYNC A side effect of the SYNC line is
that the outputs
The SYNC line can be used to mark the beginning