High Performance White Rabbit Timing Receiver in MTCA.4 format

Project description

The HP WR Timing Receiver is composed by two MTCA eRTM (Rear Transition Module) modules:

• Digital board (WR node), sitting in the slot 14. The board provides a redundant uplink to the WR network (2 SFP ports) and hosts the FPGA that implements the WR stack.
• RF board, using the slot 15. This board produces the Local Oscillator/Reference RF signals using a DDS as well as two configurable digital LVPECL clocks. They are distributed to the RTM/AMC slots of a MTCA.4 crate through the MTCA.4 RF Backplane The two boards always go together (stacked in a "sandwich" form) into the neighboring backplane slots 14 and 15. Inter-board communication is done through a high speed board-to-board cable.

Block Diagram

Features

Digital Board

• Kintex-7 (XC7K70) FPGA
  • White Rabbit Core with redundant WR links
  • Fully deterministic gigabit transceiver (GTX) with no-phase-jump mode
  • Controls the RF board through the board-to-board connector
• Front panel:
  • 2 SFP cages for White Rabbit input
  • PPS input and output connectors (SMA)
  • 10 MHz input (SMA)
  • WR clock output (SMA)
  • USB serial console

RF Board

• Front panel outputs:
  • RTM clocks CLKA and CLKB (SMA)
  • 2 LO Monitor (SMA)
  • 2 REF Monitor (SMA)
• Zone-3 backplane connector:
  • 11 RTM_CLKA signals (configurable: 62.5 MHz, 100 MHz, 125 MHz, 200 MHz, 250 MHz, 500 MHz)
  • 11 RTM_CLKB signals (configurable: 62.5 MHz, 100 MHz, 125 MHz, 200 MHz, 250 MHz, 500 MHz)
  • LVPECL clock signals with double termination, unused clocks can be shut down.
  • Possibility to encode PPS and time-code information into CLKA and CLKB
  • Less than 100 fs RMS jitter (100 Hz - 5 MHz)
• LO/REF/CAL backplane connector (Radiall Coaxipack)
  • 9 LO signals, 10-250 MHz, 12 dBm
  • 9 REF signals, 10-250 MHz, 12 dBm
  • Less than 100 fs RMS jitter (100 Hz - 5 MHz)
  • RF power monitoring on all backplane RF outputs
  • Unused RF channels can be internally terminated
  • Temperature sensors on LO and REF distribution sections
• Unique IDs
  • Three EUI-48 (MAC addresses) on WR Main Board (two for Ethernet links, one for storage)
  • One EUI-48 ID for RF board (storage)
• STM32F microcontroller for MicroTCA management
  • Runs OpenMMC

Documentation

Digital Board

• EDMS schematics & layout: EDA-03849-V1-0
• Review notes

RF Board

• EDMS schematics & layout (not yet released to public): EDA-03850-V1-0
• Review notes

Read more

• MTCA 4.1 for LLRF distribution using WR: presentation describing the main design concepts
• Synchronization through RF backplane
• MTCA.4 RF Backplane
  • Note: the backplane is not an open design and needs licensing from DESY. Patent application is filed: EP142004371.
• MTCA 4 standard
• MTCA 4.1 standard (extension of MicroTCA 4 for RF and timing applications)
• Users

Contacts

Commercial producers

• none

General questions about project

• Mattia Rizzi, CERN
• Tomasz Wlostowski, CERN

Status

Files

• EDA-03849-V1_0_project.pdf
• rf_board.pdf