Synchronization through the RF backplane
Introduction
The eRTM modules have been designed to deliver high quality clocks (CLKA
and CLKB) and RF signals to the RF backplane to be used by AMCs and
uRTMs. A clock (or carrier) signal doesn't transport information by
definition, therefore unsynchronized AMCs require a side channel to
perform synchronization.
Notably, the RF backplane doesn't provide a deterministic data channel
to provide PPS and time-code information to the AMCs. The only
communication channel from eRTMs to the AMCs is through a (LVDS) SPI
connection, which requires an MCH-RTM equipped with an FPGA. Moreover,
the MCH-RTM's FPGA must re-route the data to the front MCH and then to
the AMC backplane. This solution has been discarded due to unnecessary
complexity.
Deterministic data channel for synchronization
The requirement of a deterministic data channel originates from the
problem of PPS marking.
The clocks synthesized by the eRTM modules can have a frequency as high
as 500 MHz, or 2 ns clock period. The most challenging aspect is to
correctly mark the beginning of a second (i.e. 1-PPS) accordingly to the
related rising edge of the 500 MHz clock. This task requires the use of
a high speed (i.e. rise time less than 1 ns) and deterministic data
channel (i.e. no jitter due to data processing).
Notably, the requirements for UTC/TAI synchronization are very relaxed,
once 1-PPS synchronization is done. Therefore, the time-code can be
retrieved using the same side channel used by 1-PPS or using
non-deterministic channels (e.g. NTP).
The proposed solution
The proposed solution is to modulate the clocks distributed by the RF
backplane to perform 1-PPS synchronization. The additional UTC/TAI
information can be retrieved using the same channel or using NTP
(suggested approach). Notably, the AMCs are connected to a Ethernet
network by the AMC backplane, therefore no additional cabling is
required. The UTC/TAI alignment is a one-off procedure, during cold
start-up.
The eRTM 15 clock distribution scheme use an Analog Devices clock
distribution chip, AD9520-5 (the PLL sections are switched off). The
AD9520-5's CLK input is an high-frequency clock synthesized by a local
PLL. The output clocks are derived from the high-frequency using the
clock dividers inside
AD9520-5.
The picture above shows the clock distribution using AD9520-5. Notably,
this is the scheme for CLKA, CLKB use an identical scheme.
The clock distributed to the uRTM attached to the AMCs (slots 4 to 12)
are divided into three clock groups. Each group share the same clock
divider and therefore the same clock frequency. However, a clock group
can have some outputs turned off (e.g. when an uRTM is not connected to
the RF backplane).
As a clock division introduce an uncertainty, the chip has a "SYNC"
input, used to synchronize the outputs of the (selected) channel
dividers. The effect of the SYNC signal is applied only to the selected
channel dividers. A side effect of the SYNC signal is that the output
clocks have the value "0" till the SYNC signal is deasserted (plus a
deterministic additional
delay).
The picture above shows the effect on SYNC assertion (SYNC is an active
low signal). Notably, the picture shows an uncertainty of 1 clock cycle.
From the datasheet: " There is an uncertainty of up to one cycle of the
clock at the input to the channel divider due to the asynchronous nature
of the SYNC signal with respect to the clock edges inside the AD9520-5.
The pipeline delay from the SYNC rising edge to the beginning of the
synchronized output clocking is between 14 cycles and 15 cycles of clock
at the channel divider input, plus one cycle of the channel divider
input " .
In our case, the SYNC line is controlled by the ODELAY of the Kintex-7
FPGA, which can assert the SYNC line synchronously with CLK ,
therefore there's no uncertainty. The only challenge is to deliver a
SYNC signal with a fast rise time. The SYNC input has an input typical
capacitance of 2 pF, therefore a MAX9111 having a rise time of 0.6 ns
(under 15 pF load) is fast enough. LVDS signalling is used from the FPGA
to MAX9111.
A possible approach to 1-PPS marking is to deassert SYNC 14 clock
cycles before the 1-PPS transition. Unfortunately, the 1-PPS marking
cannot be done on a per uRTM basis. As a result, each uRTM in the
affected clock group will be affected by the missing clocks. An
interlock system can be adopted if AMC hot-plug capability is necessary.
Notably, uRTMs in a different clock group would be unaffected.
AMC implementation of 1-PPS receiver
The AMC implementation is very simple. The received clock (CLKA or CLKB)
feed the input clock of a counter, counting the elapsed ns from the
1-PPS. The counter is asynchronously reset by a logic (clocked by a
local clock of AMC) which controls if CLKA (or CLKB) had missing clock
cycles.
The mandatory requirement is to not use any PLL along the CLKA/CLKB
distribution.*
h2. AMC implementation of UTC/TAI receiver
To be discussed. The proposed solution is NTP, but a modulation using SYNC is possible. The only requirement is to avoid missing clock cycles with a duration bigger than 1 us (due to the discharge of the capacitance introduced by AC coupling).