Schematics review report
Date: 15.06.2018 - 20.07.2018
Reviewers: T. Wlostowski, M. Rizzi, D. Lampridis, M. Ricci
Tom:*
General:
- Title blocks to be updated, add OHWR licenses.
Regulators:
- Add Pulldowns on power enable signals
- Change 3V7 to 3V8 and 1V4 to 1V6 to respect maximum dropout of the
LDOs.
PLL:
- Missing ground on cdcm61002 decoupling caps
- IC6 CS pin should not be grounded!
- Add CS pin connections to the FPGA for both PLLs
LED_FP:
- don't use a PMOS to drive the LEDs (too high Vgson)
Other:
- Add pulldowns for VCXO enable inputs
- Removed XADC (seems to not be used at all)
- Added net ties on PP12V and MTCA_MP3V3
- Renamed MTCA.4 backplane connectors to follow the MTCA standard
- Changed pushbuttons to smaller ones
- Changed ARM debug pinhead to IDC with key
*Dimitris:
*
- fpga_board (node_top)
- fpga_power
- extra wire at GND symbols and pin A1 on IC1M -> junctions - transceivers
- add len match directive for calibration resistor (UG476, p303) - gtx_data_splitter
- IC25, pin 5 extra wire -> junction - regulators
- LDOs have max dropout 400mV. Safer/more robust then to provide P1V5 and P3V8 instead of P1V4 and P3V7.
- T1, T3: INH/UVLO is connected through internal resistor divider to AGND. Should they (T1 and T3) also be connected to AGND ? - pll
- AD9516: safer/more robust to drive SPI CS only when you need it, instead of always 'on' - clk_external
- AD9516: safer/more robust to drive SPI CS only when you need it, instead of always 'on'
- Diodes on TR3 secondary need refdes - sfp
- J3, J4, pins 9 and 31 extra wire -> junction
- fpga_power
- rf board (rfboard_top)
- regulators
- Note says DC/DC set to 3.7, but net name says 3.6, Rset is 3.65. Also, 0.35V less than LDO max dropout 0.4V. Safer/more robust to provide 3V8 instead.
- 5V is actually 4.98V, due to R155 being 56k instead of 56k2 - RF generation
- drive SPI CS - RF distribution
- IC22, 23, 24, pin 4 extra wire -> junction
- IC26, 27, 28, is EP grounded?
- IC26, 27, 28, why noERCs? - clk_distribution
- drive 2x SPI CS
- regulators
Maxime:*
- IC5: The CLK_HELPER_VCXO come in a capa that is pushed to P3V3A before go to XIN. Is that normal ? Or It's a mistake and only CE Have to be push to P3V3A ?
- AGND / GND of LMZ31704: Do you need a single net connect between AGND
and GND or no connect between ?. I don't really understand your
comment.
Tom: there's no need for the net tie as AGND and GND are connected
inside the chip.
- GTX Differential Pair. Could you review The “Transceivers” Page ? It
is normal that for exemple “LINK0_GTX_TX_FB_P/N” goes not in BGA but
“LINK0_GTX_TX_P” goes on 2 different Pair of BGA ?
Tom: this is a bug, the pins should be connected to FB pins. Fixed in
the schematics.
- If we search “UNIV_ID_SDA” or SCL. We found that there is 2 with
the same net name but not connected together. (Page “Management” and
Page “FPGA_local_peripherals”). Should be connect all together. Or it
is right ?
Tom: these buses are separate, we could rename them to make this clear.