eRTM14 Schematics & Layout Review
Mattia's notes:
- fpga_board (node_top)
- fpga_power
- extra wire at GND symbols and pin A1 on IC1M -> junctions
- transceivers
- cannot open image from Matia's local home
- add len match directive for calibration resistor (UG476, p303)
- gtx_data_splitter
- IC25, pin 5 extra wire -> junction
- regulators
- LDOs have max dropout 400mV. Safer/more robust then to provide P1V5 and P3V8 instead of P1V4 and P3V7.
- T1, T3: INH/UVLO is connected through internal resistor divider to AGND. Should they (T1 and T3) also be connected to AGND ?
- pll
- AD9516: safer/more robust to drive SPI CS only when you need it, instead of always 'on'
- clk_external
- AD9516: safer/more robust to drive SPI CS only when you need it, instead of always 'on'
- Diodes on TR3 secondary need refdes
- sfp
- J3, J4, pins 9 and 31 extra wire -> junction