eRTM14 Schematics & Layout Review
Mattia's notes:
- fpga_power
- extra wire at GND symbols and pin A1 on IC1M -> junctions
- transceivers
- cannot open image from Matia's local home
- add len match directive for calibration resistor (UG476, p303)
- gtx_data_splitter
- IC25, pin 5 extra wire -> junction
- regulators
- LDOs have max dropout 400mV. Safer/more robust then to provide P1V5 and P3V8 instead of P1V4 and P3V7.
- T1, T3: INH/UVLO is connected through internal resistor divider to AGND. Should they (T1 and T3) also be connected to AGND ?
- pll
- AD9516: safer/more robust to drive SPI CS only when you need it, instead of always 'on'
- clk_external
- AD9516: safer/more robust to drive SPI CS only when you need it, instead of always 'on'
- Diodes on TR3 secondary need refdes
- sfp
- J3, J4, pins 9 and 31 extra wire -> junction
Orson's notes (Layout):
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L6_PWR is dedicated to MP3V3 which takes about a half of the board, perhaps it could be also used for another power net?
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L4_PWR: P2V5 has a strange shape, I suppose there were 2.5V pins in the bottom part that do not exist anymore
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Top, L8: there are several single-ended clocks (CAL_CONTROL.SHIFTCLK, REF_CONTROl.UPDATECLK, LO_CONTROL.SHIFTCLK) routed together, perhaps there could be a larger distance between them to reduce EMI
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Bottom: slightly misaligned vias (GND, X:183.4mm Y:209.2mm and X:183.4mm Y:206mm)
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Bottom: extra vias for C84?
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Bottom: extra via at X:123.575mm Y:134.2mm?
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Bottom: swapping pins 2 and 3 in IC13 would make the connections shorter