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Last edited by Grzegorz Daniluk

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Distributed IO Tier

HL-LHC_WP18

Project description

Distributed I/O Tier - is the level where electronics modules installed close to a particle accelerator in radiation-exposed or radiation-free areas controlled by the master in the Front-end tier over the fieldbus.
These are usually FPGA-based boards sampling digital and analog inputs, driving outputs and performing various safety critical operations.

diot_kit7_scaled

Modular and reusable Distributed I/O Tier hardware kit

Project information

Modules

Main Kit:

The DI/OT Main Kit provides the following modules which are essential to the DI/OT system and application-independent:

  • DI/OT 3U crate
    Backplanes and crate mechanics designs; the crate is the same for radiation-free and radiation-exposed areas

  • 1U FanTray module
    Fan Tray module for radiation-free and radiation-exposed areas. It's made of 1U enclosure hosting 3 fans and a small control module - MoniMod

  • RaToPUS
    100W AC/DC power supply for radiation tolerant DI/OT crate; an off-the-shelf power supply at higher capacity may be used outside of radiation

  • DI/OT System Board with ZU7
    A non-radiation-tolerant crate controller with Zynq Ultrascale MPSoC, White Rabbit support and Low Pin Count FMC

  • DI/OT Rad-tol System Board with Igloo2
    A radiation-tolerant crate controller with Flash-based Igloo2 FPGA

  • Communication mezzanines
    A set of FMC mezzanine boards that support different communication protocols: White Rabbit and Profinet for radiation-free areas, Powerlink and WorldFIP for the radiation-exposed ones

  • Hydra
    Hydra is a radiation-tolerant SoC designed to operate up to 500 Gy TID. It features a RISC-V CPU running at 50 MHz, 96 kB of ROM for code, 64 kB of RAM, two Ethernet NIC with low-latency L2 packet switching, SPI and watchdog. Its first use is in the implementation of a Powerlink node using a stripped-down OpenPowerlink stack.

  • Extender card for debugging
    Extender card with P1-P6 connectors to facilitate probing and debugging on System Board or Peripheral Boards plugged to the backplane.

Peripheral Boards:

Check the dedicated page for Peripheral Boards and Rear Transition Modules catalogue

DI/OT Users

  • Wire Positioning Sensors readout (CERN, BE-GM)
  • Frequency Scanning Interferometry (CERN, BE-GM / BE-CEM)
  • Temperature readout and motor drivers for SAMbuCa project (CERN BE-CEM)
  • Fast Interlock Detection System (CERN, SY-ABT)
  • FGC4 Power Converters Control (CERN, SY-EPC)
  • Warm Interlock Controller v2 (CERN, TE-MPE)
  • Coupling-Loss Induced Quench (CERN, TE-MPE)
  • Quantum Computing Control (Warsaw University of Technology)

Reliability/Dependability Studies

Documents

Presentations

2025

Radiation qualification of DI/OT modules
A. Arias Vazquez, CHARM-RADWG User Meeting 2025, 29 Jan 2025

2023

WP18: Status and plans of DI/OT and its application to FSI
G. Daniluk, M. Lipiński, HL-LHC Technical Coordination Committee, 6th Jul 2023

2022

Radiation-tolerant DI/OT platform
G. Daniluk, Radiation Working Group workshop, 12 Oct 2022, CERN

RaToPUS DC/DC Converter
P. Peronnard, Radiation Working Group workshop, 12 Oct 2022, CERN

Radiation-tolerant DI/OT platform
G. Daniluk, 12th HL-LHC Collaboration Meeting, 21 Sep 2022, Uppsala, Sweden

2021

WP18: radiation-tolerant Distributed I/O Tier platform
G.Daniluk, 11th HL-LHC Collaboration Meeting, 21 Oct 2021

Radiation-tolerant DI/OT developments (Introduction, RaToPUS, System Board, Reliability)
CERN R2E Annual Meeting, 3 Feb 2021

2020

DI/OT developments overview for CERN Cryogenics group
G.Daniluk, J.Serrano, 11 Dec 2020

DI/OT platform: development status and interfaces with CO services (video - CERN access only)
G.Daniluk, E.Gousiou, CERN Technical Meeting, 4 Jun 2020

Papers, conference posters

A novel control system architecture for quantum computing
poster conference link
P.Kulik, M.Sowiński, T.Przywózki, G.Kasprowicz, G.Daniluk, 7th European Conference on Trapped Ions, 2023

Design of a 100W Radiation-Tolerant Power-Factor-Correction Buck AC/DC Converter
paper
Lalit Patnaik, Grzegorz Daniluk, Salvatore Danzeca, PCIM Europe digital days 2020

Low-Cost Modular Platform for Custom Electronics in Radiation-Exposed and Radiation-Free Areas at CERN
paper slides
G.Daniluk, C.Gentsos, E.Gousiou, L.Patnaik, M.Rizzi, Proceedings of ICALEPCS2019, New York, USA

Plans at CERN for electronics and communication in the Distributed I/O Tier
G.Daniluk E.Gousiou, Proceedings of ICALEPCS2017, Barcelona, Spain, ISBN: 9783954501939

Contacts

Status

Date Event
2015 Start of the project at CERN as collaboration to design generic hardware platform for accelerator equipment
2017 DI/OT becomes official work package of HL-LHC project
10-01-20 Created FAQ
01-05-20 First version of crate mechanics and backplanes design finalized, awaiting the prototypes
11-09-20 Non-radiation-tolerant System Board design finalized, awaiting the prototypes
03-12-20 First prototypes of DI/OT crate and backplanes received!
31-03-21 First prototypes of Non-rad-tol System Board received
12-07-23 Ongoing design improvements for DI/OT crate v2 and System Board ZU7 v3. System Board IGL v2 prototypes validated. Ongoing CHARM irradiation qualification
Oct 2024 Received 65 Crates produced locally at CERN for first deployments
Nov 2024 Contracts signed for the production of 550 Crates

Files