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[L7] some clock lines near IC4 are missing GND return vias (like it's done for 7_PE_CLK_P/N) 3 of 3 tasks completed
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[L3] some FMC MGT lanes have 1 sharp edge in otherwise soft-edged routing 2 of 2 tasks completed
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[multiple layers] not enough stitching vias on some GND polygons 0 of 2 tasks completed
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[L1] add some more GND return vias for diff pairs crossing layers 4 of 4 tasks completed
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[General] check DDR4 rules 2 of 2 tasks completed