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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit e121d638 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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removing outdated gw/sw, it's now stored in gitlab

parent e757498e
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      gw/.gitignore deleted 100644 → 0
      View file @ e757498e
      # cache
      .Xil
      # Generated files
      output_files
      # vivado
      *.log
      *.jou
      gw/Makefile deleted 100644 → 0
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      #!/usr/bin/make
      # ##############################################################################
      # Settings
      DOCKER_NAME=gitlab-registry.cern.ch/be-cem-edl/diot/docker-util/xilinx_tools:latest
      DOCKERFILE_PATH=docker
      XILINX_TOOLS=/opt/Xilinx
      XIL_VER?=2019.2
      SETUP_XIL_ENV=source ${XILINX_TOOLS}/Vivado/${XIL_VER}/settings64.sh
      CALL_VIVADO_DEF=vivado -source build_project.tcl -mode batch -nolog -nojournal -notrace -tclargs
      docker_build:
      docker build -f ${DOCKERFILE_PATH}/Dockerfile -t ${DOCKER_NAME} ${DOCKERFILE_PATH}
      CALL_DOCKER?=docker run -w${CURDIR} \
      -v${CURDIR}:${CURDIR} \
      -v ${HOME}:${HOME} \
      -v /etc/passwd:/etc/passwd:ro \
      -v /etc/shadow:/etc/shadow:ro \
      -v /etc/group:/etc/group:ro \
      -v /tmp:/tmp \
      -v /tmp/.X11-unix:/tmp/.X11-unix \
      -v ${XILINX_TOOLS}:${XILINX_TOOLS} \
      -v /var/run/dbus:/var/run/dbus \
      -e DISPLAY=${DISPLAY} \
      -u $$(id -u):$$(id -g) \
      --privileged \
      -t ${DOCKER_NAME} /bin/bash -c
      ifdef GITLAB_CI
      CMD_DOCKER=eval
      CALL_VIVADO=${CALL_VIVADO_DEF}
      else
      CMD_DOCKER=${CALL_DOCKER}
      CALL_VIVADO=${SETUP_XIL_ENV} && ${CALL_VIVADO_DEF}
      endif
      # ##############################################################################
      # Define project list
      TARGET_LIST:=$(shell ls projects)
      TARGET_BUILD_LIST:=$(addsuffix .build, ${TARGET_LIST})
      TARGET_BD_LIST:=$(addsuffix .bd, ${TARGET_LIST})
      TARGET_CLEAN_LIST:=$(addsuffix .clean, ${TARGET_LIST})
      # ##############################################################################
      # Build Steps
      OUTPUT_PATH=output_files
      ${OUTPUT_PATH}:
      mkdir -p @
      ${TARGET_BUILD_LIST}:
      ${CMD_DOCKER} '${CALL_VIVADO} projects/$(basename $@) build ${OUTPUT_PATH}'
      ${TARGET_BD_LIST}:
      ${CMD_DOCKER} '${CALL_VIVADO} projects/$(basename $@) bd ${OUTPUT_PATH}'
      ${TARGET_CLEAN_LIST}:
      rm -rf ${OUTPUT_PATH}/$(basename $@)
      # ##############################################################################
      # Clean rule
      # ##############################################################################
      clean:
      rm -rf ${OUTPUT_PATH}
      rm -rf *.log *.jou
      gw/README.md deleted 100644 → 0
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      # Gateware
      This repository folder allows you to build the bitstream/XSA file for the DIOT system board version 1 & 2 which based on Xilinx Zynq Ultrascale+ (**xczu7cg-ffvf1517-1-e**)
      ## Requirements Linux
      - Docker:
      - [Install Docker Debian](https://docs.docker.com/engine/install/debian/)
      - [Install Docker Ubuntu](https://docs.docker.com/engine/install/ubuntu/)
      - [Install Docker CentOS](https://docs.docker.com/engine/install/centos/)
      - Vitis **v2019.2**:
      - [Download Vitis 2019.2](https://www.xilinx.com/member/forms/download/xef-vitis.html?filename=Xilinx_Vitis_2019.2_1106_2127.tar.gz)
      - [Install Vitis](https://docs.xilinx.com/v/u/2019.2-English/ug1400-vitis-embedded)
      - Install make Debian/Ubuntu:
      ```console
      sudo apt install -y make
      ```
      - Install make CentOS:
      ```console
      yum install -y make
      ```
      ## Requirements Windows
      Unfortunately Windows is not supported yet
      ## Build Container
      ```console
      make docker_build
      ```
      ## Build Design
      - Build bitstream:
      ```console
      make <project>.build
      ```
      - Build just the block design:
      ```console
      make <project>.bd
      ```
      In both cases the project options are:
      - diot_v1
      - diot_v2
      ## Maintainers
      - [Alén Arias Vázquez](mailto:alen.arias.vazquez@cern.ch)
      - [Greg Daniluk](mailto:grzegorz.daniluk@cern.ch)
      gw/build_project.tcl deleted 100644 → 0
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      ################################################################################
      #
      # Main Script to buil any project in the repository
      #
      ################################################################################
      source functions.tcl -notrace
      write_msg "INFO: Launching Vivado TCL mode" "1"
      if { $::argc == 3 } {
      set target_path [lindex $argv 0]
      set run_type [lindex $argv 1]
      set output_path [lindex $argv 2]
      } else {
      write_msg "ERROR: Bad call to tcl script build_project.tcl" "3"
      return 1
      }
      # Loading project specific config
      source ${target_path}/tcl/project_cfg.tcl -notrace
      set_param general.maxThreads ${max_threads}
      # Set the project name
      set _xil_proj_name_ ${project_name}
      source ${target_path}/tcl/create_bd.tcl -notrace
      # Create project
      create_project ${_xil_proj_name_} ${output_path}/${_xil_proj_name_} -part ${reference_part}
      # Source TCL FPGA Device
      source common-ip/fpga_device/tcl/fpga_device.tcl
      create_fpga_version "${_xil_proj_name_}" "common-ip/fpga_device/src/fpga_device.v" "${output_path}/${_xil_proj_name_}/fpga_device.v"
      add_files -norecurse common-ip/fpga_device/src/dna_reader.v
      add_files -norecurse ${output_path}/${_xil_proj_name_}/fpga_device.v
      # Set Properties from the list
      if [ info exist ::user_list(PROP_NAME) ] {
      set curr_project [ current_project ]
      set list_names [ get_list PROP_NAME ]
      set list_values [ get_list PROP_VAL ]
      set list_names_max_i [ get_list_size PROP_NAME ]
      for { set i 0 } { $i < ${list_names_max_i} } { incr i } {
      set lname [ lindex ${list_names} ${i} ]
      set lvalue [ lindex ${list_values} ${i} ]
      write_msg "INFO: Set property $lname to $lvalue" "1"
      set_property -name $lname -value $lvalue -objects $curr_project
      }
      }
      # Add VHDL
      if [ info exist ::user_list(SRC_VHDL) ] {
      set list_vhdl [ get_list SRC_VHDL ]
      set list_lib [ get_list LIB_VHDL ]
      set list_vhdl_max_i [ get_list_size SRC_VHDL ]
      for { set i 0 } { $i < ${list_vhdl_max_i} } { incr i } {
      set vhdl_src [ lindex ${list_vhdl} ${i} ]
      set vhdl_lib [ lindex ${list_lib} ${i} ]
      write_msg "INFO: Adding VHLD file ${vhdl_src}" "1"
      read_vhdl -library ${vhdl_lib} ${target_path}/src/${vhdl_src}
      }
      }
      # Add VHDL08
      if [ info exist ::user_list(SRC_VHDL08) ] {
      set list_vhdl [ get_list SRC_VHDL08 ]
      set list_lib [ get_list LIB_VHDL08 ]
      set list_vhdl_max_i [ get_list_size SRC_VHDL08 ]
      for { set i 0 } { $i < ${list_vhdl_max_i} } { incr i } {
      set vhdl_src [ lindex ${list_vhdl} ${i} ]
      set vhdl_lib [ lindex ${list_lib} ${i} ]
      write_msg "INFO: Adding VHLD 2008 file ${vhdl_src}" "1"
      read_vhdl -library ${vhdl_lib} -2008 ${target_path}/src/${vhdl_src}
      }
      }
      # Add Verilog/SystemVerilog sources
      if [ info exist ::user_list(SRC_VERILOG) ] {
      set list_ver [ get_list SRC_VERILOG ]
      set list_ver_max_i [ get_list_size SRC_VERILOG ]
      for { set i 0 } { $i < ${list_ver_max_i} } { incr i } {
      set ver_src [ lindex ${list_ver} ${i} ]
      if { [ enable_sv_compilation ${ver_src} ] == 1 } {
      write_msg "INFO: Adding SystemVerilog file ${ver_src}" "1"
      read_verilog -library ${lib_default} -sv ${target_path}/src/${ver_src}
      } else {
      write_msg "INFO: Adding Verilog file ${ver_src}" "1"
      read_verilog -library ${lib_default} ${target_path}/src/${ver_src}
      }
      }
      }
      # Add XDC Files
      if [ info exist ::user_list(CONSTRAINT) ] {
      set list_xdc [ get_list CONSTRAINT ]
      set list_names_max_i [ get_list_size CONSTRAINT ]
      for { set i 0 } { $i < ${list_names_max_i} } { incr i } {
      set file_xdc [ lindex ${list_xdc} ${i} ]
      write_msg "INFO: Adding XDC file ${file_xdc}" "1"
      read_xdc ${target_path}/constraints/${file_xdc}
      }
      }
      # Set the directory path for the new project
      set proj_dir [get_property directory [current_project]]
      # Create 'sources_1' fileset (if not found)
      if {[string equal [get_filesets -quiet sources_1] ""]} {
      create_fileset -srcset sources_1
      }
      update_ip_catalog -rebuild
      set obj [get_filesets sources_1]
      set_property -name "top" -value ${entity_top} -objects $obj
      # ##############################################################################
      # Create Block Design
      # ##############################################################################
      write_msg "INFO: Generating block design" "1"
      create_block_design "" ${_xil_proj_name_} ${target_path}
      update_compile_order -fileset sources_1
      set_property IS_ENABLED "1" [ get_files ${_xil_proj_name_}.bd ]
      set_property REGISTERED_WITH_MANAGER "1" [ get_files ${_xil_proj_name_}.bd ]
      set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [ get_files ${_xil_proj_name_}.bd ]
      # ##############################################################################
      # Launch synthesis & implementation
      # ##############################################################################
      if { [ string equal ${run_type} "build" ] } {
      # Launch Synthesis
      write_msg "INFO: Launch Synthesis" "1"
      launch_runs synth_1 -jobs ${max_threads}
      wait_on_run synth_1
      set status_synth [ get_property STATUS [ get_runs synth_1 ] ]
      if { [ string equal ${status_synth} "synth_design Complete!" ] } {
      write_msg "INFO: ${status_synth}" "1"
      } else {
      write_msg "ERROR: Synthesis run failed" "3"
      write_msg "ERROR: ${status_synth}" "3"
      exit 1
      }
      # Set Implementation Properties
      set obj [ get_runs impl_1 ]
      set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj
      # Launch Implementation & Bitstream
      write_msg "INFO: Launch Implementation & Bistream generation" "1"
      launch_runs impl_1 -to_step write_bitstream -jobs ${max_threads}
      wait_on_run impl_1
      set status_impl_1 [ get_property STATUS [ get_runs impl_1 ] ]
      if { [ string equal ${status_impl_1} "write_bitstream Complete!" ] } {
      write_msg "INFO: ${status_impl_1}" "1"
      } else {
      write_msg "ERROR: Implementation run failed" "3"
      write_msg "ERROR: ${status_impl_1}" "3"
      exit 1
      }
      # Copy Bitstream
      if { [ file exists ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.runs/impl_1/${entity_top}.bit ] } {
      write_msg "INFO: Copy Bistream" "1"
      file copy ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.runs/impl_1/${entity_top}.bit ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.bit
      write_msg "INFO: Generating XSA with bitstream ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.xsa" "1"
      write_hw_platform -force ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.xsa -fixed -include_bit
      } else {
      write_msg "ERROR: Failed Bistream Generation" "3"
      exit 1
      }
      } else {
      # Generate XSA without bistream
      write_msg "INFO: Target Hardware Platform" "1"
      generate_target {synthesis implementation} [get_files ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/${_xil_proj_name_}/${_xil_proj_name_}.bd]
      write_msg "INFO: Generating XSA file ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.xsa" "1"
      write_hw_platform -force ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.xsa -fixed
      }
      exit 0
      gw/common-ip/fpga_device/src/dna_reader.v deleted 100644 → 0
      View file @ e757498e
      //==============================================================================
      //! @file dna_reader.v
      //==============================================================================
      //------------------------------------------------------------------------------
      // --
      // CERN - DNA Reader Xilinx FPGA --
      // --
      //------------------------------------------------------------------------------
      //
      // unit name: DNA Reader Xilinx FPGA
      //
      //! @brief DNA Reader Xilinx FPGA
      //
      //! @author alen.arias.vazquez@cern.ch
      //
      //! @date 11/05/2022
      //
      //! @details
      //! PL DNA is 96bits width in the Ultrascale/Ultrascale+
      //
      //------------------------------------------------------------------------------
      module dna_reader # (
      parameter g_SIM_DNA_VALUE = 96'hAABBCCDDEEFF112233445566
      )
      (
      input clk_i,
      input rst_n_i,
      output dna_rdy_o,
      output [95:0] dna_o
      );
      //! Status
      localparam [1:0] SET = 2'b00;
      localparam [1:0] UNSET = 2'b01;
      localparam [1:0] COUNT = 2'b11;
      localparam [1:0] DONE = 2'b10;
      (* fsm_encoding = "gray" *) reg [1:0] s_state;
      //! Constants
      localparam [6:0] c_MAX_CTR = 7'd96;
      //! Signals
      reg s_read;
      reg s_shift;
      reg s_dna_rdy;
      reg [6:0] s_shift_c;
      reg [95:0] s_dna;
      wire s_data;
      //! FSM
      always @(posedge clk_i)
      begin : p_fsm
      if(! rst_n_i) begin
      s_read <= 1'b0;
      s_shift <= 1'b0;
      s_shift_c <= 'h0;
      s_dna_rdy <= 1'b0;
      s_state <= SET;
      end
      else begin
      case (s_state)
      //! State SET
      SET:
      begin
      s_shift_c <= 'h0;
      s_read <= 1'b1;
      s_shift <= 1'b1;
      s_dna_rdy <= 1'b0;
      s_state <= UNSET;
      end
      //! State UNSET
      UNSET:
      begin
      s_shift_c <= 'h0;
      s_read <= 1'b0;
      s_shift <= 1'b1;
      s_dna_rdy <= 1'b0;
      s_state <= COUNT;
      end
      //! State COUNT
      COUNT:
      begin
      s_read <= 1'b0;
      if (s_shift_c < c_MAX_CTR) begin
      s_shift_c <= s_shift_c + 'd1;
      s_shift <= 1'b1;
      s_dna_rdy <= 1'b0;
      end
      else begin
      s_shift <= 1'b0;
      s_shift_c <= 'h0;
      s_dna_rdy <= 1'b1;
      s_state <= DONE;
      end
      end
      //! State DONE
      DONE:
      begin
      s_read <= 1'b0;
      s_shift <= 1'b0;
      s_shift_c <= 'h0;
      s_dna_rdy <= 1'b1;
      s_state <= DONE;
      end
      endcase
      end
      end : p_fsm
      //! Shift Register
      always @(posedge clk_i)
      begin : p_shift
      if (! rst_n_i)
      s_dna <= 'h0;
      else begin
      if (s_shift)
      s_dna <= {s_data, s_dna[95:1]};
      end
      end : p_shift
      assign dna_rdy_o = s_dna_rdy;
      assign dna_o = s_dna;
      //! Instance Xilinx Macro
      DNA_PORTE2 # (
      .SIM_DNA_VALUE (g_SIM_DNA_VALUE)
      ) i_DNA_PORTE2 (
      .CLK (clk_i),
      .DIN ('h0),
      .READ (s_read), //! input: load DNA
      .SHIFT (s_shift), //! input: shift enable input
      .DOUT (s_data) //! output: DNA output bit
      );
      endmodule
      //------------------------------------------------------------------------------
      //! end module
      //------------------------------------------------------------------------------
      gw/common-ip/fpga_device/src/fpga_device.v deleted 100644 → 0
      View file @ e757498e
      //==============================================================================
      //! @file fpga_device.v
      //==============================================================================
      //------------------------------------------------------------------------------
      // --
      // CERN - FPGA Version Device --
      // --
      //------------------------------------------------------------------------------
      //
      // unit name: fpga_device
      //
      //! @brief FPGA Version Device
      //
      //! @author alen.arias.vazquez@cern.ch
      //
      //! @date 06/05/2022
      //
      //! @details
      //
      //! @URL: https://ohwr.org/project/fpga-dev-id/wikis
      //
      //------------------------------------------------------------------------------
      module fpga_device # (
      parameter g_VENDOR_ID = 32'h0,
      parameter g_DEVICE_ID = 32'h0,
      parameter g_VERSION = 32'h0,
      parameter g_BYTE_ORD_MARK = 32'h0,
      parameter g_SOURCE_ID = 128'h0,
      parameter g_CAP_MASK = 32'h0,
      parameter g_VENDOR_UUID = 128'h0,
      parameter g_CORE_ID = 32'h0,
      parameter g_NAME = 64'h0,
      parameter g_BUILD_DATE = 32'd0,
      parameter g_HASH = 160'h0,
      parameter g_TAG = 64'h0,
      parameter g_S_AXI_DATA_WIDTH = 32,
      parameter g_S_AXI_ADDR_WIDTH = 8,
      parameter g_SIM_DNA_VALUE = 96'hAABBCCDDEEFF112233445566
      )
      (
      // Clock && RESET
      input S_AXI_ARESETN,
      input S_AXI_ACLK,
      //! Slave Interface Write Address Ports
      input [g_S_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
      input [2:0] S_AXI_AWPROT,
      input S_AXI_AWVALID,
      output S_AXI_AWREADY,
      //! Slave Interface Write Data Ports
      input [g_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
      input [(g_S_AXI_DATA_WIDTH/8)-1:0] S_AXI_WSTRB,
      input S_AXI_WVALID,
      output S_AXI_WREADY,
      //! Slave Interface Write Response Ports
      output [1:0] S_AXI_BRESP,
      output S_AXI_BVALID,
      input S_AXI_BREADY,
      //! Slave Interface Read Address Ports
      input [g_S_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
      input [2:0] S_AXI_ARPROT,
      input S_AXI_ARVALID,
      output S_AXI_ARREADY,
      //! Slave Interface Read Data Ports
      output [g_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
      output [1:0] S_AXI_RRESP,
      output S_AXI_RVALID,
      input S_AXI_RREADY
      );
      //! Unused lines WRITE
      assign S_AXI_AWREADY = 1'b0;
      assign S_AXI_WREADY = 1'b0;
      assign S_AXI_BRESP = 2'b0;
      assign S_AXI_BVALID = 1'b0;
      //! Unused lines READ
      assign S_AXI_RRESP = 2'b00;
      //! Constants
      localparam c_ZEROS = {g_S_AXI_DATA_WIDTH{1'b0}};
      localparam c_LSB_ADDR = (g_S_AXI_DATA_WIDTH / 32) + 1;
      localparam c_ADDR_VENDOR_ID = 'h00;
      localparam c_ADDR_DEVICE_ID = 'h01;
      localparam c_ADDR_VERSION = 'h02;
      localparam c_ADDR_BYTE_ORD_MARK = 'h03;
      localparam c_ADDR_SOURCE_ID_0 = 'h04;
      localparam c_ADDR_SOURCE_ID_1 = 'h05;
      localparam c_ADDR_SOURCE_ID_2 = 'h06;
      localparam c_ADDR_SOURCE_ID_3 = 'h07;
      localparam c_ADDR_CAP_MASK = 'h08;
      localparam c_ADDR_VENDOR_UUID_0 = 'h0C;
      localparam c_ADDR_VENDOR_UUID_1 = 'h0D;
      localparam c_ADDR_VENDOR_UUID_2 = 'h0E;
      localparam c_ADDR_VENDOR_UUID_3 = 'h0F;
      localparam c_ADDR_CORE_ID = 'h10;
      localparam c_ADDR_NAME_LSB = 'h11;
      localparam c_ADDR_NAME_MSB = 'h12;
      localparam c_ADDR_BUILD_T = 'h13;
      localparam c_ADDR_HASH_0 = 'h14;
      localparam c_ADDR_HASH_1 = 'h15;
      localparam c_ADDR_HASH_2 = 'h16;
      localparam c_ADDR_HASH_3 = 'h17;
      localparam c_ADDR_HASH_4 = 'h18;
      localparam c_ADDR_DNA_0 = 'h19;
      localparam c_ADDR_DNA_1 = 'h1A;
      localparam c_ADDR_DNA_2 = 'h1B;
      localparam c_ADDR_TAG_LSB = 'h1C;
      localparam c_ADDR_TAG_MSB = 'h1D;
      //! Axi lite auxiliary regs
      reg [g_S_AXI_ADDR_WIDTH-1:0] s_araddr;
      reg s_arready;
      reg s_rvalid;
      //! User lines
      reg [g_S_AXI_DATA_WIDTH-1:0] s_RDATA;
      wire [g_S_AXI_ADDR_WIDTH-c_LSB_ADDR-1:0] s_RADDR;
      wire s_REN;
      //! DNA
      wire [95:0] s_dna;
      //--------------------------------------------------------------------------
      //! ARREADY LOGIC & ARADDR Latch
      always @(posedge S_AXI_ACLK)
      begin : p_arready
      if (! S_AXI_ARESETN) begin
      s_araddr <= 'h0;
      s_arready <= 1'b0;
      end
      else begin
      if (!s_arready && S_AXI_ARVALID) begin
      s_araddr <= S_AXI_ARADDR;
      s_arready <= 1'b1;
      end
      else begin
      s_araddr <= s_araddr;
      s_arready <= 1'b0;
      end
      end
      end : p_arready
      assign S_AXI_ARREADY = s_arready;
      //! RVALID
      always @(posedge S_AXI_ACLK)
      begin : p_rvalid
      if (! S_AXI_ARESETN)
      s_rvalid <= 1'b0;
      else begin
      if (~(s_rvalid) & s_arready & S_AXI_ARVALID)
      s_rvalid <= 1'b1;
      else if (s_rvalid & S_AXI_RREADY)
      s_rvalid <= 1'b0;
      end
      end : p_rvalid
      //! Read assignment
      assign s_RADDR = s_araddr[g_S_AXI_ADDR_WIDTH-1:c_LSB_ADDR];
      assign s_REN = ~(s_rvalid) & s_arready & S_AXI_ARVALID;
      //! Register Access
      always @(posedge S_AXI_ACLK)
      begin : p_read
      if (! S_AXI_ARESETN)
      s_RDATA <= 'h0;
      else begin
      if (s_REN) begin
      case(s_RADDR)
      c_ADDR_VENDOR_ID : s_RDATA <= g_VENDOR_ID;
      c_ADDR_DEVICE_ID : s_RDATA <= g_DEVICE_ID;
      c_ADDR_VERSION : s_RDATA <= g_VERSION;
      c_ADDR_BYTE_ORD_MARK : s_RDATA <= g_BYTE_ORD_MARK;
      c_ADDR_SOURCE_ID_0 : s_RDATA <= g_SOURCE_ID[31:0];
      c_ADDR_SOURCE_ID_1 : s_RDATA <= g_SOURCE_ID[63:32];
      c_ADDR_SOURCE_ID_2 : s_RDATA <= g_SOURCE_ID[95:64];
      c_ADDR_SOURCE_ID_3 : s_RDATA <= g_SOURCE_ID[127:96];
      c_ADDR_CAP_MASK : s_RDATA <= g_CAP_MASK;
      c_ADDR_VENDOR_UUID_0 : s_RDATA <= s_dna[31:0];
      c_ADDR_VENDOR_UUID_1 : s_RDATA <= {g_VENDOR_UUID[63:48],s_dna[47:32]};
      c_ADDR_VENDOR_UUID_2 : s_RDATA <= g_VENDOR_UUID[95:64];
      c_ADDR_VENDOR_UUID_3 : s_RDATA <= g_VENDOR_UUID[127:96];
      c_ADDR_CORE_ID : s_RDATA <= g_CORE_ID;
      c_ADDR_NAME_LSB : s_RDATA <= g_NAME[31:0];
      c_ADDR_NAME_MSB : s_RDATA <= g_NAME[63:32];
      c_ADDR_BUILD_T : s_RDATA <= g_BUILD_DATE;
      c_ADDR_HASH_0 : s_RDATA <= g_HASH[31:0];
      c_ADDR_HASH_1 : s_RDATA <= g_HASH[63:32];
      c_ADDR_HASH_2 : s_RDATA <= g_HASH[95:64];
      c_ADDR_HASH_3 : s_RDATA <= g_HASH[127:96];
      c_ADDR_HASH_4 : s_RDATA <= g_HASH[159:128];
      c_ADDR_DNA_0 : s_RDATA <= s_dna[31:0];
      c_ADDR_DNA_1 : s_RDATA <= s_dna[63:32];
      c_ADDR_DNA_2 : s_RDATA <= s_dna[95:64];
      c_ADDR_TAG_LSB : s_RDATA <= g_TAG[31:0];
      c_ADDR_TAG_MSB : s_RDATA <= g_TAG[63:32];
      default : s_RDATA <= c_ZEROS;
      endcase
      end
      end
      end : p_read
      //! Assign outputs
      assign S_AXI_RDATA = s_RDATA;
      assign S_AXI_RVALID = s_rvalid;
      //--------------------------------------------------------------------------
      dna_reader # (
      .g_SIM_DNA_VALUE (g_SIM_DNA_VALUE)
      ) i_dna_reader (
      .clk_i (S_AXI_ACLK),
      .rst_n_i (S_AXI_ARESETN),
      .dna_rdy_o (),
      .dna_o (s_dna)
      );
      endmodule
      //------------------------------------------------------------------------------
      //! end module
      //------------------------------------------------------------------------------
      gw/common-ip/fpga_device/tb/dna_reader_tb.sv deleted 100644 → 0
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      //==============================================================================
      //! @file dna_reader_tb.sv
      //==============================================================================
      //------------------------------------------------------------------------------
      // --
      // CERN - TestBench DNA Reader Xilinx FPGA --
      // --
      //------------------------------------------------------------------------------
      //
      // unit name: TestBench DNA Reader Xilinx FPGA
      //
      //! @brief TestBench DNA Reader Xilinx FPGA
      //
      //! @author alen.arias.vazquez@cern.ch
      //
      //! @date 12/05/2022
      //
      //------------------------------------------------------------------------------
      module dna_reader_tb # (
      parameter g_SIM_DNA_VALUE = 96'hAABBCCDDEEFF112233445566
      );
      //! Define time units
      timeunit 1ns;
      //! Define stimulus
      wire [95:0] s_dna;
      reg s_clk;
      reg s_rst_n;
      wire s_dna_rdy;
      dna_reader # (
      .g_SIM_DNA_VALUE (g_SIM_DNA_VALUE)
      ) i_dna_reader (
      .clk_i (s_clk),
      .rst_n_i (s_rst_n),
      .dna_rdy_o (s_dna_rdy),
      .dna_o (s_dna)
      );
      //! Initial block
      initial
      begin : p_initial
      s_rst_n = 1'b0;
      s_clk = 1'b0;
      end : p_initial
      //! Clock generator
      always
      begin : p_clock
      #5 s_clk = 1'b1;
      #5 s_clk = 1'b0;
      end : p_clock
      //! Clock generator
      always
      begin : p_rst
      #25 s_rst_n = 1'b1;
      end : p_rst
      //! Check Result
      initial
      begin : p_result
      @(posedge s_dna_rdy)
      assert (s_dna == g_SIM_DNA_VALUE) $display("Result is correct");
      else begin
      $error("Failure in simulation");
      $error("Generic value: %X", g_SIM_DNA_VALUE);
      $error("Expecter Valuer: %X", s_dna);
      end
      end : p_result
      endmodule
      //------------------------------------------------------------------------------
      //! end module
      //------------------------------------------------------------------------------
      gw/common-ip/fpga_device/tcl/fpga_device.tcl deleted 100644 → 0
      View file @ e757498e
      ################################################################################
      #
      # Author: alen.arias.vazquez@cern.ch
      # Date: 10/05/2022
      #
      ################################################################################
      # Get Git Hash
      proc get_git_hash {} {
      return [ exec git rev-parse --short=40 HEAD ]
      }
      # Get Git Tag
      proc get_git_tag {} {
      set git_tag_check [ catch { exec git describe --tags --abbrev=0 --dirty=D } msg ]
      if { $git_tag_check == 1 } {
      write_yellow "Any tag has not been defined yet in the current repository"
      return "v0.0.0"
      } else {
      return $msg
      }
      }
      # Conver Git Tag to number:
      # bits 31-24: major number
      # bits 23-16: minor number
      # bits 15-00: patch number
      proc convert_tag_to_number { tag } {
      # Highest v255.255.65535
      if { [ string range $tag 0 0 ] == "v" } {
      # Remove v
      set tag [ string range $tag 1 end ]
      if { [ string range $tag end end ] == "D" } {
      # Remove Dirty
      set tag [ string range $tag 0 end-1 ]
      }
      set list_num [ split $tag {.} ]
      if { [ llength $list_num ] == 3 } {
      set major [ format %02X [ lindex $list_num 0 ] ]
      set minor [ format %02X [ lindex $list_num 1 ] ]
      set patch [ format %04X [ lindex $list_num 2 ] ]
      return [ concat $major$minor$patch ]
      } else {
      return 0
      }
      } else {
      return 0
      }
      }
      # Convert String to Hex String
      proc convert_string_to_hex { str size } {
      while { $size > [ string length $str ] } {
      set str [ concat -$str ]
      }
      binary scan $str H* hex
      return $hex
      }
      # Generate UUID
      proc generate_uuid {} {
      set str [ info hostname ]
      binary scan $str H* hex_value
      set uuid [ format %2.2x [ clock seconds ]]
      append uuid [ string range [ format %2.2x [ clock clicks ] ] 0 3 ]
      append uuid [ string range [ format %2.2x [ clock clicks ] ] 2 5 ]
      append uuid [ string range [ format %2.2x [ clock clicks ] ] 4 7 ]
      append uuid [ string range $hex_value 0 11]
      return $uuid
      }
      proc print_uuid { hex_uuid } {
      return [ concat [ string range $hex_uuid 0 7 ]-[ string range $hex_uuid 8 11 ]-[ string range $hex_uuid 12 15 ]-[ string range $hex_uuid 16 19 ]-[ string range $hex_uuid 20 end ] ]
      }
      proc create_fpga_version { name ref target } {
      # Parameters that are Constants:
      set vendor_id "FF000000"
      set device_id "44494F5A"
      set byte_ord "FFFE0000"
      set cap_mask "AAAAAAAA"
      # IP CORE ID
      set core_id "46504741"
      # Get git parameters
      set git_hash [ get_git_hash ]
      set git_tag [ get_git_tag ]
      # Get DATE
      set build_date [ clock seconds ]
      # Cut Commit hash
      set source_id [ string range $git_hash 8 end ]
      # UUID
      set uuid [ generate_uuid ]
      # Convert string to hex
      set name_hex [ convert_string_to_hex $name 8 ]
      set git_tag_hex [ convert_string_to_hex $git_tag 8 ]
      set num_version [ convert_tag_to_number $git_tag ]
      # Open input and output file
      set r_file [open $ref r]
      set w_file [open $target w]
      # Map for replace strings
      set map {}
      lappend map "parameter g_VENDOR_ID = 32'h0," "parameter g_VENDOR_ID = 32'h$vendor_id,"
      lappend map "parameter g_DEVICE_ID = 32'h0," "parameter g_DEVICE_ID = 32'h$device_id,"
      lappend map "parameter g_VERSION = 32'h0," "parameter g_VERSION = 32'h$num_version,"
      lappend map "parameter g_BYTE_ORD_MARK = 32'h0," "parameter g_BYTE_ORD_MARK = 32'h$byte_ord,"
      lappend map "parameter g_SOURCE_ID = 128'h0," "parameter g_SOURCE_ID = 128'h$source_id,"
      lappend map "parameter g_CAP_MASK = 32'h0," "parameter g_CAP_MASK = 32'h$cap_mask,"
      lappend map "parameter g_VENDOR_UUID = 128'h0," "parameter g_VENDOR_UUID = 128'h$uuid,"
      lappend map "parameter g_CORE_ID = 32'h0," "parameter g_CORE_ID = 32'h$core_id,"
      lappend map "parameter g_NAME = 64'h0," "parameter g_NAME = 64'h$name_hex,"
      lappend map "parameter g_BUILD_DATE = 32'd0," "parameter g_BUILD_DATE = 32'd$build_date,"
      lappend map "parameter g_HASH = 160'h0," "parameter g_HASH = 160'h$git_hash,"
      lappend map "parameter g_TAG = 64'h0," "parameter g_TAG = 64'h$git_tag_hex,"
      write_green ""
      write_green "Fpga Device Generation:"
      write_green "Vendor ID: 0x$vendor_id"
      write_green "Device ID: 0x$device_id"
      write_green "Number Version: 0x$num_version"
      write_green "Byte Order Mark: 0x$byte_ord"
      write_green "Source ID: $source_id"
      write_green "Capability Mask: 0x$cap_mask"
      write_green "Vendor UUID: [ print_uuid $uuid ]"
      write_green "IP Core ID: 0x$core_id"
      write_green "Project name: $name"
      write_green "Build Date: [ clock format $build_date -format "%Y-%m-%d %H:%M:%S" ]"
      write_green "Git Hash: $git_hash"
      write_green "Git Tag: $git_tag"
      write_green ""
      # Copy files
      while { [ gets $r_file r_line ] >= 0 } {
      set w_line [ string map $map $r_line]
      puts $w_file $w_line
      }
      # Closes files
      close $r_file
      close $w_file
      }
      gw/docker/Dockerbuild.sh deleted 100644 → 0
      View file @ e757498e
      #!/bin/sh
      docker build -f Dockerfile -t vivado .
      gw/docker/Dockerfile deleted 100644 → 0
      View file @ e757498e
      FROM ubuntu:18.04
      ENV TERM xterm
      RUN dpkg --add-architecture i386
      RUN echo 'APT::Install-Recommends "0";\nAPT::Install-Suggests "0";' > /etc/apt/apt.conf.d/01norecommend
      RUN apt-get update
      ENV DEBIAN_FRONTEND=noninteractive
      RUN apt-get -y install locales
      RUN export LC_ALL=en_US.UTF-8
      RUN export LANG=en_US.UTF-8
      RUN locale-gen en_US.UTF-8
      RUN apt-get -y install bzip2 \
      libc6-i386 \
      libprotobuf-dev \
      libxtst6 \
      libxrender-dev \
      libxext6 \
      libx11-6 \
      libfontconfig1 \
      libglib2.0-0 \
      libxext6 \
      libxrender1 \
      libxtst6 \
      libgtk2.0-0 \
      build-essential \
      net-tools \
      pkg-config \
      xauth \
      xvfb \
      bash-completion \
      ssh \
      bc \
      tmux \
      x11-utils \
      dbus-x11 \
      ca-certificates \
      libswt-gtk-4-java \
      libswt-gtk-4-jni \
      gcc-multilib \
      g++-multilib \
      git \
      vim
      RUN apt-get -y install libstdc++6:i386
      RUN apt-get -y install libgtk2.0-0:i386
      RUN apt-get -y install dpkg-dev:i386
      RUN apt-get -y install libtinfo5 libncurses5
      RUN apt-get clean autoclean
      RUN apt-get autoremove -y
      RUN ln -s /usr/bin/make /usr/bin/gmake
      gw/docker/docker_run.sh deleted 100644 → 0
      View file @ e757498e
      #!/usr/bin/env sh
      XILINX_TOOLS=/opt/Xilinx
      docker run \
      -v "$HOME":"$HOME" \
      -v /etc/passwd:/etc/passwd:ro \
      -v /etc/shadow:/etc/shadow:ro \
      -v /etc/group:/etc/group:ro \
      -v ${XILINX_TOOLS}:${XILINX_TOOLS} \
      -v /tmp/.X11-unix:/tmp/.X11-unix \
      -v /tmp:/tmp \
      -e DISPLAY=$DISPLAY \
      --privileged \
      --net=host \
      -i -w "$PWD" -u $(id -u):$(id -g) -t --rm \
      vivado bash
      gw/functions.tcl deleted 100644 → 0
      View file @ e757498e
      ################################################################################
      #
      # Common functions for different projects
      #
      ################################################################################
      # Write console message in red
      proc write_red { msg } {
      puts -nonewline "\033\[1;31m"
      puts $msg
      puts -nonewline "\033\[0m"
      }
      # Write console message in green
      proc write_green { msg } {
      puts -nonewline "\033\[1;32m"
      puts $msg
      puts -nonewline "\033\[0m"
      }
      # Write console message in green
      proc write_yellow { msg } {
      puts -nonewline "\033\[1;33m"
      puts $msg
      puts -nonewline "\033\[0m"
      }
      # Write console message in green
      proc write_blue { msg } {
      puts -nonewline "\033\[1;34m"
      puts $msg
      puts -nonewline "\033\[0m"
      }
      # Write console message in different colors
      proc write_msg { msg severity } {
      switch ${severity} {
      "1" {
      write_green $msg
      }
      "2" {
      write_yellow $msg
      }
      "3" {
      write_red $msg
      }
      default {
      write_blue $msg
      }
      }
      }
      # Returns the number of CPUs for the build
      # To set the build number of threads in Vivado
      proc get_number_cpus {} {
      global tcl_platform env
      switch ${tcl_platform(platform)} {
      "windows" {
      return $env(NUMBER_OF_PROCESSORS)
      }
      "unix" {
      if {![catch {open "/proc/cpuinfo"} f]} {
      set cores [regexp -all -line {^processor\s} [read $f]]
      close $f
      if {$cores > 0} {
      return $cores
      }
      }
      }
      default {
      write_msg "Unknown System" "3"
      return 1
      }
      }
      }
      # Define Vhdl src
      proc add_vhdl_src { lib src} {
      lappend ::user_list(SRC_VHDL) ${src}
      lappend ::user_list(LIB_VHDL) ${lib}
      }
      # Define Vhdl08 src
      proc add_vhdl08_src { lib src} {
      lappend ::user_list(SRC_VHDL08) ${src}
      lappend ::user_list(LIB_VHDL08) ${lib}
      }
      # Define Verilog/SystemVerilog src
      proc add_source { src } {
      lappend ::user_list(SRC_VERILOG) ${src}
      }
      # Define Constraint files
      proc add_constraint { file } {
      lappend ::user_list(CONSTRAINT) ${file}
      }
      # Define array property
      proc set_user_property { name value } {
      lappend ::user_list(PROP_NAME) ${name}
      lappend ::user_list(PROP_VAL) ${value}
      }
      # Return list
      proc get_list { list_name } {
      return [ set ::user_list(${list_name}) ]
      }
      # Return list size
      proc get_list_size { list_name } {
      return [ llength [ get_list ${list_name} ] ]
      }
      # Check if verilog source is SystemVerilog
      proc enable_sv_compilation { filename } {
      set extension [ file extension $filename ]
      if { [ string equal ${extension} ".sv" ] } {
      return 1
      } else {
      return 0
      }
      }
      gw/projects/diot_v1/constraints/diot_v1.xdc deleted 100644 → 0
      View file @ e757498e
      ################################################################################
      #
      # Constraints for DIOT System Board Version 1
      #
      ################################################################################
      set_property PACKAGE_PIN AJ4 [get_ports sfp_rxp]
      set_property PACKAGE_PIN AJ3 [get_ports sfp_rxn]
      set_property PACKAGE_PIN AJ8 [get_ports sfp_txp]
      set_property PACKAGE_PIN AJ7 [get_ports sfp_txn]
      set_property PACKAGE_PIN K22 [get_ports {emio_i2c_scl[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {emio_i2c_scl[0]}]
      set_property PACKAGE_PIN J20 [get_ports {emio_i2c_sda[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {emio_i2c_sda[0]}]
      #gtref_clock
      set_property PACKAGE_PIN AH10 [get_ports gtrefclk_in_clk_p]
      #125 MHz
      create_clock -period 8.000 -name gt_ref_clk -waveform {0.000 4.000} [get_ports gtrefclk_in_clk_p]
      set_property IOSTANDARD LVCMOS18 [get_ports *led]
      #GPIO_LED[1]
      #From SFP_ACT_LED from schematic
      set_property PACKAGE_PIN J30 [get_ports {link_status_led[0]}]
      #GPIO_LED[2]
      #From SFP_LINK_LED from schematic
      #GPIO_LED[4]
      #From USER_LED2 from schematic
      set_property PACKAGE_PIN AL26 [get_ports pl_reset_led]
      #GPIO_LED[5]
      #From USER_LED1 from schematic
      set_property PACKAGE_PIN AT27 [get_ports {mdc_clk_led[0]}]
      set_property PACKAGE_PIN K27 [get_ports {link_sync_led[0]}]
      set_property PACKAGE_PIN A11 [get_ports {M_SCL_0[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {M_SCL_0[0]}]
      set_property PACKAGE_PIN A12 [get_ports {M_SDA_0[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {M_SDA_0[0]}]
      set_property PACKAGE_PIN H14 [get_ports {p_pres_i_0[1]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {p_pres_i_0[1]}]
      set_property PACKAGE_PIN G14 [get_ports {p_pres_i_0[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {p_pres_i_0[0]}]
      set_property PACKAGE_PIN A31 [get_ports pwr_cycle_req_o_0]
      set_property IOSTANDARD LVCMOS18 [get_ports pwr_cycle_req_o_0]
      set_property PACKAGE_PIN AL12 [get_ports {wrflash_scl[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {wrflash_scl[0]}]
      set_property PACKAGE_PIN AT15 [get_ports {wrflash_sda[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {wrflash_sda[0]}]
      set_property PACKAGE_PIN B15 [get_ports {bckpl_servmod_b[0]}]
      set_property PACKAGE_PIN A13 [get_ports {bckpl_servmod_b[1]}]
      set_property PACKAGE_PIN B13 [get_ports {bckpl_servmod_b[2]}]
      set_property PACKAGE_PIN B14 [get_ports {bckpl_servmod_b[3]}]
      set_property PACKAGE_PIN C14 [get_ports {bckpl_servmod_b[4]}]
      set_property PACKAGE_PIN C13 [get_ports {bckpl_servmod_b[5]}]
      set_property PACKAGE_PIN D14 [get_ports {bckpl_servmod_b[6]}]
      set_property PACKAGE_PIN A15 [get_ports {bckpl_servmod_b[7]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[7]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[6]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[5]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[4]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[3]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[2]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[1]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[0]}]
      set_property PACKAGE_PIN H11 [get_ports bckpl_rst_n_o]
      set_property IOSTANDARD LVCMOS33 [get_ports bckpl_rst_n_o]
      set_property PACKAGE_PIN AR8 [get_ports psu_alert_i]
      set_property IOSTANDARD LVCMOS18 [get_ports psu_alert_i]
      set_property IOSTANDARD LVCMOS33 [get_ports bckpl_scl]
      set_property IOSTANDARD LVCMOS33 [get_ports bckpl_sda]
      set_property PACKAGE_PIN F15 [get_ports bckpl_scl]
      set_property PACKAGE_PIN G15 [get_ports bckpl_sda]
      set_property PULLUP true [get_ports {bckpl_servmod_b[7]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[6]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[5]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[4]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[3]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[2]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[1]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[0]}]
      set_property PACKAGE_PIN AW5 [get_ports {clk_src_sel_o[1]}]
      set_property PACKAGE_PIN AH17 [get_ports {clk_src_sel_o[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {clk_src_sel_o[1]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {clk_src_sel_o[0]}]
      set_property PACKAGE_PIN J10 [get_ports f_rst]
      set_property IOSTANDARD LVCMOS33 [get_ports f_rst]
      gw/projects/diot_v1/src/constants.vhd deleted 100644 → 0
      View file @ e757498e
      ----------------------------------------------------------------------------------
      -- Company:
      -- Engineer:
      --
      -- Create Date: 06/28/2021 04:30:23 PM
      -- Design Name:
      -- Module Name: constants - Behavioral
      -- Project Name:
      -- Target Devices:
      -- Tool Versions:
      -- Description:
      --
      -- Dependencies:
      --
      -- Revision:
      -- Revision 0.01 - File Created
      -- Additional Comments:
      --
      ----------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      -- Uncomment the following library declaration if instantiating
      -- any Xilinx leaf cells in this code.
      --library UNISIM;
      --use UNISIM.VComponents.all;
      entity constants is
      generic (
      g_phyaddr : integer := 9;
      g_config_vector : integer := 0;
      g_config_valid : integer := 0;
      g_signal_detect : integer := 1);
      Port (
      pl_clk_i : in std_logic;
      -- Vector indicating status. We need bits 0 and 1 of the vector
      status_vector : in std_logic_vector(15 downto 0);
      -- Management clock, (<= 2.5MHz)
      mdc_i : in std_logic;
      mdc_clk_led : out std_logic;
      -- Reset of the module, coming from PS
      pl_resetn_i : in std_logic;
      reset_o : out std_logic;
      -- Autoneg
      an_config_o : out std_logic;
      an_config_vec_o : out std_logic_vector(15 downto 0);
      -- EMIO GPIOs
      p_pres_i : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o : out std_logic;
      bckpl_servmod_i : in std_logic_vector(7 downto 0);
      bckpl_servmod_o : out std_logic_vector(7 downto 0);
      bckpl_servmod_t_o : out std_logic_vector(7 downto 0);
      bckpl_rst_n_o : out std_logic;
      psu_alert_i : in std_logic;
      f_rst_i : in std_logic;
      f_rst_o : out std_logic;
      f_rst_t_o : out std_logic;
      ps_emio_o : out std_logic_vector(15 downto 0);
      ps_emio_i : in std_logic_vector(15 downto 0);
      ps_emio_t_i : in std_logic_vector(15 downto 0);
      -- I2C busses
      wrflash_i2c_irq_i : in std_logic;
      m_i2c_irq_i : in std_logic;
      bckpl_i2c_irq_i : in std_logic;
      ps_irq_o : out std_logic_vector(2 downto 0);
      -- Constants module
      -- Addr of the PHY device(slave). A constant number
      phyaddr : out std_logic_vector(4 downto 0);
      configuration_vector : out std_logic_vector(4 downto 0);
      configuration_valid : out std_logic_vector(0 downto 0);
      --'1' (if not connected to an optical module), otherwise, default is '0'
      signal_detect : out std_logic_vector(0 downto 0);
      -- Slices module
      link_status_led : out std_logic;
      link_sync_led : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0));
      end constants;
      architecture Behavioral of constants is
      -- Because we want to check if mdc_i<=2.5MHz, cnt must be up to 4096
      signal s_cnt : unsigned(11 downto 0);
      signal s_mdc_led_o : std_logic;
      type t_pwr_state is (IDLE, RST);
      signal pwr_state : t_pwr_state;
      signal ps_emio2_d0 : std_logic;
      signal ps_emio2_p : std_logic;
      begin
      an_config_o <= '0';
      an_config_vec_o <= x"D801";
      phyaddr <= std_logic_vector(to_unsigned(g_phyaddr, phyaddr'length));
      configuration_vector <= std_logic_vector(to_unsigned(g_config_vector, configuration_vector'length));
      configuration_valid <= std_logic_vector(to_unsigned(g_config_valid, configuration_valid'length));
      signal_detect <= std_logic_vector(to_unsigned(g_signal_detect, signal_detect'length));
      reset_o <= '1' when (pl_resetn_i = '0') else
      '0';
      link_status_led <= status_vector(0);
      link_sync_led <= status_vector(1);
      clk_src_sel_o <= "11";
      calc_mdc:process(mdc_i, pl_resetn_i)
      begin
      if (pl_resetn_i = '0') then
      s_cnt <= (others=>'0');
      s_mdc_led_o <= '0';
      elsif (rising_edge(mdc_i)) then
      if (s_cnt = 4096-2) then
      s_cnt <= (others=>'0');
      s_mdc_led_o <= '1';
      else
      s_mdc_led_o <= '0';
      s_cnt <= s_cnt + 1;
      end if;
      end if;
      end process;
      mdc_clk_led <= s_mdc_led_o;
      -- EMIO -> PL GPIO
      ps_emio_o(4 downto 0) <= p_pres_i(1 downto 0) & "000";
      ps_emio2_p <= '1' when (ps_emio2_d0 = '0' and ps_emio_i(2) = '1') else
      '0';
      process(pl_clk_i)
      begin
      if rising_edge(pl_clk_i) then
      ps_emio2_d0 <= ps_emio_i(2);
      if pl_resetn_i = '0' or (ps_emio2_p = '1' and ps_emio_i(1) = '1') then
      pwr_state <= IDLE;
      pwr_cycle_req_o <= '0';
      else
      if pwr_state = IDLE then
      pwr_cycle_req_o <= '0';
      if ps_emio2_p = '1' and ps_emio_i(1) = '0' then
      pwr_state <= RST;
      end if;
      elsif pwr_state = RST then
      pwr_cycle_req_o <= '1';
      end if;
      end if;
      end if;
      end process;
      -- EMIO 83..90
      ps_emio_o(12 downto 5) <= bckpl_servmod_i(7 downto 0);
      bckpl_servmod_o(7 downto 0) <= ps_emio_i(12 downto 5);
      bckpl_servmod_t_o(7 downto 0) <= ps_emio_t_i(12 downto 5);
      -- EMIO 91
      ps_emio_o(13) <= ps_emio_i(13);
      bckpl_rst_n_o <= ps_emio_i(13);
      -- EMIO 92
      ps_emio_o(14) <= psu_alert_i;
      -- EMIO 93
      ps_emio_o(15) <= f_rst_i;
      f_rst_o <= ps_emio_i(15);
      f_rst_t_o <= ps_emio_t_i(15);
      -- I2C irqs
      ps_irq_o(2 downto 0) <= bckpl_i2c_irq_i & m_i2c_irq_i & wrflash_i2c_irq_i;
      end Behavioral;
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      --==============================================================================
      --! @file diot_v1_top.vhd
      --==============================================================================
      --------------------------------------------------------------------------------
      -- --
      -- CERN - DIOT V1 --
      -- --
      --------------------------------------------------------------------------------
      --
      -- unit name: diot_v1_top
      --
      --! @brief top level DIOT system board Version 1 based in ZynqMP+
      --
      --! @author alen.arias.vazquez@cern.ch
      --
      --! @date 05/04/2022
      --
      --------------------------------------------------------------------------------
      library ieee;
      library unisim;
      use ieee.std_logic_1164.all;
      use unisim.vcomponents.all;
      --==============================================================================
      --! Entity declaration for diot_v1_top
      --==============================================================================
      entity diot_v1_top is
      port (
      emio_i2c_scl : inout std_logic_vector(0 downto 0);
      emio_i2c_sda : inout std_logic_vector(0 downto 0);
      M_SCL_0 : inout std_logic_vector(0 downto 0);
      M_SDA_0 : inout std_logic_vector(0 downto 0);
      wrflash_scl : inout std_logic_vector(0 downto 0);
      wrflash_sda : inout std_logic_vector(0 downto 0);
      gtrefclk_in_clk_n : in std_logic;
      gtrefclk_in_clk_p : in std_logic;
      link_status_led : out std_logic_vector(0 downto 0);
      link_sync_led : out std_logic_vector(0 downto 0);
      mdc_clk_led : out std_logic_vector(0 downto 0);
      pl_reset_led : out std_logic;
      p_pres_i_0 : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o_0 : out std_logic;
      bckpl_servmod_b : inout std_logic_vector(7 downto 0);
      bckpl_rst_n_o : out std_logic;
      bckpl_scl : inout std_logic;
      bckpl_sda : inout std_logic;
      psu_alert_i : in std_logic;
      f_rst : inout std_logic;
      sfp_rxn : in std_logic;
      sfp_rxp : in std_logic;
      sfp_txn : out std_logic;
      sfp_txp : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0)
      );
      end diot_v1_top;
      --==============================================================================
      --! Architecture declaration
      --==============================================================================
      architecture structure of diot_v1_top is
      component diot_v1 is
      port (
      link_status_led : out std_logic_vector(0 downto 0);
      link_sync_led : out std_logic_vector(0 downto 0);
      mdc_clk_led : out std_logic_vector(0 downto 0);
      emio_i2c_sda : inout std_logic_vector(0 downto 0);
      emio_i2c_scl : inout std_logic_vector(0 downto 0);
      M_SDA_0 : inout std_logic_vector(0 downto 0);
      M_SCL_0 : inout std_logic_vector(0 downto 0);
      wrflash_scl : inout std_logic_vector(0 downto 0);
      wrflash_sda : inout std_logic_vector(0 downto 0);
      pl_reset_led : out std_logic;
      gtrefclk_in_clk_n : in std_logic;
      gtrefclk_in_clk_p : in std_logic;
      p_pres_i_0 : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o_0 : out std_logic;
      bckpl_servmod_b : inout std_logic_vector(7 downto 0);
      bckpl_rst_n_o : out std_logic;
      bckpl_scl : inout std_logic_vector(0 downto 0);
      bckpl_sda : inout std_logic_vector(0 downto 0);
      psu_alert_i : in std_logic;
      f_rst : inout std_logic_vector(0 downto 0);
      sfp_rxn : in std_logic;
      sfp_rxp : in std_logic;
      sfp_txn : out std_logic;
      sfp_txp : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0)
      );
      end component diot_v1;
      --==============================================================================
      --! Architecture begin
      --==============================================================================
      begin
      design_1_i: component diot_v1
      port map (
      emio_i2c_scl(0) => emio_i2c_scl(0),
      emio_i2c_sda(0) => emio_i2c_sda(0),
      M_SCL_0(0) => M_SCL_0(0),
      M_SDA_0(0) => M_SDA_0(0),
      wrflash_scl(0) => wrflash_scl(0),
      wrflash_sda(0) => wrflash_sda(0),
      gtrefclk_in_clk_n => gtrefclk_in_clk_n,
      gtrefclk_in_clk_p => gtrefclk_in_clk_p,
      link_status_led(0) => link_status_led(0),
      link_sync_led(0) => link_sync_led(0),
      mdc_clk_led(0) => mdc_clk_led(0),
      pl_reset_led => pl_reset_led,
      p_pres_i_0 => p_pres_i_0,
      pwr_cycle_req_o_0 => pwr_cycle_req_o_0,
      bckpl_servmod_b => bckpl_servmod_b,
      bckpl_rst_n_o => bckpl_rst_n_o,
      bckpl_scl(0) => bckpl_scl,
      bckpl_sda(0) => bckpl_sda,
      psu_alert_i => psu_alert_i,
      f_rst(0) => f_rst,
      sfp_rxn => sfp_rxn,
      sfp_rxp => sfp_rxp,
      sfp_txn => sfp_txn,
      sfp_txp => sfp_txp,
      clk_src_sel_o => clk_src_sel_o
      );
      end architecture structure;
      --==============================================================================
      -- architecture end
      --==============================================================================
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      # Custom project settings
      set reference_part "xczu7cg-ffvf1517-1-e"
      set project_name "diot_v1"
      set entity_top "diot_v1_top"
      # Hardcoded to 8 to work fine in CI set max_threads [get_number_cpus]
      set max_threads 8
      set project_language "VHDL"
      set lib_default xil_defaultlib
      # Add properties
      set_user_property "default_lib" "xil_defaultlib"
      set_user_property "enable_vhdl_2008" "1"
      set_user_property "xpm_libraries" "XPM_CDC XPM_FIFO XPM_MEMORY"
      # Top Level
      add_vhdl_src ${lib_default} ../src/${entity_top}.vhd
      # Vhdl Src
      add_vhdl_src ${lib_default} ../src/constants.vhd
      # Add Constraints
      add_constraint diot_v1.xdc
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      # ##############################################################################
      #
      # Constraints for DIOT System Board Version 2
      #
      # ##############################################################################
      # ------------------------------------------------------------------------------
      # GT REF CLK: 125 MHz
      set_property PACKAGE_PIN AH10 [get_ports {gtrefclk_in_clk_p}]
      create_clock -period 8.000 -name gt_ref_clk -waveform {0.000 4.000} [get_ports {gtrefclk_in_clk_p}]
      set_property PACKAGE_PIN AA12 [get_ports {aurora_refclk_p}]
      create_clock -period 8.000 -name aurora_ref_clk [get_ports {aurora_refclk_p}]
      # ------------------------------------------------------------------------------
      # Clock Selector
      set_property -dict {PACKAGE_PIN AW5 IOSTANDARD LVCMOS18} [get_ports {clk_src_sel_o[1]}]
      set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVCMOS18} [get_ports {clk_src_sel_o[0]}]
      # ------------------------------------------------------------------------------
      # Power Cycle Request
      set_property -dict {PACKAGE_PIN A31 IOSTANDARD LVCMOS18} [get_ports {pwr_cycle_req_o_0}]
      # ------------------------------------------------------------------------------
      # BUS Monitor
      set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports {f_rst_b}]
      set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {p_pres_i_0[0]}]
      set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {p_pres_i_0[1]}]
      # ------------------------------------------------------------------------------
      # LEDs:
      # SFP_ACT_LED
      set_property -dict {PACKAGE_PIN J30 IOSTANDARD LVCMOS18} [get_ports {link_status_led}]
      # From USER_LED2 from schematic
      set_property -dict {PACKAGE_PIN AL26 IOSTANDARD LVCMOS18} [get_ports {pl_reset_led}]
      # From USER_LED1 from schematic
      set_property -dict {PACKAGE_PIN AT27 IOSTANDARD LVCMOS18} [get_ports {mdc_clk_led}]
      set_property -dict {PACKAGE_PIN K27 IOSTANDARD LVCMOS18} [get_ports {link_sync_led}]
      # ------------------------------------------------------------------------------
      # PSU Alert
      set_property -dict {PACKAGE_PIN AR8 IOSTANDARD LVCMOS18} [get_ports {psu_alert_i}]
      # ------------------------------------------------------------------------------
      # I2C EMIO
      set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS18} [get_ports {emio_scl_b}]
      set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS18} [get_ports {emio_sda_b}]
      # ------------------------------------------------------------------------------
      # I2C wr Flash
      set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS18} [get_ports {wrflash_scl_b}]
      set_property -dict {PACKAGE_PIN AT15 IOSTANDARD LVCMOS18} [get_ports {wrflash_sda_b}]
      # ------------------------------------------------------------------------------
      # I2C Backplane
      set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN F15} [get_ports {bckpl_scl_b}]
      set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN G15} [get_ports {bckpl_sda_b}]
      # ------------------------------------------------------------------------------
      # SFP
      set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {tx_disable_o}]
      set_property PACKAGE_PIN AJ4 [get_ports sfp_rxp]
      set_property PACKAGE_PIN AJ3 [get_ports sfp_rxn]
      set_property PACKAGE_PIN AJ8 [get_ports sfp_txp]
      set_property PACKAGE_PIN AJ7 [get_ports sfp_txn]
      # ------------------------------------------------------------------------------
      # Backplane
      set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[0]}]
      set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[1]}]
      set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[2]}]
      set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[3]}]
      set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[4]}]
      set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[5]}]
      set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[6]}]
      set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[7]}]
      set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports {bckpl_rst_n_o}]
      # ------------------------------------------------------------------------------
      # Aurora GTX pins are defined in the block desing IP GUI
      # Overwriting them here will only generate placement conflicts
      # ------------------------------------------------------------------------------
      # Timing ignore for quasi-static status signals
      set_false_path -from [get_pins diot_v2_i/chip2chip_subsystem/link_*/aurora/*/*/*/CHANNEL_UP_reg/C] \
      -to [get_pins {diot_v2_i/chip2chip_subsystem/c2c_link_ctrl/*/*/rd_data_reg[0]/D}]
      set_false_path -from [get_pins diot_v2_i/chip2chip_subsystem/link_*/aurora/*/*/*/CHANNEL_HARD_ERR_reg/C] \
      -to [get_pins {diot_v2_i/chip2chip_subsystem/c2c_link_ctrl/*/*/rd_data_reg[1]/D}]
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      -------------------------------------------------------------------------------
      --! @file c2c_link.vhd
      --! @author Adrian Byszuk
      --! @copyright CERN SY-EPC-CCE
      --! @date 05-07-2022
      --! @brief Chip2Chip link control and status
      -------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      --! @brief Chip2Chip link control and status
      --! @details
      --! Provides software with basic control and diagnostic capabilities.
      --! Intended to be easily integrated with Xilinx Block Design.
      --! Supports up to 8 links, which is maximum in a standard DIOT crate.
      entity c2c_link is
      generic (
      addr_width_g : positive := 6
      );
      port (
      --! @name AXI4Lite slave bus (naming convention compatible with Xilinx IP Integrator)
      s_axi_aclk : in std_ulogic;
      s_axi_aresetn : in std_ulogic;
      --
      s_axi_awvalid : in std_logic;
      s_axi_awready : out std_logic;
      s_axi_awaddr : in std_logic_vector(addr_width_g-1 downto 0);
      --
      s_axi_wvalid : in std_logic;
      s_axi_wready : out std_logic;
      s_axi_wdata : in std_logic_vector(31 downto 0);
      s_axi_wstrb : in std_logic_vector(3 downto 0);
      --
      s_axi_bvalid : out std_logic;
      s_axi_bready : in std_logic;
      s_axi_bresp : out std_logic_vector(1 downto 0);
      --
      s_axi_arvalid : in std_logic;
      s_axi_arready : out std_logic;
      s_axi_araddr : in std_logic_vector(addr_width_g-1 downto 0);
      --
      s_axi_rvalid : out std_logic;
      s_axi_rready : in std_logic;
      s_axi_rdata : out std_logic_vector(31 downto 0);
      s_axi_rresp : out std_logic_vector(1 downto 0);
      --! @name Aurora/Chip2Chip signals (for meaning of some signals see the IP documentation)
      --! Output reset vector is split to avoid stupid block design slicing
      reset_0 : out std_logic; --! PMA reset to link 0
      reset_1 : out std_logic; --! PMA reset to link 1
      reset_2 : out std_logic; --! PMA reset to link 2
      reset_3 : out std_logic; --! PMA reset to link 3
      reset_4 : out std_logic; --! PMA reset to link 4
      reset_5 : out std_logic; --! PMA reset to link 5
      reset_6 : out std_logic; --! PMA reset to link 6
      reset_7 : out std_logic; --! PMA reset to link 7
      channel_up : in std_logic_vector(7 downto 0); --! Aurora channel_up status
      hard_err : in std_logic_vector(7 downto 0); --! Aurora hard_err status
      gt_pll_lock : in std_logic_vector(7 downto 0); --! MGT PLL lock status
      link_status : in std_logic_vector(7 downto 0); --! Chip2Chip link up status
      config_error : in std_logic_vector(7 downto 0); --! Chip2Chip endpoint config error
      link_error : in std_logic_vector(7 downto 0); --! Chip2Chip link error
      multi_bit_error : in std_logic_vector(7 downto 0) --! Chip2Chip multi_bit error status
      );
      end entity c2c_link;
      --! RTL implementation of c2c_link
      architecture rtl of c2c_link is
      --! @name Attributes required to silence Vivado BD GUI
      ATTRIBUTE X_INTERFACE_INFO : STRING;
      ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
      ATTRIBUTE X_INTERFACE_INFO OF reset_0: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_0: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF reset_1: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_1: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF reset_2: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_2: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF reset_3: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_3: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF reset_4: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_4: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF reset_5: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_5: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF reset_6: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_6: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF reset_7: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_7: SIGNAL is "POLARITY ACTIVE_HIGH";
      --! @}
      begin
      --! Wishbone registers (autogenerated)
      x_regs : entity work.link_ctrl_regs
      port map (
      aclk => s_axi_aclk,
      areset_n => s_axi_aresetn,
      awvalid => s_axi_awvalid,
      awready => s_axi_awready,
      awaddr => s_axi_awaddr,
      awprot => "000",
      wvalid => s_axi_wvalid,
      wready => s_axi_wready,
      wdata => s_axi_wdata,
      wstrb => s_axi_wstrb,
      bvalid => s_axi_bvalid,
      bready => s_axi_bready,
      bresp => s_axi_bresp,
      arvalid => s_axi_arvalid,
      arready => s_axi_arready,
      araddr => s_axi_araddr,
      arprot => "000",
      rvalid => s_axi_rvalid,
      rready => s_axi_rready,
      rdata => s_axi_rdata,
      rresp => s_axi_rresp,
      link_0_ctrl_reset_o => reset_0,
      link_0_status_channel_up_i => channel_up(0),
      link_0_status_hard_err_i => hard_err(0),
      link_0_status_gt_pll_lock_i => gt_pll_lock(0),
      link_0_status_link_status_i => link_status(0),
      link_0_status_config_error_i => config_error(0),
      link_0_status_link_error_i => link_error(0),
      link_0_status_multi_bit_error_i => multi_bit_error(0),
      link_1_ctrl_reset_o => reset_1,
      link_1_status_channel_up_i => channel_up(1),
      link_1_status_hard_err_i => hard_err(1),
      link_1_status_gt_pll_lock_i => gt_pll_lock(1),
      link_1_status_link_status_i => link_status(1),
      link_1_status_config_error_i => config_error(1),
      link_1_status_link_error_i => link_error(1),
      link_1_status_multi_bit_error_i => multi_bit_error(1),
      link_2_ctrl_reset_o => reset_2,
      link_2_status_channel_up_i => channel_up(2),
      link_2_status_hard_err_i => hard_err(2),
      link_2_status_gt_pll_lock_i => gt_pll_lock(2),
      link_2_status_link_status_i => link_status(2),
      link_2_status_config_error_i => config_error(2),
      link_2_status_link_error_i => link_error(2),
      link_2_status_multi_bit_error_i => multi_bit_error(2),
      link_3_ctrl_reset_o => reset_3,
      link_3_status_channel_up_i => channel_up(3),
      link_3_status_hard_err_i => hard_err(3),
      link_3_status_gt_pll_lock_i => gt_pll_lock(3),
      link_3_status_link_status_i => link_status(3),
      link_3_status_config_error_i => config_error(3),
      link_3_status_link_error_i => link_error(3),
      link_3_status_multi_bit_error_i => multi_bit_error(3),
      link_4_ctrl_reset_o => reset_4,
      link_4_status_channel_up_i => channel_up(4),
      link_4_status_hard_err_i => hard_err(4),
      link_4_status_gt_pll_lock_i => gt_pll_lock(4),
      link_4_status_link_status_i => link_status(4),
      link_4_status_config_error_i => config_error(4),
      link_4_status_link_error_i => link_error(4),
      link_4_status_multi_bit_error_i => multi_bit_error(4),
      link_5_ctrl_reset_o => reset_5,
      link_5_status_channel_up_i => channel_up(5),
      link_5_status_hard_err_i => hard_err(5),
      link_5_status_gt_pll_lock_i => gt_pll_lock(5),
      link_5_status_link_status_i => link_status(5),
      link_5_status_config_error_i => config_error(5),
      link_5_status_link_error_i => link_error(5),
      link_5_status_multi_bit_error_i => multi_bit_error(5),
      link_6_ctrl_reset_o => reset_6,
      link_6_status_channel_up_i => channel_up(6),
      link_6_status_hard_err_i => hard_err(6),
      link_6_status_gt_pll_lock_i => gt_pll_lock(6),
      link_6_status_link_status_i => link_status(6),
      link_6_status_config_error_i => config_error(6),
      link_6_status_link_error_i => link_error(6),
      link_6_status_multi_bit_error_i => multi_bit_error(6),
      link_7_ctrl_reset_o => reset_7,
      link_7_status_channel_up_i => channel_up(7),
      link_7_status_hard_err_i => hard_err(7),
      link_7_status_gt_pll_lock_i => gt_pll_lock(7),
      link_7_status_link_status_i => link_status(7),
      link_7_status_config_error_i => config_error(7),
      link_7_status_link_error_i => link_error(7),
      link_7_status_multi_bit_error_i => multi_bit_error(7)
      );
      end architecture rtl;
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      memory-map:
      bus: axi4-lite-32
      name: link_ctrl_regs
      description: Aurora link control/status
      x-hdl:
      bus-granularity: byte
      children:
      - repeat:
      name: link
      description: Data to be sent to DAC
      count: 8
      children:
      - reg:
      name: ctrl
      description: Control register
      width: 32
      access: rw
      type: unsigned
      children:
      - field:
      name: reset
      description: Reset the Aurora link
      range: 0
      preset: 0
      x-hdl:
      type: autoclear
      - reg:
      name: status
      description: Status register
      type: unsigned
      width: 32
      access: ro
      children:
      - field:
      name: channel_up
      description: Aurora channel is up and running
      range: 0
      - field:
      name: hard_err
      description: Aurora hard error - reset required
      range: 1
      - field:
      name: gt_pll_lock
      description: MGT PLL is locked
      range: 2
      - field:
      name: link_status
      description: Chip2Chip link is up and running
      range: 3
      - field:
      name: config_error
      description: Chip2Chip config error (see Xilinx PG067)
      range: 4
      - field:
      name: link_error
      description: Chip2Chip link error (see Xilinx PG067)
      range: 5
      - field:
      name: multi_bit_error
      description: Chip2Chip multi-bit error (see Xilinx PG067)
      range: 6
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      gw/projects/diot_v2/src/ps2pl_glue.vhd deleted 100644 → 0
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      -------------------------------------------------------------------------------
      --! @file ps2pl_glue.vhd
      --! @author Adrian Byszuk <adrian.byszuk@cern.ch>
      --! @company CERN
      --! @date 2021-06-28
      --! @brief PS to PL glue logic and hardcoded config
      -------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      --! @brief PS to PL glue logic and hardcoded config signals
      entity ps2pl_glue is
      generic (
      g_phyaddr : natural := 9; --! Ethernet PHY MDIO address
      g_config_vector : natural := 0; --! Ethernet IP configuration vector
      g_config_valid : std_logic_vector := "0"; --! Configuration vector is valid
      g_signal_detect : std_logic_vector := "1" --! SFP signal detected status
      );
      Port (
      --! @name Fundamental clock and reset
      pl_clk_i : in std_logic; --! PL clock
      pl_resetn_i : in std_logic; --! Reset of the module, coming from PS
      reset_o : out std_logic; --! Reset to the PL
      --! @name Ethernet config and status
      --! MAC status. Check Xilinx docs for detailed info
      status_vector_i : in std_logic_vector(15 downto 0);
      mdc_i : in std_logic; --! Management clock, (<= 2.5MHz)
      mdc_clk_led_o : out std_logic; --! MDC activity LED
      an_config_o : out std_logic;
      --! Config data for autonegotiation
      an_config_vec_o : out std_logic_vector(15 downto 0);
      tx_disable_o : out std_logic;
      --! @}
      --! @name EMIO GPIOs
      p_pres_i : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o : out std_logic;
      bckpl_servmod_i : in std_logic_vector(7 downto 0);
      bckpl_servmod_o : out std_logic_vector(7 downto 0);
      bckpl_servmod_t_o : out std_logic_vector(7 downto 0);
      bckpl_rst_n_o : out std_logic;
      psu_alert_i : in std_logic;
      f_rst_i : in std_logic;
      f_rst_o : out std_logic;
      f_rst_t_o : out std_logic;
      ps_emio_o : out std_logic_vector(15 downto 0);
      ps_emio_i : in std_logic_vector(94 downto 0);
      ps_emio_t_i : in std_logic_vector(15 downto 0);
      --! @name I2C bus and other IRQs
      wrflash_i2c_irq_i : in std_logic;
      bckpl_i2c_irq_i : in std_logic;
      aurora_dma_irq_i : in std_logic;
      ps_irq_o : out std_logic_vector(2 downto 0);
      --! @name Constants module
      --! Addr of the PHY device(slave). A constant number
      phyaddr_o : out std_logic_vector(4 downto 0);
      --! PHY IP configuration vector (consult with Xilinx documentation)
      configuration_vector_o : out std_logic_vector(4 downto 0);
      --! Configuration vector is valid
      configuration_valid_o : out std_logic_vector(0 downto 0);
      --! Optical signal detected ('1' if not connected to an optical module)
      signal_detect_o : out std_logic_vector(0 downto 0);
      --! @name Slices module
      link_status_led_o : out std_logic;
      link_sync_led_o : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0)
      );
      end ps2pl_glue;
      architecture Behavioral of ps2pl_glue is
      --! @name Port attributes for Xilinx IP Integrator
      ATTRIBUTE X_INTERFACE_INFO : STRING;
      ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
      ATTRIBUTE X_INTERFACE_INFO OF pl_clk_i: signal IS "xilinx.com:signal:clock:1.0 pl_clk_i CLK";
      ATTRIBUTE X_INTERFACE_PARAMETER of pl_clk_i: SIGNAL is "ASSOCIATED_RESET pl_resetn_i";
      ATTRIBUTE X_INTERFACE_INFO OF pl_resetn_i: SIGNAL IS "xilinx.com:signal:reset:1.0 pl_resetn_i RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of pl_resetn_i: SIGNAL is "POLARITY ACTIVE_LOW";
      ATTRIBUTE X_INTERFACE_INFO OF reset_o: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_o: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF mdc_i: signal IS "xilinx.com:signal:clock:1.0 mdc_i CLK";
      ATTRIBUTE X_INTERFACE_INFO of ps_irq_o: SIGNAL is "xilinx.com:signal:interrupt:1.0 ps_irq_o INTERRUPT";
      ATTRIBUTE X_INTERFACE_INFO of wrflash_i2c_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 wrflash_i2c_irq_i INTERRUPT";
      ATTRIBUTE X_INTERFACE_INFO of bckpl_i2c_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 bckpl_i2c_irq_i INTERRUPT";
      ATTRIBUTE X_INTERFACE_INFO of aurora_dma_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 aurora_dma_irq_i INTERRUPT";
      --! @}
      -- Because we want to check if mdc_i<=2.5MHz, cnt must be up to 4096
      signal s_cnt : unsigned(11 downto 0);
      signal s_mdc_led : std_logic;
      type t_pwr_state is (IDLE, RST);
      signal pwr_state : t_pwr_state;
      signal ps_emio2_d0 : std_logic;
      signal ps_emio2_p : std_logic;
      begin
      an_config_o <= '0';
      an_config_vec_o <= x"D801";
      tx_disable_o <= '0';
      phyaddr_o <= std_logic_vector(to_unsigned(g_phyaddr, phyaddr_o'length));
      configuration_vector_o <= std_logic_vector(to_unsigned(g_config_vector, configuration_vector_o'length));
      configuration_valid_o <= g_config_valid;
      signal_detect_o <= g_signal_detect;
      reset_o <= '1' when (pl_resetn_i = '0') else
      '0';
      link_status_led_o <= status_vector_i(0);
      link_sync_led_o <= status_vector_i(1);
      clk_src_sel_o <= "11";
      calc_mdc: process(mdc_i, pl_resetn_i)
      begin
      if (pl_resetn_i = '0') then
      s_cnt <= (others => '0');
      s_mdc_led <= '0';
      elsif (rising_edge(mdc_i)) then
      if (s_cnt = 4096-2) then
      s_cnt <= (others=>'0');
      s_mdc_led <= '1';
      else
      s_mdc_led <= '0';
      s_cnt <= s_cnt + 1;
      end if;
      end if;
      end process;
      mdc_clk_led_o <= s_mdc_led;
      -- EMIO -> PL GPIO
      ps_emio_o(4 downto 0) <= p_pres_i(1 downto 0) & "000";
      ps_emio2_p <= '1' when (ps_emio2_d0 = '0' and ps_emio_i(2) = '1') else
      '0';
      process(pl_clk_i)
      begin
      if rising_edge(pl_clk_i) then
      ps_emio2_d0 <= ps_emio_i(2);
      if pl_resetn_i = '0' or (ps_emio2_p = '1' and ps_emio_i(1) = '1') then
      pwr_state <= IDLE;
      pwr_cycle_req_o <= '0';
      else
      if pwr_state = IDLE then
      pwr_cycle_req_o <= '0';
      if ps_emio2_p = '1' and ps_emio_i(1) = '0' then
      pwr_state <= RST;
      end if;
      elsif pwr_state = RST then
      pwr_cycle_req_o <= '1';
      end if;
      end if;
      end if;
      end process;
      -- EMIO 83..90
      ps_emio_o(12 downto 5) <= bckpl_servmod_i(7 downto 0);
      bckpl_servmod_o(7 downto 0) <= ps_emio_i(12 downto 5);
      bckpl_servmod_t_o(7 downto 0) <= ps_emio_t_i(12 downto 5);
      -- EMIO 91
      ps_emio_o(13) <= ps_emio_i(13);
      bckpl_rst_n_o <= ps_emio_i(13);
      -- EMIO 92
      ps_emio_o(14) <= psu_alert_i;
      -- EMIO 93
      ps_emio_o(15) <= f_rst_i;
      f_rst_o <= ps_emio_i(15);
      f_rst_t_o <= ps_emio_t_i(15);
      -- I2C irqs
      ps_irq_o <= aurora_dma_irq_i & bckpl_i2c_irq_i & wrflash_i2c_irq_i;
      end Behavioral;
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      #!/bin/sh
      NAME="c2c_link_regs"
      # commands must be executed from script directory, where both script and .cheby files are
      cd "$(dirname "$(readlink -f "$0")")"
      cheby --print-simple --gen-hdl=$NAME.vhd --gen-doc=$NAME.html -i $NAME.cheby
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      # Custom project settings
      set reference_part "xczu7cg-ffvf1517-1-e"
      set project_name "diot_v2"
      set entity_top "diot_v2_top"
      # Hardcoded to 8 to work fine in CI set max_threads [get_number_cpus]
      set max_threads 8
      set lib_default xil_defaultlib
      # Common IP directory
      set COMMON_IP ../../../common-ip
      # Add properties
      set_user_property "default_lib" "xil_defaultlib"
      set_user_property "enable_vhdl_2008" "1"
      set_user_property "xpm_libraries" "XPM_CDC XPM_FIFO XPM_MEMORY"
      # Top Level
      add_vhdl_src ${lib_default} ../src/${entity_top}.vhd
      # Vhdl Src
      add_vhdl_src ${lib_default} ../src/ps2pl_glue.vhd
      add_vhdl_src ${lib_default} ../src/c2c_link_regs.vhd
      add_vhdl_src ${lib_default} ../src/c2c_link.vhd
      # Add Constraints
      add_constraint diot_v2.xdc
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      artifacts
      _done
      build
      log
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      /* Linux */
      the_ROM_image:
      {
      [bootloader, destination_cpu = a53-0] fsbl.elf
      [destination_cpu = pmu] pmufw.elf
      [destination_device = pl] pl_gateware.bit
      [destination_cpu = a53-0, exception_level = el-3, trustzone = secure] bl31.elf
      [destination_cpu = a53-0, exception_level = el-2] u-boot.elf
      }
      sw/configs/bootfw/Si5341-RevD-diot_sb-Registers.h deleted 100644 → 0
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      sw/configs/bootfw/app.tcl deleted 100755 → 0
      View file @ e757498e
      package require cmdline
      package require yaml
      proc clean_n_build {type name} {
      cd $params(ws)
      cd $name
      make clean
      }
      proc build_only {type name} {
      cd $params(ws)
      cd $name
      make
      }
      proc env_read {name} {
      # Assume env as false if dosent exists
      if { [info exists ::env($name)] } {
      return $::env($name)
      }
      return 0
      }
      proc check_ws {workspace} {
      # Check if any Projects exits and import them to retain right metadata
      }
      set option {
      {hdf.arg "" "hardware Definition file"}
      {processor.arg "" "target processor"}
      {osname.arg "standalone" "target OS"}
      {rp.arg "" "repo path"}
      {app.arg "Empty Application" "Application project fsbl, empty.."}
      {lib.arg "" "Add library"}
      {pname.arg "" "Project Name"}
      {bspname.arg "" "standalone bsp name"}
      {ws.arg "" "Work Space Path"}
      {hwpname.arg "" "hardware project name"}
      {arch.arg "64" "32/64 bit architecture"}
      {do_compile.arg "0" "Build the project"}
      {forceconf.arg "0" "Apply the yaml comfigs on existing project"}
      {yamlconf.arg "" "Path to Config File"}
      }
      set usage "xsct app.tcl <arguments>"
      array set params [cmdline::getoptions argv $option $usage]
      proc set_app_conf {action prop val} {
      if { $prop == "build-config" } {
      if { $val == "Debug"} {
      set flags "-O0 -g3"
      ::sdk::append_app_compiler_flags $flags
      } else {
      #puts "DEBUG: No change for Release Configuration."
      }
      } else {
      ::sdk::append_app_compiler_flags $val
      }
      }
      proc set_bsp_conf {action prop val} {
      if { $action == "set"} {
      if { [catch {bsp config $prop $val} result1] } {
      if { [catch {bsp config $prop $val} result2] } {
      puts "ERROR:[info level 0]: Cannot set Property \"$prop\" with $val \n$result2"
      }
      }
      } else {
      if { [catch {bsp config -$action $prop $val} result1] } {
      if { [catch {bsp config $prop $val} result2] } {
      puts "ERROR:[info level 0]: Cannot set Property \"$prop\" with $val \n$result2"
      }
      }
      }
      }
      proc xsct_config {type conf} {
      foreach prop [dict keys $conf] {
      foreach action [dict keys [dict get $conf $prop]] {
      set_$type\_conf $action $prop [dict get $conf $prop $action]
      }
      }
      }
      proc xsct_set_libs {addlib} {
      foreach l $addlib {
      bsp setlib -name $l
      }
      }
      proc do_bsp_config {conf} {
      # Availabe BSP configs
      # proc :
      # archiver ex: aarch64-none-elf-ar
      # compiler ex: aarch64-none-elf-gcc
      # compiler_flags
      # extra_compiler_flags
      #
      # OS: (standalone)
      # enable_sw_intrusive_profiling
      # microblaze_exceptions
      # predecode_fpu_exceptions
      # profile_timer
      # stdin
      # stdout
      #
      # Also can configure Library Specific Configs
      #
      # puts "DEBUG: bsp conf $conf "
      if { [catch {xsct_config bsp [dict get $conf bsp]} result] } {
      puts "XSCTHELPER INFO: No BSP Configuration \n\t $result"
      }
      }
      proc do_app_config {conf} {
      # Available App Configurations
      # assembler-flags Miscellaneous flags for assembler
      # build-config Get/set build configuration
      # compiler-misc Compiler miscellaneous flags
      # compiler-optimization Optimization level
      # define-compiler-symbols Define symbols. Ex. MYSYMBOL
      # include-path Include path for header files
      # libraries Libraries to be added while linking
      # library-search-path Search path for the libraries added
      # linker-misc Linker miscellaneous flags
      # linker-script Linker script for linking the program sections
      # undef-compiler-symbols Undefine symbols. Ex. MYSYMBOL
      #
      # puts "DEBUG: app conf $conf "
      if { [catch {xsct_config app [dict get $conf app]} result] } {
      puts "XSCTHELPER INFO: No APP configuration \n\t $result"
      }
      }
      set libs [split $params(lib) { }]
      # Workspace required
      if { $params(ws) ne "" } {
      #Local Work Space available
      if { $params(pname) ne "" } {
      # hwpname/bspname is empty then default it to pname+_hwproj/bsp
      if {$params(hwpname) eq ""} {
      set params(hwpname) "$params(pname)\_plat"
      }
      if {$params(bspname) eq ""} {
      set params(bspname) "$params(pname)\_domain"
      # set autogenbsp 1
      }
      if { $params(do_compile) == 1 } {
      clean_n_build app $params(pname)
      build_only app $params(pname)
      exit 0
      }
      if { $params(yamlconf) ne "" } {
      set conf_dict [::yaml::yaml2dict -file $params(yamlconf)]
      }
      if { $params(rp) ne "none" } {
      #Local Repo Available, Set repo path. Or will pick it up from build
      set path [split $params(rp) { }]
      ::hsi::utils::add_repo "$path/lib $path"
      }
      # Check if $hwpname exist
      catch {cd $params(ws) }
      if { [catch { set dirlist [glob -type d *] } msg ] } {
      set poke_hwproj -1
      set poke_app -1
      } else {
      set poke_hwproj [lsearch -exact $dirlist $params(hwpname)]
      set poke_app [lsearch -exact $dirlist $params(pname)]
      }
      if { $poke_hwproj >= 0 } {
      puts "INFO: Update hw $params(hwpname) project"
      cd $params(ws)
      set platname $params(hwpname)
      platform read $params(ws)/$platname/platform.spr
      platform remove $platname
      }
      platform create -name $params(hwpname) -hw $params(hdf) -out $params(ws)
      set hsitemplate [::scw::get_app_template $params(app)]
      sysconfig create -name sysconfig1
      domain create -name $params(bspname) -proc $params(processor) \
      -os $params(osname) -support-app $hsitemplate -arch $params(arch)
      if { [info exists conf_dict] } {
      xsct_set_libs $libs
      do_bsp_config $conf_dict
      platform generate -quick
      }
      puts "INFO: create bsp using $params(bspname)"
      cd $params(ws)
      set platname $params(hwpname)
      # Create a App for custom bsp
      if { [info exists conf_dict] } {
      do_app_config $conf_dict
      }
      app create -name $params(pname) -lang c -template $params(app) -plnx
      }
      } else {
      # Error: Workspace is needed
      puts stderr "ERROR: Workspace not mentioned"
      }
      exit
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      {app: {build-config: {set: release}}, bsp: {periph_type_overrides: {set: '{BOARD template}'}, stdin: {set: psu_uart_0}, stdout: {set: psu_uart_0}}}
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      {app: {build-config: {set: release}, compiler-misc: {add: ' -DENABLE_MOD_ULTRA96 '}}, bsp: {periph_type_overrides: {set: '{BOARD template}'}, stdin: {set: psu_uart_0}, stdout: {set: psu_uart_0}}}
      sw/configs/device-tree/base-hsi.tcl deleted 100644 → 0
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      #requires xsa repo path proc dir yaml-file-location
      package require cmdline
      package require yaml
      proc get_os_config_list {} {
      set prop_data [hsi report_property -all -return_string \
      [hsi get_os] CONFIG.*]
      set conf_data [split $prop_data "\n"]
      set config_list {}
      foreach line $conf_data {
      if { [regexp "^CONFIG..*" $line matched] == 1 } {
      set config_name [split $line " "]
      set config_name [lindex $config_name 0]
      regsub -- "CONFIG." $config_name "" config_name
      lappend config_list $config_name
      }
      }
      return $config_list
      }
      proc set_properties { yamlconf } {
      set os_config_list [get_os_config_list]
      if { $yamlconf ne "" } {
      set conf_dict [::yaml::yaml2dict -file $yamlconf]
      if {[dict exists $conf_dict "bsp"]} {
      foreach prop [dict keys [dict get $conf_dict "bsp"]] {
      foreach action [dict keys \
      [dict get $conf_dict "bsp" $prop]] {
      if { [lsearch -exact -nocase $os_config_list $prop] < 0} {
      continue
      }
      if { [catch {hsi set_property CONFIG.$prop \
      [dict get $conf_dict "bsp" $prop $action] \
      [hsi get_os]} res] } {
      error "NO BSP configuration available"
      }
      }
      }
      }
      }
      }
      proc set_hw_design {project hdf hdf_type} {
      file mkdir $project
      if { [catch { exec cp $hdf $project/hardware_description.$hdf_type } msg] } {
      puts "$::errorInfo"
      }
      if { [catch {openhw $project/hardware_description.$hdf_type} res] } {
      error "Failed to open hardware design \
      $project/hardware_description.$hdf_type"
      }
      }
      sw/configs/device-tree/device-tree.yaml deleted 100644 → 0
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      {app: {compiler-misc: {add: None}}, bsp: {console_device: {set: psu_uart_0}, main_memory: {set: PSU_DDR_0}, overlay_custom_dts: {set: pl-final.dts}, periph_type_overrides: {set: '{BOARD template}'}}}
      sw/configs/device-tree/dtgen.tcl deleted 100644 → 0
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      set dir [file dirname [info script]]
      source $dir/base-hsi.tcl
      set option {
      {hdf.arg "" "hardware Definition file"}
      {hdf_type.arg "hdf" "hardware Defination file type: xsa"}
      {processor.arg "" "target processor"}
      {rp.arg "" "repo path"}
      {app.arg "empty_application" "Application project fsbl, empty.."}
      {lib.arg "" "Add library"}
      {pname.arg "" "Project Name"}
      {bspname.arg "" "standalone bsp name"}
      {ws.arg "" "Work Space Path"}
      {hwpname.arg "" "hardware project name"}
      {arch.arg "64" "32/64 bit architecture"}
      {do_compile.arg "0" "Build the project"}
      {forceconf.arg "0" "Apply the yaml configs on existing project"}
      {yamlconf.arg "" "Path to Config File"}
      }
      set usage "A script to generate and compile device-tree"
      array set params [::cmdline::getoptions argv $option $usage]
      set project "$params(ws)/$params(pname)"
      set_hw_design $project $params(hdf) $params(hdf_type)
      if { [catch {hsi set_repo_path $params(rp)} res] } {
      error "Failed to set repo path $params(rp)"
      }
      if {[catch {hsi create_sw_design $params(app) \
      -os device_tree -proc $params(processor)} res] } {
      error "create_sw_design failed for $params(app)"
      }
      if {[file exists $params(yamlconf)]} {
      set_properties $params(yamlconf)
      }
      if {[catch {hsi generate_target -dir $project} res]} {
      error "generate_target failed"
      }
      if { [catch {hsi close_hw_design [hsi current_hw_design]} res] } {
      error "Failed to close hw design [hsi current_hw_design]"
      }
      sw/configs/device-tree/pl-user_v1.dtsi deleted 100644 → 0
      View file @ e757498e
      /*
      * author: Adam Wujek
      * copyright: CERN 2021
      */
      / {
      };
      &axi_iic_0 {
      interrupt-names = "iic2intc_irpt";
      interrupt-parent = <&gic>;
      interrupts = <0 89 4>;
      wr_eeprom: eeprom@50 {
      compatible = "atmel,24c64";
      reg = <0x50>;
      // read-only;
      };
      mac_eeprom: eeprom@51 {
      compatible = "atmel,24c02";
      reg = <0x51>;
      read-only;
      /* MAC is at the offset 0xfa */
      };
      };
      &axi_iic_1 {
      interrupt-names = "iic2intc_irpt";
      interrupt-parent = <&gic>;
      interrupts = <0 90 4>;
      fantray: monimod@12 {
      compatible = "monimod";
      reg = <0x12>;
      };
      psu1: psu@18 {
      compatible = "D57500520";
      reg = <0x18>;
      };
      psu2: psu@19 {
      compatible = "D57500520";
      reg = <0x19>;
      };
      };
      &axi_iic_2 {
      interrupt-names = "iic2intc_irpt";
      interrupt-parent = <&gic>;
      interrupts = <0 91 4>;
      pb: pb@50 {
      compatible = "atmel,24c02";
      reg = <0x50>;
      };
      };
      sw/configs/device-tree/pl-user_v2.dtsi deleted 100644 → 0
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      sw/patches/bootfw/0002-sw_apps-zynqmp_fsbl-exclude-fsbl-secure.patch deleted 100644 → 0
      View file @ e757498e
      From 030bfd9334c7489a14605194046b3230d4adf74e Mon Sep 17 00:00:00 2001
      From: Adam Wujek <dev_public@wujek.eu>
      Date: Thu, 2 Dec 2021 00:45:27 +0100
      Subject: [PATCH 1/3] sw_apps: zynqmp_fsbl: exclude fsbl secure
      Signed-off-by: Adam Wujek <dev_public@wujek.eu>
      ---
      lib/sw_apps/zynqmp_fsbl/src/xfsbl_config.h | 2 +-
      1 file changed, 1 insertion(+), 1 deletion(-)
      diff --git a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_config.h b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_config.h
      index f7fccd5566..3f3eaa5d8d 100644
      --- a/lib/sw_apps/zynqmp_fsbl/src/xfsbl_config.h
      +++ b/lib/sw_apps/zynqmp_fsbl/src/xfsbl_config.h
      @@ -132,7 +132,7 @@ extern "C" {
      #define FSBL_NAND_EXCLUDE_VAL (0U)
      #define FSBL_QSPI_EXCLUDE_VAL (0U)
      #define FSBL_SD_EXCLUDE_VAL (0U)
      -#define FSBL_SECURE_EXCLUDE_VAL (0U)
      +#define FSBL_SECURE_EXCLUDE_VAL (1U)
      #define FSBL_BS_EXCLUDE_VAL (0U)
      #define FSBL_EARLY_HANDOFF_EXCLUDE_VAL (1U)
      #define FSBL_WDT_EXCLUDE_VAL (0U)
      --
      2.25.1
      sw/petalinux/.gitignore deleted 100644 → 0
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      */*/config.old
      */*/rootfs_config.old
      build/
      images/linux/
      pre-built/linux/
      .petalinux/*
      !.petalinux/metadata
      *.o
      *.jou
      *.log
      project-spec/meta-plnx-generated/
      project-spec/hw-description
      /components/plnx_workspace
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