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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit e757498e authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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remove hw design files, they are now stored in EDMS

parent 6051d5dc
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      hw/DIOT_System_Board.OutJob deleted 100644 → 0
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      hw/DIOT_System_Board.PrjPcb deleted 100644 → 0
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      hw/DIOT_System_Board.PrjPcbStructure deleted 100644 → 0
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      hw/SIM/power_budget.ltp3 deleted 100644 → 0
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      hw/fpga_pin_delays.csv deleted 100644 → 0
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      hw/manufacturing/DIOT_System_Board_Gerber/DIOT_System_Board-macro.APR_LIB deleted 100644 → 0
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      hw/manufacturing/DIOT_System_Board_Gerber/DIOT_System_Board.EXTREP deleted 100644 → 0
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      ------------------------------------------------------------------------------------------
      Gerber File Extension Report For: DIOT_System_Board.GBR 23.11.2021 18:58:58
      ------------------------------------------------------------------------------------------
      ------------------------------------------------------------------------------------------
      Layer Extension Layer Description
      ------------------------------------------------------------------------------------------
      .GTO Top Overlay
      .GTP Top Paste
      .GTS Top Solder
      .GTL Top Layer
      .GP1 L2GND
      .G1 L3
      .GP2 L4PWR
      .G2 L5
      .GP3 L6GND
      .G3 L7
      .G4 L8
      .GP4 L9GND
      .G5 L10
      .GP5 L11PWR
      .G6 L12
      .GP6 L13GND
      .GBL Bottom Layer
      .GBS Bottom Solder
      .GBP Bottom Paste
      .GBO Bottom Overlay
      .GM1 Board outline
      .GM2 Board information
      .GD1 Drill Drawing
      .GD2 Drill Drawing
      .GD3 Drill Drawing
      .GG1 Drill Guide
      .GG2 Drill Guide
      .GG3 Drill Guide
      ------------------------------------------------------------------------------------------
      hw/manufacturing/DIOT_System_Board_Gerber/DIOT_System_Board.GG2 deleted 100644 → 0
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      hw/manufacturing/DIOT_System_Board_Gerber/DIOT_System_Board.GG3 deleted 100644 → 0
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      G04*
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      Y165212D01*
      X647216Y164617D02*
      X648405D01*
      X647810Y164023D02*
      Y165212D01*
      M02*
      hw/manufacturing/DIOT_System_Board_Gerber/DIOT_System_Board.GM1 deleted 100644 → 0
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      G04*
      G04 #@! TF.GenerationSoftware,Altium Limited,Altium Designer,21.8.1 (53)*
      G04*
      G04 Layer_Color=16711935*
      %FSLAX25Y25*%
      %MOIN*%
      G70*
      G04*
      G04 #@! TF.SameCoordinates,A1AE4060-B53B-4171-95B2-E8D2D30D7E40*
      G04*
      G04*
      G04 #@! TF.FilePolarity,Positive*
      G04*
      G01*
      G75*
      %ADD411C,0.05000*%
      D411*
      X23622Y349606D02*
      G03*
      X15748Y357480I-7874J0D01*
      G01*
      Y115551D02*
      G03*
      X23622Y123425I0J7874D01*
      G01*
      X188583Y311220D02*
      G03*
      X184646Y315157I-3937J0D01*
      G01*
      Y162008D02*
      G03*
      X188583Y165945I0J3937D01*
      G01*
      X0Y115551D02*
      X0Y-0D01*
      X0Y357480D02*
      Y393701D01*
      X0Y357480D02*
      X15748D01*
      X0Y115551D02*
      X15748D01*
      X23622Y332086D02*
      Y349606D01*
      Y332086D02*
      X40551Y315157D01*
      X188583Y165945D02*
      Y311220D01*
      X40453Y315157D02*
      X184646Y315157D01*
      X40551Y162008D02*
      X184646D01*
      X23622Y145079D02*
      X40551Y162008D01*
      X23622Y123425D02*
      Y145079D01*
      X0Y-0D02*
      X858421D01*
      X866294Y7873D01*
      X858421Y393701D02*
      X866294Y385828D01*
      Y7873D02*
      Y385828D01*
      X0Y393701D02*
      X858421D01*
      M02*
      hw/manufacturing/DIOT_System_Board_Gerber/DIOT_System_Board.RUL deleted 100644 → 0
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      DRC Rules Export File for PCB: C:\Users\PS\Documents\CTI\DIOT\OHWR_repo\diot-sb-zu\hw\pcb\DIOT_System_Board.PcbDoc
      RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion_IRPS|Scope=Board|Minimum=-0.43
      RuleKind=Clearance|RuleName=Clearance_copper_balance|Scope=Board|Minimum=9.84
      RuleKind=Clearance|RuleName=Clearance_HS|Scope=Board|Minimum=3.15
      RuleKind=Clearance|RuleName=Clearance_NPTH|Scope=Board|Minimum=27.56
      RuleKind=Clearance|RuleName=Clearance_poly_diff|Scope=Board|Minimum=19.69
      RuleKind=Clearance|RuleName=Clearance_SE50|Scope=Board|Minimum=23.62
      RuleKind=Clearance|RuleName=Clearance_DDR|Scope=Board|Minimum=39.37
      RuleKind=Width|RuleName=Width_SE40|Scope=Board|Minimum=4.72
      RuleKind=Width|RuleName=Width_NAND Flash|Scope=Board|Minimum=3.15
      RuleKind=Clearance|RuleName=Clearance_Poly|Scope=Board|Minimum=10.00
      RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
      RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=0.00
      RuleKind=Width|RuleName=Width_SE50|Scope=Board|Minimum=2.97
      RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=3.15
      RuleKind=MinimumAnnularRing|RuleName=MinimumAnnularRing_Via|Scope=Board|Minimum=3.94
      RuleKind=ShortCircuit|RuleName=ShortCircuit_NT|Scope=Board|Allowed=1
      RuleKind=Clearance|RuleName=Clearance_NT|Scope=Board|Minimum=0.00
      RuleKind=MinimumAnnularRing|RuleName=MinimumAnnularRing|Scope=Board|Minimum=7.80
      hw/manufacturing/DIOT_System_Board_NC Drill/DIOT_System_Board-SlotHoles.TXT deleted 100644 → 0
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      M48
      ;Layer_Color=9474304
      ;FILE_FORMAT=4:4
      METRIC,LZ
      ;TYPE=PLATED
      T3F00S00C0.3500
      ;TYPE=NON_PLATED
      %
      G90
      G05
      T03
      G00X002075Y0005005
      M15
      G01Y0004355
      M16
      G00X00279Y0005005
      M15
      G01Y0004355
      M16
      M17
      M30
      hw/manufacturing/DIOT_System_Board_NC Drill/DIOT_System_Board.LDP deleted 100644 → 0
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      Layer Pairs Export File for PCB: C:\Users\PS\Documents\CTI\DIOT\OHWR_repo\diot-sb-zu\hw\pcb\DIOT_System_Board.PcbDoc
      LayersSetName=Top_Bot_Thru_Holes|DrillFile=diot_system_board-roundholes.txt|DrillLayers=gtl,gp1,g1,gp2,g2,gp3,g3,g4,gp4,g5,gp5,g6,gp6,gbl
      LayersSetName=Top_Bot_Slot_Holes|DrillFile=diot_system_board-slotholes.txt|DrillLayers=gtl,gp1,g1,gp2,g2,gp3,g3,g4,gp4,g5,gp5,g6,gp6,gbl
      LayersSetName=L3_Bot_Blind_Vias|DrillFile=diot_system_board-roundholes.tx5|DrillLayers=g1,gp2,g2,gp3,g3,g4,gp4,g5,gp5,g6,gp6,gbl
      LayersSetName=L5_Bot_Blind_Vias|DrillFile=diot_system_board-roundholes.tx6|DrillLayers=g2,gp3,g3,g4,gp4,g5,gp5,g6,gp6,gbl
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