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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit 6d97cb8a authored by Alén Arias Vázquez's avatar Alén Arias Vázquez 😎
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Merge branch 'gw_add_gbit_links' into 'master' 

GW: add Chip2Chip/Aurora link subsystem to all peripheral boards

See merge request !2
parents a292404f 849d80e0
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      gw/common-ip/fpga_device/src/dna_reader.v
      View file @ 6d97cb8a
      ......@@ -49,7 +49,7 @@ module dna_reader # (
      wire s_data;
      //! FSM
      always @(posedge clk_i, negedge rst_n_i)
      always @(posedge clk_i)
      begin : p_fsm
      if(! rst_n_i) begin
      s_read <= 1'b0;
      ......@@ -108,7 +108,7 @@ module dna_reader # (
      end : p_fsm
      //! Shift Register
      always @(posedge clk_i, negedge rst_n_i)
      always @(posedge clk_i)
      begin : p_shift
      if (! rst_n_i)
      s_dna <= 'h0;
      ......
      gw/common-ip/fpga_device/src/fpga_device.v
      View file @ 6d97cb8a
      ......@@ -123,7 +123,7 @@ module fpga_device # (
      //--------------------------------------------------------------------------
      //! ARREADY LOGIC & ARADDR Latch
      always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
      always @(posedge S_AXI_ACLK)
      begin : p_arready
      if (! S_AXI_ARESETN) begin
      s_araddr <= 'h0;
      ......@@ -144,7 +144,7 @@ module fpga_device # (
      assign S_AXI_ARREADY = s_arready;
      //! RVALID
      always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
      always @(posedge S_AXI_ACLK)
      begin : p_rvalid
      if (! S_AXI_ARESETN)
      s_rvalid <= 1'b0;
      ......@@ -161,7 +161,7 @@ module fpga_device # (
      assign s_REN = ~(s_rvalid) & s_arready & S_AXI_ARVALID;
      //! Register Access
      always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
      always @(posedge S_AXI_ACLK)
      begin : p_read
      if (! S_AXI_ARESETN)
      s_RDATA <= 'h0;
      ......
      gw/projects/diot_v2/constraints/diot_v2.xdc
      View file @ 6d97cb8a
      ......@@ -5,9 +5,11 @@
      # ##############################################################################
      # ------------------------------------------------------------------------------
      # GT REG CLK: 125 MHz
      # GT REF CLK: 125 MHz
      set_property PACKAGE_PIN AH10 [get_ports {gtrefclk_in_clk_p}]
      create_clock -period 8.000 -name gt_ref_clk -waveform {0.000 4.000} [get_ports {gtrefclk_in_clk_p}]
      set_property PACKAGE_PIN AA12 [get_ports {aurora_refclk_p}]
      create_clock -period 8.000 -name aurora_ref_clk [get_ports {aurora_refclk_p}]
      # ------------------------------------------------------------------------------
      # Clock Selector
      ......@@ -62,7 +64,7 @@ set_property PACKAGE_PIN AJ8 [get_ports sfp_txp]
      set_property PACKAGE_PIN AJ7 [get_ports sfp_txn]
      # ------------------------------------------------------------------------------
      # Backplain
      # Backplane
      set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[0]}]
      set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[1]}]
      set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[2]}]
      ......@@ -72,3 +74,14 @@ set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports
      set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[6]}]
      set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[7]}]
      set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports {bckpl_rst_n_o}]
      # ------------------------------------------------------------------------------
      # Aurora GTX pins are defined in the block desing IP GUI
      # Overwriting them here will only generate placement conflicts
      # ------------------------------------------------------------------------------
      # Timing ignore for quasi-static status signals
      set_false_path -from [get_pins diot_v2_i/chip2chip_subsystem/link_*/aurora/*/*/*/CHANNEL_UP_reg/C] \
      -to [get_pins {diot_v2_i/chip2chip_subsystem/c2c_link_ctrl/*/*/rd_data_reg[0]/D}]
      set_false_path -from [get_pins diot_v2_i/chip2chip_subsystem/link_*/aurora/*/*/*/CHANNEL_HARD_ERR_reg/C] \
      -to [get_pins {diot_v2_i/chip2chip_subsystem/c2c_link_ctrl/*/*/rd_data_reg[1]/D}]
      gw/projects/diot_v2/src/c2c_link.vhd 0 → 100644
      View file @ 6d97cb8a
      -------------------------------------------------------------------------------
      --! @file c2c_link.vhd
      --! @author Adrian Byszuk
      --! @copyright CERN SY-EPC-CCE
      --! @date 05-07-2022
      --! @brief Chip2Chip link control and status
      -------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      --! @brief Chip2Chip link control and status
      --! @details
      --! Provides software with basic control and diagnostic capabilities.
      --! Intended to be easily integrated with Xilinx Block Design.
      --! Supports up to 8 links, which is maximum in a standard DIOT crate.
      entity c2c_link is
      generic (
      addr_width_g : positive := 6
      );
      port (
      --! @name AXI4Lite slave bus (naming convention compatible with Xilinx IP Integrator)
      s_axi_aclk : in std_ulogic;
      s_axi_aresetn : in std_ulogic;
      --
      s_axi_awvalid : in std_logic;
      s_axi_awready : out std_logic;
      s_axi_awaddr : in std_logic_vector(addr_width_g-1 downto 0);
      --
      s_axi_wvalid : in std_logic;
      s_axi_wready : out std_logic;
      s_axi_wdata : in std_logic_vector(31 downto 0);
      s_axi_wstrb : in std_logic_vector(3 downto 0);
      --
      s_axi_bvalid : out std_logic;
      s_axi_bready : in std_logic;
      s_axi_bresp : out std_logic_vector(1 downto 0);
      --
      s_axi_arvalid : in std_logic;
      s_axi_arready : out std_logic;
      s_axi_araddr : in std_logic_vector(addr_width_g-1 downto 0);
      --
      s_axi_rvalid : out std_logic;
      s_axi_rready : in std_logic;
      s_axi_rdata : out std_logic_vector(31 downto 0);
      s_axi_rresp : out std_logic_vector(1 downto 0);
      --! @name Aurora/Chip2Chip signals (for meaning of some signals see the IP documentation)
      --! Output reset vector is split to avoid stupid block design slicing
      reset_0 : out std_logic; --! PMA reset to link 0
      reset_1 : out std_logic; --! PMA reset to link 1
      reset_2 : out std_logic; --! PMA reset to link 2
      reset_3 : out std_logic; --! PMA reset to link 3
      reset_4 : out std_logic; --! PMA reset to link 4
      reset_5 : out std_logic; --! PMA reset to link 5
      reset_6 : out std_logic; --! PMA reset to link 6
      reset_7 : out std_logic; --! PMA reset to link 7
      channel_up : in std_logic_vector(7 downto 0); --! Aurora channel_up status
      hard_err : in std_logic_vector(7 downto 0); --! Aurora hard_err status
      gt_pll_lock : in std_logic_vector(7 downto 0); --! MGT PLL lock status
      link_status : in std_logic_vector(7 downto 0); --! Chip2Chip link up status
      config_error : in std_logic_vector(7 downto 0); --! Chip2Chip endpoint config error
      link_error : in std_logic_vector(7 downto 0); --! Chip2Chip link error
      multi_bit_error : in std_logic_vector(7 downto 0) --! Chip2Chip multi_bit error status
      );
      end entity c2c_link;
      --! RTL implementation of c2c_link
      architecture rtl of c2c_link is
      --! @name Attributes required to silence Vivado BD GUI
      ATTRIBUTE X_INTERFACE_INFO : STRING;
      ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
      ATTRIBUTE X_INTERFACE_INFO OF reset_0: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_0: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF reset_1: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_1: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF reset_2: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_2: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF reset_3: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_3: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF reset_4: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_4: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF reset_5: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_5: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF reset_6: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_6: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF reset_7: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_7: SIGNAL is "POLARITY ACTIVE_HIGH";
      --! @}
      begin
      --! Wishbone registers (autogenerated)
      x_regs : entity work.link_ctrl_regs
      port map (
      aclk => s_axi_aclk,
      areset_n => s_axi_aresetn,
      awvalid => s_axi_awvalid,
      awready => s_axi_awready,
      awaddr => s_axi_awaddr,
      awprot => "000",
      wvalid => s_axi_wvalid,
      wready => s_axi_wready,
      wdata => s_axi_wdata,
      wstrb => s_axi_wstrb,
      bvalid => s_axi_bvalid,
      bready => s_axi_bready,
      bresp => s_axi_bresp,
      arvalid => s_axi_arvalid,
      arready => s_axi_arready,
      araddr => s_axi_araddr,
      arprot => "000",
      rvalid => s_axi_rvalid,
      rready => s_axi_rready,
      rdata => s_axi_rdata,
      rresp => s_axi_rresp,
      link_0_ctrl_reset_o => reset_0,
      link_0_status_channel_up_i => channel_up(0),
      link_0_status_hard_err_i => hard_err(0),
      link_0_status_gt_pll_lock_i => gt_pll_lock(0),
      link_0_status_link_status_i => link_status(0),
      link_0_status_config_error_i => config_error(0),
      link_0_status_link_error_i => link_error(0),
      link_0_status_multi_bit_error_i => multi_bit_error(0),
      link_1_ctrl_reset_o => reset_1,
      link_1_status_channel_up_i => channel_up(1),
      link_1_status_hard_err_i => hard_err(1),
      link_1_status_gt_pll_lock_i => gt_pll_lock(1),
      link_1_status_link_status_i => link_status(1),
      link_1_status_config_error_i => config_error(1),
      link_1_status_link_error_i => link_error(1),
      link_1_status_multi_bit_error_i => multi_bit_error(1),
      link_2_ctrl_reset_o => reset_2,
      link_2_status_channel_up_i => channel_up(2),
      link_2_status_hard_err_i => hard_err(2),
      link_2_status_gt_pll_lock_i => gt_pll_lock(2),
      link_2_status_link_status_i => link_status(2),
      link_2_status_config_error_i => config_error(2),
      link_2_status_link_error_i => link_error(2),
      link_2_status_multi_bit_error_i => multi_bit_error(2),
      link_3_ctrl_reset_o => reset_3,
      link_3_status_channel_up_i => channel_up(3),
      link_3_status_hard_err_i => hard_err(3),
      link_3_status_gt_pll_lock_i => gt_pll_lock(3),
      link_3_status_link_status_i => link_status(3),
      link_3_status_config_error_i => config_error(3),
      link_3_status_link_error_i => link_error(3),
      link_3_status_multi_bit_error_i => multi_bit_error(3),
      link_4_ctrl_reset_o => reset_4,
      link_4_status_channel_up_i => channel_up(4),
      link_4_status_hard_err_i => hard_err(4),
      link_4_status_gt_pll_lock_i => gt_pll_lock(4),
      link_4_status_link_status_i => link_status(4),
      link_4_status_config_error_i => config_error(4),
      link_4_status_link_error_i => link_error(4),
      link_4_status_multi_bit_error_i => multi_bit_error(4),
      link_5_ctrl_reset_o => reset_5,
      link_5_status_channel_up_i => channel_up(5),
      link_5_status_hard_err_i => hard_err(5),
      link_5_status_gt_pll_lock_i => gt_pll_lock(5),
      link_5_status_link_status_i => link_status(5),
      link_5_status_config_error_i => config_error(5),
      link_5_status_link_error_i => link_error(5),
      link_5_status_multi_bit_error_i => multi_bit_error(5),
      link_6_ctrl_reset_o => reset_6,
      link_6_status_channel_up_i => channel_up(6),
      link_6_status_hard_err_i => hard_err(6),
      link_6_status_gt_pll_lock_i => gt_pll_lock(6),
      link_6_status_link_status_i => link_status(6),
      link_6_status_config_error_i => config_error(6),
      link_6_status_link_error_i => link_error(6),
      link_6_status_multi_bit_error_i => multi_bit_error(6),
      link_7_ctrl_reset_o => reset_7,
      link_7_status_channel_up_i => channel_up(7),
      link_7_status_hard_err_i => hard_err(7),
      link_7_status_gt_pll_lock_i => gt_pll_lock(7),
      link_7_status_link_status_i => link_status(7),
      link_7_status_config_error_i => config_error(7),
      link_7_status_link_error_i => link_error(7),
      link_7_status_multi_bit_error_i => multi_bit_error(7)
      );
      end architecture rtl;
      gw/projects/diot_v2/src/c2c_link_regs.cheby 0 → 100644
      View file @ 6d97cb8a
      memory-map:
      bus: axi4-lite-32
      name: link_ctrl_regs
      description: Aurora link control/status
      x-hdl:
      bus-granularity: byte
      children:
      - repeat:
      name: link
      description: Data to be sent to DAC
      count: 8
      children:
      - reg:
      name: ctrl
      description: Control register
      width: 32
      access: rw
      type: unsigned
      children:
      - field:
      name: reset
      description: Reset the Aurora link
      range: 0
      preset: 0
      x-hdl:
      type: autoclear
      - reg:
      name: status
      description: Status register
      type: unsigned
      width: 32
      access: ro
      children:
      - field:
      name: channel_up
      description: Aurora channel is up and running
      range: 0
      - field:
      name: hard_err
      description: Aurora hard error - reset required
      range: 1
      - field:
      name: gt_pll_lock
      description: MGT PLL is locked
      range: 2
      - field:
      name: link_status
      description: Chip2Chip link is up and running
      range: 3
      - field:
      name: config_error
      description: Chip2Chip config error (see Xilinx PG067)
      range: 4
      - field:
      name: link_error
      description: Chip2Chip link error (see Xilinx PG067)
      range: 5
      - field:
      name: multi_bit_error
      description: Chip2Chip multi-bit error (see Xilinx PG067)
      range: 6
      gw/projects/diot_v2/src/c2c_link_regs.vhd 0 → 100644
      View file @ 6d97cb8a
      -- Do not edit. Generated by cheby 1.5.dev0 using these options:
      -- --print-simple --gen-hdl=c2c_link_regs.vhd --gen-doc=c2c_link_regs.html -i c2c_link_regs.cheby
      -- Generated on Mon Jul 11 18:17:36 2022 by adrian
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      entity link_ctrl_regs is
      port (
      aclk : in std_logic;
      areset_n : in std_logic;
      awvalid : in std_logic;
      awready : out std_logic;
      awaddr : in std_logic_vector(5 downto 0);
      awprot : in std_logic_vector(2 downto 0);
      wvalid : in std_logic;
      wready : out std_logic;
      wdata : in std_logic_vector(31 downto 0);
      wstrb : in std_logic_vector(3 downto 0);
      bvalid : out std_logic;
      bready : in std_logic;
      bresp : out std_logic_vector(1 downto 0);
      arvalid : in std_logic;
      arready : out std_logic;
      araddr : in std_logic_vector(5 downto 0);
      arprot : in std_logic_vector(2 downto 0);
      rvalid : out std_logic;
      rready : in std_logic;
      rdata : out std_logic_vector(31 downto 0);
      rresp : out std_logic_vector(1 downto 0);
      -- Control register
      -- Reset the Aurora link
      link_0_ctrl_reset_o : out std_logic;
      -- Status register
      -- Aurora channel is up and running
      link_0_status_channel_up_i : in std_logic;
      -- Aurora hard error - reset required
      link_0_status_hard_err_i : in std_logic;
      -- MGT PLL is locked
      link_0_status_gt_pll_lock_i : in std_logic;
      -- Chip2Chip link is up and running
      link_0_status_link_status_i : in std_logic;
      -- Chip2Chip config error (see Xilinx PG067)
      link_0_status_config_error_i : in std_logic;
      -- Chip2Chip link error (see Xilinx PG067)
      link_0_status_link_error_i : in std_logic;
      -- Chip2Chip multi-bit error (see Xilinx PG067)
      link_0_status_multi_bit_error_i : in std_logic;
      -- Control register
      -- Reset the Aurora link
      link_1_ctrl_reset_o : out std_logic;
      -- Status register
      -- Aurora channel is up and running
      link_1_status_channel_up_i : in std_logic;
      -- Aurora hard error - reset required
      link_1_status_hard_err_i : in std_logic;
      -- MGT PLL is locked
      link_1_status_gt_pll_lock_i : in std_logic;
      -- Chip2Chip link is up and running
      link_1_status_link_status_i : in std_logic;
      -- Chip2Chip config error (see Xilinx PG067)
      link_1_status_config_error_i : in std_logic;
      -- Chip2Chip link error (see Xilinx PG067)
      link_1_status_link_error_i : in std_logic;
      -- Chip2Chip multi-bit error (see Xilinx PG067)
      link_1_status_multi_bit_error_i : in std_logic;
      -- Control register
      -- Reset the Aurora link
      link_2_ctrl_reset_o : out std_logic;
      -- Status register
      -- Aurora channel is up and running
      link_2_status_channel_up_i : in std_logic;
      -- Aurora hard error - reset required
      link_2_status_hard_err_i : in std_logic;
      -- MGT PLL is locked
      link_2_status_gt_pll_lock_i : in std_logic;
      -- Chip2Chip link is up and running
      link_2_status_link_status_i : in std_logic;
      -- Chip2Chip config error (see Xilinx PG067)
      link_2_status_config_error_i : in std_logic;
      -- Chip2Chip link error (see Xilinx PG067)
      link_2_status_link_error_i : in std_logic;
      -- Chip2Chip multi-bit error (see Xilinx PG067)
      link_2_status_multi_bit_error_i : in std_logic;
      -- Control register
      -- Reset the Aurora link
      link_3_ctrl_reset_o : out std_logic;
      -- Status register
      -- Aurora channel is up and running
      link_3_status_channel_up_i : in std_logic;
      -- Aurora hard error - reset required
      link_3_status_hard_err_i : in std_logic;
      -- MGT PLL is locked
      link_3_status_gt_pll_lock_i : in std_logic;
      -- Chip2Chip link is up and running
      link_3_status_link_status_i : in std_logic;
      -- Chip2Chip config error (see Xilinx PG067)
      link_3_status_config_error_i : in std_logic;
      -- Chip2Chip link error (see Xilinx PG067)
      link_3_status_link_error_i : in std_logic;
      -- Chip2Chip multi-bit error (see Xilinx PG067)
      link_3_status_multi_bit_error_i : in std_logic;
      -- Control register
      -- Reset the Aurora link
      link_4_ctrl_reset_o : out std_logic;
      -- Status register
      -- Aurora channel is up and running
      link_4_status_channel_up_i : in std_logic;
      -- Aurora hard error - reset required
      link_4_status_hard_err_i : in std_logic;
      -- MGT PLL is locked
      link_4_status_gt_pll_lock_i : in std_logic;
      -- Chip2Chip link is up and running
      link_4_status_link_status_i : in std_logic;
      -- Chip2Chip config error (see Xilinx PG067)
      link_4_status_config_error_i : in std_logic;
      -- Chip2Chip link error (see Xilinx PG067)
      link_4_status_link_error_i : in std_logic;
      -- Chip2Chip multi-bit error (see Xilinx PG067)
      link_4_status_multi_bit_error_i : in std_logic;
      -- Control register
      -- Reset the Aurora link
      link_5_ctrl_reset_o : out std_logic;
      -- Status register
      -- Aurora channel is up and running
      link_5_status_channel_up_i : in std_logic;
      -- Aurora hard error - reset required
      link_5_status_hard_err_i : in std_logic;
      -- MGT PLL is locked
      link_5_status_gt_pll_lock_i : in std_logic;
      -- Chip2Chip link is up and running
      link_5_status_link_status_i : in std_logic;
      -- Chip2Chip config error (see Xilinx PG067)
      link_5_status_config_error_i : in std_logic;
      -- Chip2Chip link error (see Xilinx PG067)
      link_5_status_link_error_i : in std_logic;
      -- Chip2Chip multi-bit error (see Xilinx PG067)
      link_5_status_multi_bit_error_i : in std_logic;
      -- Control register
      -- Reset the Aurora link
      link_6_ctrl_reset_o : out std_logic;
      -- Status register
      -- Aurora channel is up and running
      link_6_status_channel_up_i : in std_logic;
      -- Aurora hard error - reset required
      link_6_status_hard_err_i : in std_logic;
      -- MGT PLL is locked
      link_6_status_gt_pll_lock_i : in std_logic;
      -- Chip2Chip link is up and running
      link_6_status_link_status_i : in std_logic;
      -- Chip2Chip config error (see Xilinx PG067)
      link_6_status_config_error_i : in std_logic;
      -- Chip2Chip link error (see Xilinx PG067)
      link_6_status_link_error_i : in std_logic;
      -- Chip2Chip multi-bit error (see Xilinx PG067)
      link_6_status_multi_bit_error_i : in std_logic;
      -- Control register
      -- Reset the Aurora link
      link_7_ctrl_reset_o : out std_logic;
      -- Status register
      -- Aurora channel is up and running
      link_7_status_channel_up_i : in std_logic;
      -- Aurora hard error - reset required
      link_7_status_hard_err_i : in std_logic;
      -- MGT PLL is locked
      link_7_status_gt_pll_lock_i : in std_logic;
      -- Chip2Chip link is up and running
      link_7_status_link_status_i : in std_logic;
      -- Chip2Chip config error (see Xilinx PG067)
      link_7_status_config_error_i : in std_logic;
      -- Chip2Chip link error (see Xilinx PG067)
      link_7_status_link_error_i : in std_logic;
      -- Chip2Chip multi-bit error (see Xilinx PG067)
      link_7_status_multi_bit_error_i : in std_logic
      );
      end link_ctrl_regs;
      architecture syn of link_ctrl_regs is
      signal wr_req : std_logic;
      signal wr_ack : std_logic;
      signal wr_addr : std_logic_vector(5 downto 2);
      signal wr_data : std_logic_vector(31 downto 0);
      signal axi_awset : std_logic;
      signal axi_wset : std_logic;
      signal axi_wdone : std_logic;
      signal rd_req : std_logic;
      signal rd_ack : std_logic;
      signal rd_addr : std_logic_vector(5 downto 2);
      signal rd_data : std_logic_vector(31 downto 0);
      signal axi_arset : std_logic;
      signal axi_rdone : std_logic;
      signal link_0_ctrl_reset_reg : std_logic;
      signal link_0_ctrl_wreq : std_logic;
      signal link_0_ctrl_wack : std_logic;
      signal link_1_ctrl_reset_reg : std_logic;
      signal link_1_ctrl_wreq : std_logic;
      signal link_1_ctrl_wack : std_logic;
      signal link_2_ctrl_reset_reg : std_logic;
      signal link_2_ctrl_wreq : std_logic;
      signal link_2_ctrl_wack : std_logic;
      signal link_3_ctrl_reset_reg : std_logic;
      signal link_3_ctrl_wreq : std_logic;
      signal link_3_ctrl_wack : std_logic;
      signal link_4_ctrl_reset_reg : std_logic;
      signal link_4_ctrl_wreq : std_logic;
      signal link_4_ctrl_wack : std_logic;
      signal link_5_ctrl_reset_reg : std_logic;
      signal link_5_ctrl_wreq : std_logic;
      signal link_5_ctrl_wack : std_logic;
      signal link_6_ctrl_reset_reg : std_logic;
      signal link_6_ctrl_wreq : std_logic;
      signal link_6_ctrl_wack : std_logic;
      signal link_7_ctrl_reset_reg : std_logic;
      signal link_7_ctrl_wreq : std_logic;
      signal link_7_ctrl_wack : std_logic;
      signal rd_ack_d0 : std_logic;
      signal rd_dat_d0 : std_logic_vector(31 downto 0);
      signal wr_req_d0 : std_logic;
      signal wr_adr_d0 : std_logic_vector(5 downto 2);
      signal wr_dat_d0 : std_logic_vector(31 downto 0);
      begin
      -- AW, W and B channels
      awready <= not axi_awset;
      wready <= not axi_wset;
      bvalid <= axi_wdone;
      process (aclk) begin
      if rising_edge(aclk) then
      if areset_n = '0' then
      wr_req <= '0';
      axi_awset <= '0';
      axi_wset <= '0';
      axi_wdone <= '0';
      else
      wr_req <= '0';
      if awvalid = '1' and axi_awset = '0' then
      wr_addr <= awaddr(5 downto 2);
      axi_awset <= '1';
      wr_req <= axi_wset;
      end if;
      if wvalid = '1' and axi_wset = '0' then
      wr_data <= wdata;
      axi_wset <= '1';
      wr_req <= axi_awset or awvalid;
      end if;
      if (axi_wdone and bready) = '1' then
      axi_wset <= '0';
      axi_awset <= '0';
      axi_wdone <= '0';
      end if;
      if wr_ack = '1' then
      axi_wdone <= '1';
      end if;
      end if;
      end if;
      end process;
      bresp <= "00";
      -- AR and R channels
      arready <= not axi_arset;
      rvalid <= axi_rdone;
      process (aclk) begin
      if rising_edge(aclk) then
      if areset_n = '0' then
      rd_req <= '0';
      axi_arset <= '0';
      axi_rdone <= '0';
      rdata <= (others => '0');
      else
      rd_req <= '0';
      if arvalid = '1' and axi_arset = '0' then
      rd_addr <= araddr(5 downto 2);
      axi_arset <= '1';
      rd_req <= '1';
      end if;
      if (axi_rdone and rready) = '1' then
      axi_arset <= '0';
      axi_rdone <= '0';
      end if;
      if rd_ack = '1' then
      axi_rdone <= '1';
      rdata <= rd_data;
      end if;
      end if;
      end if;
      end process;
      rresp <= "00";
      -- pipelining for wr-in+rd-out
      process (aclk) begin
      if rising_edge(aclk) then
      if areset_n = '0' then
      rd_ack <= '0';
      wr_req_d0 <= '0';
      else
      rd_ack <= rd_ack_d0;
      rd_data <= rd_dat_d0;
      wr_req_d0 <= wr_req;
      wr_adr_d0 <= wr_addr;
      wr_dat_d0 <= wr_data;
      end if;
      end if;
      end process;
      -- Register link_0_ctrl
      link_0_ctrl_reset_o <= link_0_ctrl_reset_reg;
      process (aclk) begin
      if rising_edge(aclk) then
      if areset_n = '0' then
      link_0_ctrl_reset_reg <= '0';
      link_0_ctrl_wack <= '0';
      else
      if link_0_ctrl_wreq = '1' then
      link_0_ctrl_reset_reg <= wr_dat_d0(0);
      else
      link_0_ctrl_reset_reg <= '0';
      end if;
      link_0_ctrl_wack <= link_0_ctrl_wreq;
      end if;
      end if;
      end process;
      -- Register link_0_status
      -- Register link_1_ctrl
      link_1_ctrl_reset_o <= link_1_ctrl_reset_reg;
      process (aclk) begin
      if rising_edge(aclk) then
      if areset_n = '0' then
      link_1_ctrl_reset_reg <= '0';
      link_1_ctrl_wack <= '0';
      else
      if link_1_ctrl_wreq = '1' then
      link_1_ctrl_reset_reg <= wr_dat_d0(0);
      else
      link_1_ctrl_reset_reg <= '0';
      end if;
      link_1_ctrl_wack <= link_1_ctrl_wreq;
      end if;
      end if;
      end process;
      -- Register link_1_status
      -- Register link_2_ctrl
      link_2_ctrl_reset_o <= link_2_ctrl_reset_reg;
      process (aclk) begin
      if rising_edge(aclk) then
      if areset_n = '0' then
      link_2_ctrl_reset_reg <= '0';
      link_2_ctrl_wack <= '0';
      else
      if link_2_ctrl_wreq = '1' then
      link_2_ctrl_reset_reg <= wr_dat_d0(0);
      else
      link_2_ctrl_reset_reg <= '0';
      end if;
      link_2_ctrl_wack <= link_2_ctrl_wreq;
      end if;
      end if;
      end process;
      -- Register link_2_status
      -- Register link_3_ctrl
      link_3_ctrl_reset_o <= link_3_ctrl_reset_reg;
      process (aclk) begin
      if rising_edge(aclk) then
      if areset_n = '0' then
      link_3_ctrl_reset_reg <= '0';
      link_3_ctrl_wack <= '0';
      else
      if link_3_ctrl_wreq = '1' then
      link_3_ctrl_reset_reg <= wr_dat_d0(0);
      else
      link_3_ctrl_reset_reg <= '0';
      end if;
      link_3_ctrl_wack <= link_3_ctrl_wreq;
      end if;
      end if;
      end process;
      -- Register link_3_status
      -- Register link_4_ctrl
      link_4_ctrl_reset_o <= link_4_ctrl_reset_reg;
      process (aclk) begin
      if rising_edge(aclk) then
      if areset_n = '0' then
      link_4_ctrl_reset_reg <= '0';
      link_4_ctrl_wack <= '0';
      else
      if link_4_ctrl_wreq = '1' then
      link_4_ctrl_reset_reg <= wr_dat_d0(0);
      else
      link_4_ctrl_reset_reg <= '0';
      end if;
      link_4_ctrl_wack <= link_4_ctrl_wreq;
      end if;
      end if;
      end process;
      -- Register link_4_status
      -- Register link_5_ctrl
      link_5_ctrl_reset_o <= link_5_ctrl_reset_reg;
      process (aclk) begin
      if rising_edge(aclk) then
      if areset_n = '0' then
      link_5_ctrl_reset_reg <= '0';
      link_5_ctrl_wack <= '0';
      else
      if link_5_ctrl_wreq = '1' then
      link_5_ctrl_reset_reg <= wr_dat_d0(0);
      else
      link_5_ctrl_reset_reg <= '0';
      end if;
      link_5_ctrl_wack <= link_5_ctrl_wreq;
      end if;
      end if;
      end process;
      -- Register link_5_status
      -- Register link_6_ctrl
      link_6_ctrl_reset_o <= link_6_ctrl_reset_reg;
      process (aclk) begin
      if rising_edge(aclk) then
      if areset_n = '0' then
      link_6_ctrl_reset_reg <= '0';
      link_6_ctrl_wack <= '0';
      else
      if link_6_ctrl_wreq = '1' then
      link_6_ctrl_reset_reg <= wr_dat_d0(0);
      else
      link_6_ctrl_reset_reg <= '0';
      end if;
      link_6_ctrl_wack <= link_6_ctrl_wreq;
      end if;
      end if;
      end process;
      -- Register link_6_status
      -- Register link_7_ctrl
      link_7_ctrl_reset_o <= link_7_ctrl_reset_reg;
      process (aclk) begin
      if rising_edge(aclk) then
      if areset_n = '0' then
      link_7_ctrl_reset_reg <= '0';
      link_7_ctrl_wack <= '0';
      else
      if link_7_ctrl_wreq = '1' then
      link_7_ctrl_reset_reg <= wr_dat_d0(0);
      else
      link_7_ctrl_reset_reg <= '0';
      end if;
      link_7_ctrl_wack <= link_7_ctrl_wreq;
      end if;
      end if;
      end process;
      -- Register link_7_status
      -- Process for write requests.
      process (wr_adr_d0, wr_req_d0, link_0_ctrl_wack, link_1_ctrl_wack, link_2_ctrl_wack, link_3_ctrl_wack, link_4_ctrl_wack, link_5_ctrl_wack, link_6_ctrl_wack, link_7_ctrl_wack) begin
      link_0_ctrl_wreq <= '0';
      link_1_ctrl_wreq <= '0';
      link_2_ctrl_wreq <= '0';
      link_3_ctrl_wreq <= '0';
      link_4_ctrl_wreq <= '0';
      link_5_ctrl_wreq <= '0';
      link_6_ctrl_wreq <= '0';
      link_7_ctrl_wreq <= '0';
      case wr_adr_d0(5 downto 2) is
      when "0000" =>
      -- Reg link_0_ctrl
      link_0_ctrl_wreq <= wr_req_d0;
      wr_ack <= link_0_ctrl_wack;
      when "0001" =>
      -- Reg link_0_status
      wr_ack <= wr_req_d0;
      when "0010" =>
      -- Reg link_1_ctrl
      link_1_ctrl_wreq <= wr_req_d0;
      wr_ack <= link_1_ctrl_wack;
      when "0011" =>
      -- Reg link_1_status
      wr_ack <= wr_req_d0;
      when "0100" =>
      -- Reg link_2_ctrl
      link_2_ctrl_wreq <= wr_req_d0;
      wr_ack <= link_2_ctrl_wack;
      when "0101" =>
      -- Reg link_2_status
      wr_ack <= wr_req_d0;
      when "0110" =>
      -- Reg link_3_ctrl
      link_3_ctrl_wreq <= wr_req_d0;
      wr_ack <= link_3_ctrl_wack;
      when "0111" =>
      -- Reg link_3_status
      wr_ack <= wr_req_d0;
      when "1000" =>
      -- Reg link_4_ctrl
      link_4_ctrl_wreq <= wr_req_d0;
      wr_ack <= link_4_ctrl_wack;
      when "1001" =>
      -- Reg link_4_status
      wr_ack <= wr_req_d0;
      when "1010" =>
      -- Reg link_5_ctrl
      link_5_ctrl_wreq <= wr_req_d0;
      wr_ack <= link_5_ctrl_wack;
      when "1011" =>
      -- Reg link_5_status
      wr_ack <= wr_req_d0;
      when "1100" =>
      -- Reg link_6_ctrl
      link_6_ctrl_wreq <= wr_req_d0;
      wr_ack <= link_6_ctrl_wack;
      when "1101" =>
      -- Reg link_6_status
      wr_ack <= wr_req_d0;
      when "1110" =>
      -- Reg link_7_ctrl
      link_7_ctrl_wreq <= wr_req_d0;
      wr_ack <= link_7_ctrl_wack;
      when "1111" =>
      -- Reg link_7_status
      wr_ack <= wr_req_d0;
      when others =>
      wr_ack <= wr_req_d0;
      end case;
      end process;
      -- Process for read requests.
      process (rd_addr, rd_req, link_0_status_channel_up_i, link_0_status_hard_err_i, link_0_status_gt_pll_lock_i, link_0_status_link_status_i, link_0_status_config_error_i, link_0_status_link_error_i, link_0_status_multi_bit_error_i, link_1_status_channel_up_i, link_1_status_hard_err_i, link_1_status_gt_pll_lock_i, link_1_status_link_status_i, link_1_status_config_error_i, link_1_status_link_error_i, link_1_status_multi_bit_error_i, link_2_status_channel_up_i, link_2_status_hard_err_i, link_2_status_gt_pll_lock_i, link_2_status_link_status_i, link_2_status_config_error_i, link_2_status_link_error_i, link_2_status_multi_bit_error_i, link_3_status_channel_up_i, link_3_status_hard_err_i, link_3_status_gt_pll_lock_i, link_3_status_link_status_i, link_3_status_config_error_i, link_3_status_link_error_i, link_3_status_multi_bit_error_i, link_4_status_channel_up_i, link_4_status_hard_err_i, link_4_status_gt_pll_lock_i, link_4_status_link_status_i, link_4_status_config_error_i, link_4_status_link_error_i, link_4_status_multi_bit_error_i, link_5_status_channel_up_i, link_5_status_hard_err_i, link_5_status_gt_pll_lock_i, link_5_status_link_status_i, link_5_status_config_error_i, link_5_status_link_error_i, link_5_status_multi_bit_error_i, link_6_status_channel_up_i, link_6_status_hard_err_i, link_6_status_gt_pll_lock_i, link_6_status_link_status_i, link_6_status_config_error_i, link_6_status_link_error_i, link_6_status_multi_bit_error_i, link_7_status_channel_up_i, link_7_status_hard_err_i, link_7_status_gt_pll_lock_i, link_7_status_link_status_i, link_7_status_config_error_i, link_7_status_link_error_i, link_7_status_multi_bit_error_i) begin
      -- By default ack read requests
      rd_dat_d0 <= (others => 'X');
      case rd_addr(5 downto 2) is
      when "0000" =>
      -- Reg link_0_ctrl
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= '0';
      rd_dat_d0(31 downto 1) <= (others => '0');
      when "0001" =>
      -- Reg link_0_status
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= link_0_status_channel_up_i;
      rd_dat_d0(1) <= link_0_status_hard_err_i;
      rd_dat_d0(2) <= link_0_status_gt_pll_lock_i;
      rd_dat_d0(3) <= link_0_status_link_status_i;
      rd_dat_d0(4) <= link_0_status_config_error_i;
      rd_dat_d0(5) <= link_0_status_link_error_i;
      rd_dat_d0(6) <= link_0_status_multi_bit_error_i;
      rd_dat_d0(31 downto 7) <= (others => '0');
      when "0010" =>
      -- Reg link_1_ctrl
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= '0';
      rd_dat_d0(31 downto 1) <= (others => '0');
      when "0011" =>
      -- Reg link_1_status
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= link_1_status_channel_up_i;
      rd_dat_d0(1) <= link_1_status_hard_err_i;
      rd_dat_d0(2) <= link_1_status_gt_pll_lock_i;
      rd_dat_d0(3) <= link_1_status_link_status_i;
      rd_dat_d0(4) <= link_1_status_config_error_i;
      rd_dat_d0(5) <= link_1_status_link_error_i;
      rd_dat_d0(6) <= link_1_status_multi_bit_error_i;
      rd_dat_d0(31 downto 7) <= (others => '0');
      when "0100" =>
      -- Reg link_2_ctrl
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= '0';
      rd_dat_d0(31 downto 1) <= (others => '0');
      when "0101" =>
      -- Reg link_2_status
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= link_2_status_channel_up_i;
      rd_dat_d0(1) <= link_2_status_hard_err_i;
      rd_dat_d0(2) <= link_2_status_gt_pll_lock_i;
      rd_dat_d0(3) <= link_2_status_link_status_i;
      rd_dat_d0(4) <= link_2_status_config_error_i;
      rd_dat_d0(5) <= link_2_status_link_error_i;
      rd_dat_d0(6) <= link_2_status_multi_bit_error_i;
      rd_dat_d0(31 downto 7) <= (others => '0');
      when "0110" =>
      -- Reg link_3_ctrl
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= '0';
      rd_dat_d0(31 downto 1) <= (others => '0');
      when "0111" =>
      -- Reg link_3_status
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= link_3_status_channel_up_i;
      rd_dat_d0(1) <= link_3_status_hard_err_i;
      rd_dat_d0(2) <= link_3_status_gt_pll_lock_i;
      rd_dat_d0(3) <= link_3_status_link_status_i;
      rd_dat_d0(4) <= link_3_status_config_error_i;
      rd_dat_d0(5) <= link_3_status_link_error_i;
      rd_dat_d0(6) <= link_3_status_multi_bit_error_i;
      rd_dat_d0(31 downto 7) <= (others => '0');
      when "1000" =>
      -- Reg link_4_ctrl
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= '0';
      rd_dat_d0(31 downto 1) <= (others => '0');
      when "1001" =>
      -- Reg link_4_status
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= link_4_status_channel_up_i;
      rd_dat_d0(1) <= link_4_status_hard_err_i;
      rd_dat_d0(2) <= link_4_status_gt_pll_lock_i;
      rd_dat_d0(3) <= link_4_status_link_status_i;
      rd_dat_d0(4) <= link_4_status_config_error_i;
      rd_dat_d0(5) <= link_4_status_link_error_i;
      rd_dat_d0(6) <= link_4_status_multi_bit_error_i;
      rd_dat_d0(31 downto 7) <= (others => '0');
      when "1010" =>
      -- Reg link_5_ctrl
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= '0';
      rd_dat_d0(31 downto 1) <= (others => '0');
      when "1011" =>
      -- Reg link_5_status
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= link_5_status_channel_up_i;
      rd_dat_d0(1) <= link_5_status_hard_err_i;
      rd_dat_d0(2) <= link_5_status_gt_pll_lock_i;
      rd_dat_d0(3) <= link_5_status_link_status_i;
      rd_dat_d0(4) <= link_5_status_config_error_i;
      rd_dat_d0(5) <= link_5_status_link_error_i;
      rd_dat_d0(6) <= link_5_status_multi_bit_error_i;
      rd_dat_d0(31 downto 7) <= (others => '0');
      when "1100" =>
      -- Reg link_6_ctrl
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= '0';
      rd_dat_d0(31 downto 1) <= (others => '0');
      when "1101" =>
      -- Reg link_6_status
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= link_6_status_channel_up_i;
      rd_dat_d0(1) <= link_6_status_hard_err_i;
      rd_dat_d0(2) <= link_6_status_gt_pll_lock_i;
      rd_dat_d0(3) <= link_6_status_link_status_i;
      rd_dat_d0(4) <= link_6_status_config_error_i;
      rd_dat_d0(5) <= link_6_status_link_error_i;
      rd_dat_d0(6) <= link_6_status_multi_bit_error_i;
      rd_dat_d0(31 downto 7) <= (others => '0');
      when "1110" =>
      -- Reg link_7_ctrl
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= '0';
      rd_dat_d0(31 downto 1) <= (others => '0');
      when "1111" =>
      -- Reg link_7_status
      rd_ack_d0 <= rd_req;
      rd_dat_d0(0) <= link_7_status_channel_up_i;
      rd_dat_d0(1) <= link_7_status_hard_err_i;
      rd_dat_d0(2) <= link_7_status_gt_pll_lock_i;
      rd_dat_d0(3) <= link_7_status_link_status_i;
      rd_dat_d0(4) <= link_7_status_config_error_i;
      rd_dat_d0(5) <= link_7_status_link_error_i;
      rd_dat_d0(6) <= link_7_status_multi_bit_error_i;
      rd_dat_d0(31 downto 7) <= (others => '0');
      when others =>
      rd_ack_d0 <= rd_req;
      end case;
      end process;
      end syn;
      gw/projects/diot_v2/src/constants.vhd deleted 100644 → 0
      View file @ a292404f
      ----------------------------------------------------------------------------------
      -- Company:
      -- Engineer:
      --
      -- Create Date: 06/28/2021 04:30:23 PM
      -- Design Name:
      -- Module Name: constants - Behavioral
      -- Project Name:
      -- Target Devices:
      -- Tool Versions:
      -- Description:
      --
      -- Dependencies:
      --
      -- Revision:
      -- Revision 0.01 - File Created
      -- Additional Comments:
      --
      ----------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      --==============================================================================
      --! Entity declaration for constants
      --==============================================================================
      entity constants is
      generic (
      g_phyaddr : integer := 9;
      g_config_vector : integer := 0;
      g_config_valid : integer := 0;
      g_signal_detect : integer := 1
      );
      port (
      pl_clk_i : in std_logic;
      --! Vector indicating status. We need bits 0 and 1 of the vector
      status_vector : in std_logic_vector(15 downto 0);
      --! Management clock, (<= 2.5MHz)
      mdc_i : in std_logic;
      mdc_clk_led : out std_logic;
      --! Reset of the module, coming from PS
      pl_resetn_i : in std_logic;
      reset_o : out std_logic;
      --! Autoneg
      an_config_o : out std_logic;
      an_config_vec_o : out std_logic_vector(15 downto 0);
      tx_disable_o : out std_logic;
      --! EMIO GPIOs
      p_pres_i : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o : out std_logic;
      bckpl_servmod_i : in std_logic_vector(7 downto 0);
      bckpl_servmod_o : out std_logic_vector(7 downto 0);
      bckpl_servmod_t_o : out std_logic_vector(7 downto 0);
      bckpl_rst_n_o : out std_logic;
      psu_alert_i : in std_logic;
      f_rst_i : in std_logic;
      f_rst_o : out std_logic;
      f_rst_t_o : out std_logic;
      ps_emio_o : out std_logic_vector(15 downto 0);
      ps_emio_i : in std_logic_vector(15 downto 0);
      ps_emio_t_i : in std_logic_vector(15 downto 0);
      --! I2C busses
      wrflash_i2c_irq_i : in std_logic;
      bckpl_i2c_irq_i : in std_logic;
      ps_irq_o : out std_logic_vector(1 downto 0);
      --! Constants module
      --! Addr of the PHY device(slave). A constant number
      phyaddr : out std_logic_vector(4 downto 0);
      configuration_vector : out std_logic_vector(4 downto 0);
      configuration_valid : out std_logic_vector(0 downto 0);
      --!'1' (if not connected to an optical module), otherwise, default is '0'
      signal_detect : out std_logic_vector(0 downto 0);
      --! Slices module
      link_status_led : out std_logic;
      link_sync_led : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0)
      );
      end constants;
      --==============================================================================
      --! Architecture declaration
      --==============================================================================
      architecture Behavioral of constants is
      --! Because we want to check if mdc_i<=2.5MHz, cnt must be up to 4096
      signal s_cnt : unsigned(11 downto 0);
      signal s_mdc_led_o : std_logic;
      type t_pwr_state is (IDLE, RST);
      signal pwr_state : t_pwr_state;
      signal ps_emio2_d0 : std_logic;
      signal ps_emio2_p : std_logic;
      --==============================================================================
      --! Architecture begin
      --==============================================================================
      begin
      an_config_o <= '0';
      an_config_vec_o <= x"D801";
      tx_disable_o <= '0';
      phyaddr <= std_logic_vector(to_unsigned(g_phyaddr, phyaddr'length));
      configuration_vector <= std_logic_vector(to_unsigned(g_config_vector, configuration_vector'length));
      configuration_valid <= std_logic_vector(to_unsigned(g_config_valid, configuration_valid'length));
      signal_detect <= std_logic_vector(to_unsigned(g_signal_detect, signal_detect'length));
      reset_o <= '1' when (pl_resetn_i = '0') else '0';
      link_status_led <= status_vector(0);
      link_sync_led <= status_vector(1);
      clk_src_sel_o <= "11";
      p_calc_mdc: process(mdc_i, pl_resetn_i)
      begin
      if (pl_resetn_i = '0') then
      s_cnt <= (others=>'0');
      s_mdc_led_o <= '0';
      elsif (rising_edge(mdc_i)) then
      if (s_cnt = 4096-2) then
      s_cnt <= (others=>'0');
      s_mdc_led_o <= '1';
      else
      s_mdc_led_o <= '0';
      s_cnt <= s_cnt + 1;
      end if;
      end if;
      end process p_calc_mdc;
      mdc_clk_led <= s_mdc_led_o;
      --! EMIO -> PL GPIO
      ps_emio_o(4 downto 0) <= p_pres_i(1 downto 0) & "000";
      ps_emio2_p <= '1' when (ps_emio2_d0 = '0' and ps_emio_i(2) = '1') else '0';
      p_pwr: process(pl_clk_i)
      begin
      if rising_edge(pl_clk_i) then
      ps_emio2_d0 <= ps_emio_i(2);
      if pl_resetn_i = '0' or (ps_emio2_p = '1' and ps_emio_i(1) = '1') then
      pwr_state <= IDLE;
      pwr_cycle_req_o <= '0';
      else
      if pwr_state = IDLE then
      pwr_cycle_req_o <= '0';
      if ps_emio2_p = '1' and ps_emio_i(1) = '0' then
      pwr_state <= RST;
      end if;
      elsif pwr_state = RST then
      pwr_cycle_req_o <= '1';
      end if;
      end if;
      end if;
      end process p_pwr;
      --! EMIO 83..90
      ps_emio_o(12 downto 5) <= bckpl_servmod_i(7 downto 0);
      bckpl_servmod_o(7 downto 0) <= ps_emio_i(12 downto 5);
      bckpl_servmod_t_o(7 downto 0) <= ps_emio_t_i(12 downto 5);
      --! EMIO 91
      ps_emio_o(13) <= ps_emio_i(13);
      bckpl_rst_n_o <= ps_emio_i(13);
      --! EMIO 92
      ps_emio_o(14) <= psu_alert_i;
      --! EMIO 93
      ps_emio_o(15) <= f_rst_i;
      f_rst_o <= ps_emio_i(15);
      f_rst_t_o <= ps_emio_t_i(15);
      --! I2C irqs
      ps_irq_o(1 downto 0) <= bckpl_i2c_irq_i & wrflash_i2c_irq_i;
      end Behavioral;
      --==============================================================================
      -- architecture end
      --==============================================================================
      gw/projects/diot_v2/src/diot_v2_top.vhd
      View file @ 6d97cb8a
      ......@@ -51,7 +51,13 @@ entity diot_v2_top is
      emio_scl_b : inout std_logic;
      emio_sda_b : inout std_logic;
      wrflash_scl_b : inout std_logic;
      wrflash_sda_b : inout std_logic
      wrflash_sda_b : inout std_logic;
      aurora_refclk_p : in std_logic;
      aurora_refclk_n : in std_logic;
      aurora_rx_p : in std_logic_vector(7 downto 0);
      aurora_rx_n : in std_logic_vector(7 downto 0);
      aurora_tx_p : out std_logic_vector(7 downto 0);
      aurora_tx_n : out std_logic_vector(7 downto 0)
      );
      end diot_v2_top;
      ......@@ -62,60 +68,94 @@ architecture structure of diot_v2_top is
      component diot_v2 is
      port (
      f_rst_i : in std_logic;
      f_rst_o : out std_logic;
      f_rst_t : out std_logic;
      psu_alert_i : in std_logic;
      p_pres_i_0 : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o_0 : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0);
      gtrefclk_in_clk_p : in std_logic;
      gtrefclk_in_clk_n : in std_logic;
      pl_reset_led : out std_logic;
      link_status_led : out std_logic;
      link_sync_led : out std_logic;
      mdc_clk_led : out std_logic;
      tx_disable_o : out std_logic;
      sfp_rxp : in std_logic;
      sfp_rxn : in std_logic;
      sfp_txp : out std_logic;
      sfp_txn : out std_logic;
      bckpl_rst_n_o : out std_logic;
      bckpl_servmod_i : in std_logic_vector(7 downto 0);
      bckpl_servmod_o : out std_logic_vector(7 downto 0);
      bckpl_servmod_t : out std_logic_vector(7 downto 0);
      i2c_bckpl_scl_i : in std_logic;
      i2c_bckpl_scl_o : out std_logic;
      i2c_bckpl_scl_t : out std_logic;
      i2c_bckpl_sda_i : in std_logic;
      i2c_bckpl_sda_o : out std_logic;
      i2c_bckpl_sda_t : out std_logic;
      i2c_emio_scl_i : in std_logic;
      i2c_emio_scl_o : out std_logic;
      i2c_emio_scl_t : out std_logic;
      i2c_emio_sda_i : in std_logic;
      i2c_emio_sda_o : out std_logic;
      i2c_emio_sda_t : out std_logic;
      i2c_wrflash_scl_i : in std_logic;
      i2c_wrflash_scl_o : out std_logic;
      i2c_wrflash_scl_t : out std_logic;
      i2c_wrflash_sda_i : in std_logic;
      i2c_wrflash_sda_o : out std_logic;
      i2c_wrflash_sda_t : out std_logic
      f_rst_i : in std_logic;
      f_rst_o : out std_logic;
      f_rst_t : out std_logic;
      psu_alert_i : in std_logic;
      p_pres_i_0 : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o_0 : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0);
      gtrefclk_in_clk_p : in std_logic;
      gtrefclk_in_clk_n : in std_logic;
      pl_reset_led : out std_logic;
      link_status_led : out std_logic;
      link_sync_led : out std_logic;
      mdc_clk_led : out std_logic;
      tx_disable_o : out std_logic;
      sfp_rxp : in std_logic;
      sfp_rxn : in std_logic;
      sfp_txp : out std_logic;
      sfp_txn : out std_logic;
      bckpl_rst_n_o : out std_logic;
      bckpl_servmod_i : in std_logic_vector(7 downto 0);
      bckpl_servmod_o : out std_logic_vector(7 downto 0);
      bckpl_servmod_t : out std_logic_vector(7 downto 0);
      i2c_bckpl_scl_i : in std_logic;
      i2c_bckpl_scl_o : out std_logic;
      i2c_bckpl_scl_t : out std_logic;
      i2c_bckpl_sda_i : in std_logic;
      i2c_bckpl_sda_o : out std_logic;
      i2c_bckpl_sda_t : out std_logic;
      i2c_emio_scl_i : in std_logic;
      i2c_emio_scl_o : out std_logic;
      i2c_emio_scl_t : out std_logic;
      i2c_emio_sda_i : in std_logic;
      i2c_emio_sda_o : out std_logic;
      i2c_emio_sda_t : out std_logic;
      i2c_wrflash_scl_i : in std_logic;
      i2c_wrflash_scl_o : out std_logic;
      i2c_wrflash_scl_t : out std_logic;
      i2c_wrflash_sda_i : in std_logic;
      i2c_wrflash_sda_o : out std_logic;
      i2c_wrflash_sda_t : out std_logic;
      aur_refclk_i_clk_p : in std_logic;
      aur_refclk_i_clk_n : in std_logic;
      aurora_rx_0_rxp : in std_logic;
      aurora_rx_0_rxn : in std_logic;
      aurora_rx_1_rxp : in std_logic;
      aurora_rx_1_rxn : in std_logic;
      aurora_rx_2_rxp : in std_logic;
      aurora_rx_2_rxn : in std_logic;
      aurora_rx_3_rxp : in std_logic;
      aurora_rx_3_rxn : in std_logic;
      aurora_rx_4_rxp : in std_logic;
      aurora_rx_4_rxn : in std_logic;
      aurora_rx_5_rxp : in std_logic;
      aurora_rx_5_rxn : in std_logic;
      aurora_rx_6_rxp : in std_logic;
      aurora_rx_6_rxn : in std_logic;
      aurora_rx_7_rxp : in std_logic;
      aurora_rx_7_rxn : in std_logic;
      aurora_tx_0_txp : out std_logic;
      aurora_tx_0_txn : out std_logic;
      aurora_tx_1_txp : out std_logic;
      aurora_tx_1_txn : out std_logic;
      aurora_tx_2_txp : out std_logic;
      aurora_tx_2_txn : out std_logic;
      aurora_tx_3_txp : out std_logic;
      aurora_tx_3_txn : out std_logic;
      aurora_tx_4_txp : out std_logic;
      aurora_tx_4_txn : out std_logic;
      aurora_tx_5_txp : out std_logic;
      aurora_tx_5_txn : out std_logic;
      aurora_tx_6_txp : out std_logic;
      aurora_tx_6_txn : out std_logic;
      aurora_tx_7_txp : out std_logic;
      aurora_tx_7_txn : out std_logic
      );
      end component diot_v2;
      --! Signals backplane servmod
      --! @name Signals backplane servmod
      signal s_bckpl_servmod_o : std_logic_vector(7 downto 0);
      signal s_bckpl_servmod_i : std_logic_vector(7 downto 0);
      signal s_bckpl_servmod_t : std_logic_vector(7 downto 0);
      --! Signals F RST buffer
      --! @name Signals F RST buffer
      signal s_f_rst_o : std_logic;
      signal s_f_rst_i : std_logic;
      signal s_f_rst_t : std_logic;
      --! Signals I2C WR FLASH
      --! @name Signals I2C WR FLASH
      signal s_wrflash_scl_i : std_logic;
      signal s_wrflash_scl_o : std_logic;
      signal s_wrflash_scl_t : std_logic;
      ......@@ -123,7 +163,7 @@ architecture structure of diot_v2_top is
      signal s_wrflash_sda_o : std_logic;
      signal s_wrflash_sda_t : std_logic;
      --! Signals I2C Backplane
      --! @name Signals I2C Backplane
      signal s_bckpl_scl_i : std_logic;
      signal s_bckpl_scl_o : std_logic;
      signal s_bckpl_scl_t : std_logic;
      ......@@ -131,7 +171,7 @@ architecture structure of diot_v2_top is
      signal s_bckpl_sda_o : std_logic;
      signal s_bckpl_sda_t : std_logic;
      --! Signals I2C EMIO
      --! @name Signals I2C EMIO
      signal s_emio_scl_i : std_logic;
      signal s_emio_scl_o : std_logic;
      signal s_emio_scl_t : std_logic;
      ......@@ -263,7 +303,41 @@ begin
      i2c_wrflash_scl_t => s_wrflash_scl_t,
      i2c_wrflash_sda_i => s_wrflash_sda_i,
      i2c_wrflash_sda_o => s_wrflash_sda_o,
      i2c_wrflash_sda_t => s_wrflash_sda_t
      i2c_wrflash_sda_t => s_wrflash_sda_t,
      aur_refclk_i_clk_p => aurora_refclk_p,
      aur_refclk_i_clk_n => aurora_refclk_n,
      aurora_rx_0_rxp => aurora_rx_p(0),
      aurora_rx_0_rxn => aurora_rx_n(0),
      aurora_rx_1_rxp => aurora_rx_p(1),
      aurora_rx_1_rxn => aurora_rx_n(1),
      aurora_rx_2_rxp => aurora_rx_p(2),
      aurora_rx_2_rxn => aurora_rx_n(2),
      aurora_rx_3_rxp => aurora_rx_p(3),
      aurora_rx_3_rxn => aurora_rx_n(3),
      aurora_rx_4_rxp => aurora_rx_p(4),
      aurora_rx_4_rxn => aurora_rx_n(4),
      aurora_rx_5_rxp => aurora_rx_p(5),
      aurora_rx_5_rxn => aurora_rx_n(5),
      aurora_rx_6_rxp => aurora_rx_p(6),
      aurora_rx_6_rxn => aurora_rx_n(6),
      aurora_rx_7_rxp => aurora_rx_p(7),
      aurora_rx_7_rxn => aurora_rx_n(7),
      aurora_tx_0_txp => aurora_tx_p(0),
      aurora_tx_0_txn => aurora_tx_n(0),
      aurora_tx_1_txp => aurora_tx_p(1),
      aurora_tx_1_txn => aurora_tx_n(1),
      aurora_tx_2_txp => aurora_tx_p(2),
      aurora_tx_2_txn => aurora_tx_n(2),
      aurora_tx_3_txp => aurora_tx_p(3),
      aurora_tx_3_txn => aurora_tx_n(3),
      aurora_tx_4_txp => aurora_tx_p(4),
      aurora_tx_4_txn => aurora_tx_n(4),
      aurora_tx_5_txp => aurora_tx_p(5),
      aurora_tx_5_txn => aurora_tx_n(5),
      aurora_tx_6_txp => aurora_tx_p(6),
      aurora_tx_6_txn => aurora_tx_n(6),
      aurora_tx_7_txp => aurora_tx_p(7),
      aurora_tx_7_txn => aurora_tx_n(7)
      );
      end architecture structure;
      ......
      gw/projects/diot_v2/src/ps2pl_glue.vhd 0 → 100644
      View file @ 6d97cb8a
      -------------------------------------------------------------------------------
      --! @file ps2pl_glue.vhd
      --! @author Adrian Byszuk <adrian.byszuk@cern.ch>
      --! @company CERN
      --! @date 2021-06-28
      --! @brief PS to PL glue logic and hardcoded config
      -------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      --! @brief PS to PL glue logic and hardcoded config signals
      entity ps2pl_glue is
      generic (
      g_phyaddr : natural := 9; --! Ethernet PHY MDIO address
      g_config_vector : natural := 0; --! Ethernet IP configuration vector
      g_config_valid : std_logic_vector := "0"; --! Configuration vector is valid
      g_signal_detect : std_logic_vector := "1" --! SFP signal detected status
      );
      Port (
      --! @name Fundamental clock and reset
      pl_clk_i : in std_logic; --! PL clock
      pl_resetn_i : in std_logic; --! Reset of the module, coming from PS
      reset_o : out std_logic; --! Reset to the PL
      --! @name Ethernet config and status
      --! MAC status. Check Xilinx docs for detailed info
      status_vector_i : in std_logic_vector(15 downto 0);
      mdc_i : in std_logic; --! Management clock, (<= 2.5MHz)
      mdc_clk_led_o : out std_logic; --! MDC activity LED
      an_config_o : out std_logic;
      --! Config data for autonegotiation
      an_config_vec_o : out std_logic_vector(15 downto 0);
      tx_disable_o : out std_logic;
      --! @}
      --! @name EMIO GPIOs
      p_pres_i : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o : out std_logic;
      bckpl_servmod_i : in std_logic_vector(7 downto 0);
      bckpl_servmod_o : out std_logic_vector(7 downto 0);
      bckpl_servmod_t_o : out std_logic_vector(7 downto 0);
      bckpl_rst_n_o : out std_logic;
      psu_alert_i : in std_logic;
      f_rst_i : in std_logic;
      f_rst_o : out std_logic;
      f_rst_t_o : out std_logic;
      ps_emio_o : out std_logic_vector(15 downto 0);
      ps_emio_i : in std_logic_vector(94 downto 0);
      ps_emio_t_i : in std_logic_vector(15 downto 0);
      --! @name I2C bus and other IRQs
      wrflash_i2c_irq_i : in std_logic;
      bckpl_i2c_irq_i : in std_logic;
      aurora_dma_irq_i : in std_logic;
      ps_irq_o : out std_logic_vector(2 downto 0);
      --! @name Constants module
      --! Addr of the PHY device(slave). A constant number
      phyaddr_o : out std_logic_vector(4 downto 0);
      --! PHY IP configuration vector (consult with Xilinx documentation)
      configuration_vector_o : out std_logic_vector(4 downto 0);
      --! Configuration vector is valid
      configuration_valid_o : out std_logic_vector(0 downto 0);
      --! Optical signal detected ('1' if not connected to an optical module)
      signal_detect_o : out std_logic_vector(0 downto 0);
      --! @name Slices module
      link_status_led_o : out std_logic;
      link_sync_led_o : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0)
      );
      end ps2pl_glue;
      architecture Behavioral of ps2pl_glue is
      --! @name Port attributes for Xilinx IP Integrator
      ATTRIBUTE X_INTERFACE_INFO : STRING;
      ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
      ATTRIBUTE X_INTERFACE_INFO OF pl_clk_i: signal IS "xilinx.com:signal:clock:1.0 pl_clk_i CLK";
      ATTRIBUTE X_INTERFACE_PARAMETER of pl_clk_i: SIGNAL is "ASSOCIATED_RESET pl_resetn_i";
      ATTRIBUTE X_INTERFACE_INFO OF pl_resetn_i: SIGNAL IS "xilinx.com:signal:reset:1.0 pl_resetn_i RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of pl_resetn_i: SIGNAL is "POLARITY ACTIVE_LOW";
      ATTRIBUTE X_INTERFACE_INFO OF reset_o: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
      ATTRIBUTE X_INTERFACE_PARAMETER of reset_o: SIGNAL is "POLARITY ACTIVE_HIGH";
      ATTRIBUTE X_INTERFACE_INFO OF mdc_i: signal IS "xilinx.com:signal:clock:1.0 mdc_i CLK";
      ATTRIBUTE X_INTERFACE_INFO of ps_irq_o: SIGNAL is "xilinx.com:signal:interrupt:1.0 ps_irq_o INTERRUPT";
      ATTRIBUTE X_INTERFACE_INFO of wrflash_i2c_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 wrflash_i2c_irq_i INTERRUPT";
      ATTRIBUTE X_INTERFACE_INFO of bckpl_i2c_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 bckpl_i2c_irq_i INTERRUPT";
      ATTRIBUTE X_INTERFACE_INFO of aurora_dma_irq_i: SIGNAL is "xilinx.com:signal:interrupt:1.0 aurora_dma_irq_i INTERRUPT";
      --! @}
      -- Because we want to check if mdc_i<=2.5MHz, cnt must be up to 4096
      signal s_cnt : unsigned(11 downto 0);
      signal s_mdc_led : std_logic;
      type t_pwr_state is (IDLE, RST);
      signal pwr_state : t_pwr_state;
      signal ps_emio2_d0 : std_logic;
      signal ps_emio2_p : std_logic;
      begin
      an_config_o <= '0';
      an_config_vec_o <= x"D801";
      tx_disable_o <= '0';
      phyaddr_o <= std_logic_vector(to_unsigned(g_phyaddr, phyaddr_o'length));
      configuration_vector_o <= std_logic_vector(to_unsigned(g_config_vector, configuration_vector_o'length));
      configuration_valid_o <= g_config_valid;
      signal_detect_o <= g_signal_detect;
      reset_o <= '1' when (pl_resetn_i = '0') else
      '0';
      link_status_led_o <= status_vector_i(0);
      link_sync_led_o <= status_vector_i(1);
      clk_src_sel_o <= "11";
      calc_mdc: process(mdc_i, pl_resetn_i)
      begin
      if (pl_resetn_i = '0') then
      s_cnt <= (others => '0');
      s_mdc_led <= '0';
      elsif (rising_edge(mdc_i)) then
      if (s_cnt = 4096-2) then
      s_cnt <= (others=>'0');
      s_mdc_led <= '1';
      else
      s_mdc_led <= '0';
      s_cnt <= s_cnt + 1;
      end if;
      end if;
      end process;
      mdc_clk_led_o <= s_mdc_led;
      -- EMIO -> PL GPIO
      ps_emio_o(4 downto 0) <= p_pres_i(1 downto 0) & "000";
      ps_emio2_p <= '1' when (ps_emio2_d0 = '0' and ps_emio_i(2) = '1') else
      '0';
      process(pl_clk_i)
      begin
      if rising_edge(pl_clk_i) then
      ps_emio2_d0 <= ps_emio_i(2);
      if pl_resetn_i = '0' or (ps_emio2_p = '1' and ps_emio_i(1) = '1') then
      pwr_state <= IDLE;
      pwr_cycle_req_o <= '0';
      else
      if pwr_state = IDLE then
      pwr_cycle_req_o <= '0';
      if ps_emio2_p = '1' and ps_emio_i(1) = '0' then
      pwr_state <= RST;
      end if;
      elsif pwr_state = RST then
      pwr_cycle_req_o <= '1';
      end if;
      end if;
      end if;
      end process;
      -- EMIO 83..90
      ps_emio_o(12 downto 5) <= bckpl_servmod_i(7 downto 0);
      bckpl_servmod_o(7 downto 0) <= ps_emio_i(12 downto 5);
      bckpl_servmod_t_o(7 downto 0) <= ps_emio_t_i(12 downto 5);
      -- EMIO 91
      ps_emio_o(13) <= ps_emio_i(13);
      bckpl_rst_n_o <= ps_emio_i(13);
      -- EMIO 92
      ps_emio_o(14) <= psu_alert_i;
      -- EMIO 93
      ps_emio_o(15) <= f_rst_i;
      f_rst_o <= ps_emio_i(15);
      f_rst_t_o <= ps_emio_t_i(15);
      -- I2C irqs
      ps_irq_o <= aurora_dma_irq_i & bckpl_i2c_irq_i & wrflash_i2c_irq_i;
      end Behavioral;
      gw/projects/diot_v2/src/run_cheby.sh 0 → 100755
      View file @ 6d97cb8a
      #!/bin/sh
      NAME="c2c_link_regs"
      # commands must be executed from script directory, where both script and .cheby files are
      cd "$(dirname "$(readlink -f "$0")")"
      cheby --print-simple --gen-hdl=$NAME.vhd --gen-doc=$NAME.html -i $NAME.cheby
      gw/projects/diot_v2/tcl/create_bd.tcl
      View file @ 6d97cb8a
      This source diff could not be displayed because it is too large. You can view the blob instead.
      gw/projects/diot_v2/tcl/project_cfg.tcl
      View file @ 6d97cb8a
      ......@@ -4,7 +4,6 @@ set project_name "diot_v2"
      set entity_top "diot_v2_top"
      # Hardcoded to 8 to work fine in CI set max_threads [get_number_cpus]
      set max_threads 8
      set project_language "VHDL"
      set lib_default xil_defaultlib
      # Common IP directory
      ......@@ -19,7 +18,9 @@ set_user_property "xpm_libraries" "XPM_CDC XPM_FIFO XPM_MEMORY"
      add_vhdl_src ${lib_default} ../src/${entity_top}.vhd
      # Vhdl Src
      add_vhdl_src ${lib_default} ../src/constants.vhd
      add_vhdl_src ${lib_default} ../src/ps2pl_glue.vhd
      add_vhdl_src ${lib_default} ../src/c2c_link_regs.vhd
      add_vhdl_src ${lib_default} ../src/c2c_link.vhd
      # Add Constraints
      add_constraint diot_v2.xdc
      gw/projects/diot_v2/tcl/ps_cfg.tcl
      View file @ 6d97cb8a
      ......@@ -622,7 +622,7 @@ MIO} \
      CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
      CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
      CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {DPLL} \
      CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
      CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {0} \
      CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {600} \
      ......@@ -641,20 +641,20 @@ MIO} \
      CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
      CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
      CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {12} \
      CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
      CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {APLL} \
      CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {400.000000} \
      CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.333} \
      CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {VPLL} \
      CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {APLL} \
      CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
      CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {42} \
      CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {60} \
      CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
      CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
      CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
      CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
      CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
      CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
      ......@@ -680,9 +680,9 @@ MIO} \
      CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
      CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
      CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
      CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \
      ......@@ -740,8 +740,8 @@ MIO} \
      CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
      CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
      CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {266.666656} \
      CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {3} \
      CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
      CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {4} \
      CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {267} \
      CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
      ......@@ -766,14 +766,14 @@ MIO} \
      CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
      CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {50.000000} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {16} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {30} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {50} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
      CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {200.000000} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {200} \
      CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
      CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
      ......@@ -791,19 +791,19 @@ MIO} \
      CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {300} \
      CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
      CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
      CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {32} \
      CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {40} \
      CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
      CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
      CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
      CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
      CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
      CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200.000000} \
      CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {4} \
      CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {5} \
      CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
      CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {50.000000} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {16} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {20} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {50} \
      CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {RPLL} \
      ......@@ -1023,7 +1023,7 @@ MIO} \
      CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100} \
      CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
      CONFIG.PSU__FPGA_PL0_ENABLE {1} \
      CONFIG.PSU__FPGA_PL1_ENABLE {0} \
      CONFIG.PSU__FPGA_PL1_ENABLE {1} \
      CONFIG.PSU__FPGA_PL2_ENABLE {0} \
      CONFIG.PSU__FPGA_PL3_ENABLE {0} \
      CONFIG.PSU__FP__POWER__ON {1} \
      ......@@ -1064,7 +1064,7 @@ MIO} \
      CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__GPIO_EMIO_WIDTH {95} \
      CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \
      CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {16} \
      CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {95} \
      CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
      CONFIG.PSU__GPU_PP0__POWER__ON {0} \
      CONFIG.PSU__GPU_PP1__POWER__ON {0} \
      ......@@ -1199,7 +1199,7 @@ MIO} \
      CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \
      CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \
      CONFIG.PSU__MAXIGP0__DATA_WIDTH {32} \
      CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
      CONFIG.PSU__MAXIGP1__DATA_WIDTH {32} \
      CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
      CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
      CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
      ......@@ -1295,7 +1295,7 @@ MIO} \
      CONFIG.PSU__PCIE__VENDOR_ID {} \
      CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__PL_CLK0_BUF {TRUE} \
      CONFIG.PSU__PL_CLK1_BUF {FALSE} \
      CONFIG.PSU__PL_CLK1_BUF {TRUE} \
      CONFIG.PSU__PL_CLK2_BUF {FALSE} \
      CONFIG.PSU__PL_CLK3_BUF {FALSE} \
      CONFIG.PSU__PL__POWER__ON {1} \
      ......@@ -1322,46 +1322,37 @@ MIO} \
      CONFIG.PSU__PROTECTION__DEBUG {0} \
      CONFIG.PSU__PROTECTION__ENABLE {0} \
      CONFIG.PSU__PROTECTION__FPD_SEGMENTS {\
      SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
      subsystemId:PMU Firmware | SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure;\
      WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD010000; SIZE:64;\
      UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
      SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
      subsystemId:PMU Firmware | SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure;\
      WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD040000; SIZE:64;\
      UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
      SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
      subsystemId:PMU Firmware | SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure;\
      WrAllowed:Read/Write; subsystemId:PMU Firmware | SA:0xFD5D0000; SIZE:64;\
      UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware |\
      SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write;\
      subsystemId:Secure Subsystem} \
      SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
      SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
      SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
      SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
      SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
      SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
      SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
      SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
      SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware | \
      SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \
      CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \
      CONFIG.PSU__PROTECTION__LPD_SEGMENTS {\
      SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
      subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure;\
      WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64;\
      UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
      SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
      subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure;\
      WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64;\
      UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
      SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
      subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ;\
      WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64;\
      UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure\
      Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ;\
      WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64;\
      UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \
      SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| \
      SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| \
      SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| \
      SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| \
      SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| \
      SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| \
      SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| \
      SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem| \
      SA:0xFFCC0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem| \
      SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem| \
      SA:0xFF9A0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem} \
      CONFIG.PSU__PROTECTION__MASTERS {\
      USB1:NonSecure;0|USB0:NonSecure;0|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;1|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
      USB1:NonSecure;0|USB0:NonSecure;0|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;1|FDMA:NonSecure;1|DP:NonSecure;0|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
      CONFIG.PSU__PROTECTION__MASTERS_TZ {\
      GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \
      CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
      CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
      CONFIG.PSU__PROTECTION__SLAVES {\
      LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;0|LPD;USB3_0;FF9D0000;FF9DFFFF;0|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;1|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
      Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
      LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;0|LPD;USB3_0;FF9D0000;FF9DFFFF;0|LPD;UART1;FF010000;FF01FFFF;0|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;0|LPD;TTC2;FF130000;FF13FFFF;0|LPD;TTC1;FF120000;FF12FFFF;0|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;0|LPD;SWDT0;FF150000;FF15FFFF;0|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;1|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
      CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \
      CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
      CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
      ......@@ -1379,7 +1370,7 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000
      CONFIG.PSU__SATA__LANE0__ENABLE {0} \
      CONFIG.PSU__SATA__LANE1__ENABLE {0} \
      CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
      CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \
      CONFIG.PSU__SAXIGP0__DATA_WIDTH {32} \
      CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \
      CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \
      CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \
      ......@@ -1494,7 +1485,7 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000
      CONFIG.PSU__USE__IRQ0 {1} \
      CONFIG.PSU__USE__IRQ1 {0} \
      CONFIG.PSU__USE__M_AXI_GP0 {0} \
      CONFIG.PSU__USE__M_AXI_GP1 {0} \
      CONFIG.PSU__USE__M_AXI_GP1 {1} \
      CONFIG.PSU__USE__M_AXI_GP2 {1} \
      CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
      CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
      ......@@ -1506,7 +1497,7 @@ Port;FD4A0000;FD4AFFFF;0|FPD;DPDMA;FD4C0000;FD4CFFFF;0|FPD;DDR_XMPU5_CFG;FD05000
      CONFIG.PSU__USE__STM {0} \
      CONFIG.PSU__USE__S_AXI_ACE {0} \
      CONFIG.PSU__USE__S_AXI_ACP {0} \
      CONFIG.PSU__USE__S_AXI_GP0 {0} \
      CONFIG.PSU__USE__S_AXI_GP0 {1} \
      CONFIG.PSU__USE__S_AXI_GP1 {0} \
      CONFIG.PSU__USE__S_AXI_GP2 {0} \
      CONFIG.PSU__USE__S_AXI_GP3 {0} \
      ......
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