Commit 6d97cb8a authored by Alén Arias Vázquez's avatar Alén Arias Vázquez 😎

Merge branch 'gw_add_gbit_links' into 'master'

GW: add Chip2Chip/Aurora link subsystem to all peripheral boards

See merge request !2
parents a292404f 849d80e0
Pipeline #4058 passed with stages
in 92 minutes and 33 seconds
......@@ -49,7 +49,7 @@ module dna_reader # (
wire s_data;
//! FSM
always @(posedge clk_i, negedge rst_n_i)
always @(posedge clk_i)
begin : p_fsm
if(! rst_n_i) begin
s_read <= 1'b0;
......@@ -108,7 +108,7 @@ module dna_reader # (
end : p_fsm
//! Shift Register
always @(posedge clk_i, negedge rst_n_i)
always @(posedge clk_i)
begin : p_shift
if (! rst_n_i)
s_dna <= 'h0;
......
......@@ -123,7 +123,7 @@ module fpga_device # (
//--------------------------------------------------------------------------
//! ARREADY LOGIC & ARADDR Latch
always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
always @(posedge S_AXI_ACLK)
begin : p_arready
if (! S_AXI_ARESETN) begin
s_araddr <= 'h0;
......@@ -144,7 +144,7 @@ module fpga_device # (
assign S_AXI_ARREADY = s_arready;
//! RVALID
always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
always @(posedge S_AXI_ACLK)
begin : p_rvalid
if (! S_AXI_ARESETN)
s_rvalid <= 1'b0;
......@@ -161,7 +161,7 @@ module fpga_device # (
assign s_REN = ~(s_rvalid) & s_arready & S_AXI_ARVALID;
//! Register Access
always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
always @(posedge S_AXI_ACLK)
begin : p_read
if (! S_AXI_ARESETN)
s_RDATA <= 'h0;
......
......@@ -5,9 +5,11 @@
# ##############################################################################
# ------------------------------------------------------------------------------
# GT REG CLK: 125 MHz
# GT REF CLK: 125 MHz
set_property PACKAGE_PIN AH10 [get_ports {gtrefclk_in_clk_p}]
create_clock -period 8.000 -name gt_ref_clk -waveform {0.000 4.000} [get_ports {gtrefclk_in_clk_p}]
set_property PACKAGE_PIN AA12 [get_ports {aurora_refclk_p}]
create_clock -period 8.000 -name aurora_ref_clk [get_ports {aurora_refclk_p}]
# ------------------------------------------------------------------------------
# Clock Selector
......@@ -62,7 +64,7 @@ set_property PACKAGE_PIN AJ8 [get_ports sfp_txp]
set_property PACKAGE_PIN AJ7 [get_ports sfp_txn]
# ------------------------------------------------------------------------------
# Backplain
# Backplane
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[0]}]
set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[1]}]
set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[2]}]
......@@ -72,3 +74,14 @@ set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports
set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[6]}]
set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[7]}]
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports {bckpl_rst_n_o}]
# ------------------------------------------------------------------------------
# Aurora GTX pins are defined in the block desing IP GUI
# Overwriting them here will only generate placement conflicts
# ------------------------------------------------------------------------------
# Timing ignore for quasi-static status signals
set_false_path -from [get_pins diot_v2_i/chip2chip_subsystem/link_*/aurora/*/*/*/CHANNEL_UP_reg/C] \
-to [get_pins {diot_v2_i/chip2chip_subsystem/c2c_link_ctrl/*/*/rd_data_reg[0]/D}]
set_false_path -from [get_pins diot_v2_i/chip2chip_subsystem/link_*/aurora/*/*/*/CHANNEL_HARD_ERR_reg/C] \
-to [get_pins {diot_v2_i/chip2chip_subsystem/c2c_link_ctrl/*/*/rd_data_reg[1]/D}]
-------------------------------------------------------------------------------
--! @file c2c_link.vhd
--! @author Adrian Byszuk
--! @copyright CERN SY-EPC-CCE
--! @date 05-07-2022
--! @brief Chip2Chip link control and status
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! @brief Chip2Chip link control and status
--! @details
--! Provides software with basic control and diagnostic capabilities.
--! Intended to be easily integrated with Xilinx Block Design.
--! Supports up to 8 links, which is maximum in a standard DIOT crate.
entity c2c_link is
generic (
addr_width_g : positive := 6
);
port (
--! @name AXI4Lite slave bus (naming convention compatible with Xilinx IP Integrator)
s_axi_aclk : in std_ulogic;
s_axi_aresetn : in std_ulogic;
--
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_awaddr : in std_logic_vector(addr_width_g-1 downto 0);
--
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
--
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
--
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_araddr : in std_logic_vector(addr_width_g-1 downto 0);
--
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
--! @name Aurora/Chip2Chip signals (for meaning of some signals see the IP documentation)
--! Output reset vector is split to avoid stupid block design slicing
reset_0 : out std_logic; --! PMA reset to link 0
reset_1 : out std_logic; --! PMA reset to link 1
reset_2 : out std_logic; --! PMA reset to link 2
reset_3 : out std_logic; --! PMA reset to link 3
reset_4 : out std_logic; --! PMA reset to link 4
reset_5 : out std_logic; --! PMA reset to link 5
reset_6 : out std_logic; --! PMA reset to link 6
reset_7 : out std_logic; --! PMA reset to link 7
channel_up : in std_logic_vector(7 downto 0); --! Aurora channel_up status
hard_err : in std_logic_vector(7 downto 0); --! Aurora hard_err status
gt_pll_lock : in std_logic_vector(7 downto 0); --! MGT PLL lock status
link_status : in std_logic_vector(7 downto 0); --! Chip2Chip link up status
config_error : in std_logic_vector(7 downto 0); --! Chip2Chip endpoint config error
link_error : in std_logic_vector(7 downto 0); --! Chip2Chip link error
multi_bit_error : in std_logic_vector(7 downto 0) --! Chip2Chip multi_bit error status
);
end entity c2c_link;
--! RTL implementation of c2c_link
architecture rtl of c2c_link is
--! @name Attributes required to silence Vivado BD GUI
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF reset_0: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_0: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_1: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_1: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_2: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_2: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_3: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_3: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_4: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_4: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_5: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_5: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_6: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_6: SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF reset_7: SIGNAL IS "xilinx.com:signal:reset:1.0 reset_o RST";
ATTRIBUTE X_INTERFACE_PARAMETER of reset_7: SIGNAL is "POLARITY ACTIVE_HIGH";
--! @}
begin
--! Wishbone registers (autogenerated)
x_regs : entity work.link_ctrl_regs
port map (
aclk => s_axi_aclk,
areset_n => s_axi_aresetn,
awvalid => s_axi_awvalid,
awready => s_axi_awready,
awaddr => s_axi_awaddr,
awprot => "000",
wvalid => s_axi_wvalid,
wready => s_axi_wready,
wdata => s_axi_wdata,
wstrb => s_axi_wstrb,
bvalid => s_axi_bvalid,
bready => s_axi_bready,
bresp => s_axi_bresp,
arvalid => s_axi_arvalid,
arready => s_axi_arready,
araddr => s_axi_araddr,
arprot => "000",
rvalid => s_axi_rvalid,
rready => s_axi_rready,
rdata => s_axi_rdata,
rresp => s_axi_rresp,
link_0_ctrl_reset_o => reset_0,
link_0_status_channel_up_i => channel_up(0),
link_0_status_hard_err_i => hard_err(0),
link_0_status_gt_pll_lock_i => gt_pll_lock(0),
link_0_status_link_status_i => link_status(0),
link_0_status_config_error_i => config_error(0),
link_0_status_link_error_i => link_error(0),
link_0_status_multi_bit_error_i => multi_bit_error(0),
link_1_ctrl_reset_o => reset_1,
link_1_status_channel_up_i => channel_up(1),
link_1_status_hard_err_i => hard_err(1),
link_1_status_gt_pll_lock_i => gt_pll_lock(1),
link_1_status_link_status_i => link_status(1),
link_1_status_config_error_i => config_error(1),
link_1_status_link_error_i => link_error(1),
link_1_status_multi_bit_error_i => multi_bit_error(1),
link_2_ctrl_reset_o => reset_2,
link_2_status_channel_up_i => channel_up(2),
link_2_status_hard_err_i => hard_err(2),
link_2_status_gt_pll_lock_i => gt_pll_lock(2),
link_2_status_link_status_i => link_status(2),
link_2_status_config_error_i => config_error(2),
link_2_status_link_error_i => link_error(2),
link_2_status_multi_bit_error_i => multi_bit_error(2),
link_3_ctrl_reset_o => reset_3,
link_3_status_channel_up_i => channel_up(3),
link_3_status_hard_err_i => hard_err(3),
link_3_status_gt_pll_lock_i => gt_pll_lock(3),
link_3_status_link_status_i => link_status(3),
link_3_status_config_error_i => config_error(3),
link_3_status_link_error_i => link_error(3),
link_3_status_multi_bit_error_i => multi_bit_error(3),
link_4_ctrl_reset_o => reset_4,
link_4_status_channel_up_i => channel_up(4),
link_4_status_hard_err_i => hard_err(4),
link_4_status_gt_pll_lock_i => gt_pll_lock(4),
link_4_status_link_status_i => link_status(4),
link_4_status_config_error_i => config_error(4),
link_4_status_link_error_i => link_error(4),
link_4_status_multi_bit_error_i => multi_bit_error(4),
link_5_ctrl_reset_o => reset_5,
link_5_status_channel_up_i => channel_up(5),
link_5_status_hard_err_i => hard_err(5),
link_5_status_gt_pll_lock_i => gt_pll_lock(5),
link_5_status_link_status_i => link_status(5),
link_5_status_config_error_i => config_error(5),
link_5_status_link_error_i => link_error(5),
link_5_status_multi_bit_error_i => multi_bit_error(5),
link_6_ctrl_reset_o => reset_6,
link_6_status_channel_up_i => channel_up(6),
link_6_status_hard_err_i => hard_err(6),
link_6_status_gt_pll_lock_i => gt_pll_lock(6),
link_6_status_link_status_i => link_status(6),
link_6_status_config_error_i => config_error(6),
link_6_status_link_error_i => link_error(6),
link_6_status_multi_bit_error_i => multi_bit_error(6),
link_7_ctrl_reset_o => reset_7,
link_7_status_channel_up_i => channel_up(7),
link_7_status_hard_err_i => hard_err(7),
link_7_status_gt_pll_lock_i => gt_pll_lock(7),
link_7_status_link_status_i => link_status(7),
link_7_status_config_error_i => config_error(7),
link_7_status_link_error_i => link_error(7),
link_7_status_multi_bit_error_i => multi_bit_error(7)
);
end architecture rtl;
memory-map:
bus: axi4-lite-32
name: link_ctrl_regs
description: Aurora link control/status
x-hdl:
bus-granularity: byte
children:
- repeat:
name: link
description: Data to be sent to DAC
count: 8
children:
- reg:
name: ctrl
description: Control register
width: 32
access: rw
type: unsigned
children:
- field:
name: reset
description: Reset the Aurora link
range: 0
preset: 0
x-hdl:
type: autoclear
- reg:
name: status
description: Status register
type: unsigned
width: 32
access: ro
children:
- field:
name: channel_up
description: Aurora channel is up and running
range: 0
- field:
name: hard_err
description: Aurora hard error - reset required
range: 1
- field:
name: gt_pll_lock
description: MGT PLL is locked
range: 2
- field:
name: link_status
description: Chip2Chip link is up and running
range: 3
- field:
name: config_error
description: Chip2Chip config error (see Xilinx PG067)
range: 4
- field:
name: link_error
description: Chip2Chip link error (see Xilinx PG067)
range: 5
- field:
name: multi_bit_error
description: Chip2Chip multi-bit error (see Xilinx PG067)
range: 6
This diff is collapsed.
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06/28/2021 04:30:23 PM
-- Design Name:
-- Module Name: constants - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--==============================================================================
--! Entity declaration for constants
--==============================================================================
entity constants is
generic (
g_phyaddr : integer := 9;
g_config_vector : integer := 0;
g_config_valid : integer := 0;
g_signal_detect : integer := 1
);
port (
pl_clk_i : in std_logic;
--! Vector indicating status. We need bits 0 and 1 of the vector
status_vector : in std_logic_vector(15 downto 0);
--! Management clock, (<= 2.5MHz)
mdc_i : in std_logic;
mdc_clk_led : out std_logic;
--! Reset of the module, coming from PS
pl_resetn_i : in std_logic;
reset_o : out std_logic;
--! Autoneg
an_config_o : out std_logic;
an_config_vec_o : out std_logic_vector(15 downto 0);
tx_disable_o : out std_logic;
--! EMIO GPIOs
p_pres_i : in std_logic_vector(1 downto 0);
pwr_cycle_req_o : out std_logic;
bckpl_servmod_i : in std_logic_vector(7 downto 0);
bckpl_servmod_o : out std_logic_vector(7 downto 0);
bckpl_servmod_t_o : out std_logic_vector(7 downto 0);
bckpl_rst_n_o : out std_logic;
psu_alert_i : in std_logic;
f_rst_i : in std_logic;
f_rst_o : out std_logic;
f_rst_t_o : out std_logic;
ps_emio_o : out std_logic_vector(15 downto 0);
ps_emio_i : in std_logic_vector(15 downto 0);
ps_emio_t_i : in std_logic_vector(15 downto 0);
--! I2C busses
wrflash_i2c_irq_i : in std_logic;
bckpl_i2c_irq_i : in std_logic;
ps_irq_o : out std_logic_vector(1 downto 0);
--! Constants module
--! Addr of the PHY device(slave). A constant number
phyaddr : out std_logic_vector(4 downto 0);
configuration_vector : out std_logic_vector(4 downto 0);
configuration_valid : out std_logic_vector(0 downto 0);
--!'1' (if not connected to an optical module), otherwise, default is '0'
signal_detect : out std_logic_vector(0 downto 0);
--! Slices module
link_status_led : out std_logic;
link_sync_led : out std_logic;
clk_src_sel_o : out std_logic_vector(1 downto 0)
);
end constants;
--==============================================================================
--! Architecture declaration
--==============================================================================
architecture Behavioral of constants is
--! Because we want to check if mdc_i<=2.5MHz, cnt must be up to 4096
signal s_cnt : unsigned(11 downto 0);
signal s_mdc_led_o : std_logic;
type t_pwr_state is (IDLE, RST);
signal pwr_state : t_pwr_state;
signal ps_emio2_d0 : std_logic;
signal ps_emio2_p : std_logic;
--==============================================================================
--! Architecture begin
--==============================================================================
begin
an_config_o <= '0';
an_config_vec_o <= x"D801";
tx_disable_o <= '0';
phyaddr <= std_logic_vector(to_unsigned(g_phyaddr, phyaddr'length));
configuration_vector <= std_logic_vector(to_unsigned(g_config_vector, configuration_vector'length));
configuration_valid <= std_logic_vector(to_unsigned(g_config_valid, configuration_valid'length));
signal_detect <= std_logic_vector(to_unsigned(g_signal_detect, signal_detect'length));
reset_o <= '1' when (pl_resetn_i = '0') else '0';
link_status_led <= status_vector(0);
link_sync_led <= status_vector(1);
clk_src_sel_o <= "11";
p_calc_mdc: process(mdc_i, pl_resetn_i)
begin
if (pl_resetn_i = '0') then
s_cnt <= (others=>'0');
s_mdc_led_o <= '0';
elsif (rising_edge(mdc_i)) then
if (s_cnt = 4096-2) then
s_cnt <= (others=>'0');
s_mdc_led_o <= '1';
else
s_mdc_led_o <= '0';
s_cnt <= s_cnt + 1;
end if;
end if;
end process p_calc_mdc;
mdc_clk_led <= s_mdc_led_o;
--! EMIO -> PL GPIO
ps_emio_o(4 downto 0) <= p_pres_i(1 downto 0) & "000";
ps_emio2_p <= '1' when (ps_emio2_d0 = '0' and ps_emio_i(2) = '1') else '0';
p_pwr: process(pl_clk_i)
begin
if rising_edge(pl_clk_i) then
ps_emio2_d0 <= ps_emio_i(2);
if pl_resetn_i = '0' or (ps_emio2_p = '1' and ps_emio_i(1) = '1') then
pwr_state <= IDLE;
pwr_cycle_req_o <= '0';
else
if pwr_state = IDLE then
pwr_cycle_req_o <= '0';
if ps_emio2_p = '1' and ps_emio_i(1) = '0' then
pwr_state <= RST;
end if;
elsif pwr_state = RST then
pwr_cycle_req_o <= '1';
end if;
end if;
end if;
end process p_pwr;
--! EMIO 83..90
ps_emio_o(12 downto 5) <= bckpl_servmod_i(7 downto 0);
bckpl_servmod_o(7 downto 0) <= ps_emio_i(12 downto 5);
bckpl_servmod_t_o(7 downto 0) <= ps_emio_t_i(12 downto 5);
--! EMIO 91
ps_emio_o(13) <= ps_emio_i(13);
bckpl_rst_n_o <= ps_emio_i(13);
--! EMIO 92
ps_emio_o(14) <= psu_alert_i;
--! EMIO 93
ps_emio_o(15) <= f_rst_i;
f_rst_o <= ps_emio_i(15);
f_rst_t_o <= ps_emio_t_i(15);
--! I2C irqs
ps_irq_o(1 downto 0) <= bckpl_i2c_irq_i & wrflash_i2c_irq_i;
end Behavioral;
--==============================================================================
-- architecture end
--==============================================================================
......@@ -51,7 +51,13 @@ entity diot_v2_top is
emio_scl_b : inout std_logic;
emio_sda_b : inout std_logic;
wrflash_scl_b : inout std_logic;
wrflash_sda_b : inout std_logic
wrflash_sda_b : inout std_logic;
aurora_refclk_p : in std_logic;
aurora_refclk_n : in std_logic;
aurora_rx_p : in std_logic_vector(7 downto 0);
aurora_rx_n : in std_logic_vector(7 downto 0);
aurora_tx_p : out std_logic_vector(7 downto 0);
aurora_tx_n : out std_logic_vector(7 downto 0)
);
end diot_v2_top;
......@@ -62,60 +68,94 @@ architecture structure of diot_v2_top is
component diot_v2 is
port (
f_rst_i : in std_logic;
f_rst_o : out std_logic;
f_rst_t : out std_logic;
psu_alert_i : in std_logic;
p_pres_i_0 : in std_logic_vector(1 downto 0);
pwr_cycle_req_o_0 : out std_logic;
clk_src_sel_o : out std_logic_vector(1 downto 0);
gtrefclk_in_clk_p : in std_logic;
gtrefclk_in_clk_n : in std_logic;
pl_reset_led : out std_logic;
link_status_led : out std_logic;
link_sync_led : out std_logic;
mdc_clk_led : out std_logic;
tx_disable_o : out std_logic;
sfp_rxp : in std_logic;
sfp_rxn : in std_logic;
sfp_txp : out std_logic;
sfp_txn : out std_logic;
bckpl_rst_n_o : out std_logic;
bckpl_servmod_i : in std_logic_vector(7 downto 0);
bckpl_servmod_o : out std_logic_vector(7 downto 0);
bckpl_servmod_t : out std_logic_vector(7 downto 0);
i2c_bckpl_scl_i : in std_logic;
i2c_bckpl_scl_o : out std_logic;
i2c_bckpl_scl_t : out std_logic;
i2c_bckpl_sda_i : in std_logic;
i2c_bckpl_sda_o : out std_logic;
i2c_bckpl_sda_t : out std_logic;
i2c_emio_scl_i : in std_logic;
i2c_emio_scl_o : out std_logic;
i2c_emio_scl_t : out std_logic;
i2c_emio_sda_i : in std_logic;
i2c_emio_sda_o : out std_logic;
i2c_emio_sda_t : out std_logic;
i2c_wrflash_scl_i : in std_logic;
i2c_wrflash_scl_o : out std_logic;
i2c_wrflash_scl_t : out std_logic;
i2c_wrflash_sda_i : in std_logic;
i2c_wrflash_sda_o : out std_logic;
i2c_wrflash_sda_t : out std_logic
f_rst_i : in std_logic;
f_rst_o : out std_logic;
f_rst_t : out std_logic;
psu_alert_i : in std_logic;
p_pres_i_0 : in std_logic_vector(1 downto 0);
pwr_cycle_req_o_0 : out std_logic;
clk_src_sel_o : out std_logic_vector(1 downto 0);
gtrefclk_in_clk_p : in std_logic;
gtrefclk_in_clk_n : in std_logic;
pl_reset_led : out std_logic;
link_status_led : out std_logic;
link_sync_led : out std_logic;
mdc_clk_led : out std_logic;
tx_disable_o : out std_logic;
sfp_rxp : in std_logic;
sfp_rxn : in std_logic;
sfp_txp : out std_logic;
sfp_txn : out std_logic;
bckpl_rst_n_o : out std_logic;
bckpl_servmod_i : in std_logic_vector(7 downto 0);
bckpl_servmod_o : out std_logic_vector(7 downto 0);
bckpl_servmod_t : out std_logic_vector(7 downto 0);
i2c_bckpl_scl_i : in std_logic;
i2c_bckpl_scl_o : out std_logic;
i2c_bckpl_scl_t : out std_logic;
i2c_bckpl_sda_i : in std_logic;
i2c_bckpl_sda_o : out std_logic;
i2c_bckpl_sda_t : out std_logic;
i2c_emio_scl_i : in std_logic;
i2c_emio_scl_o : out std_logic;
i2c_emio_scl_t : out std_logic;
i2c_emio_sda_i : in std_logic;
i2c_emio_sda_o : out std_logic;
i2c_emio_sda_t : out std_logic;
i2c_wrflash_scl_i : in std_logic;
i2c_wrflash_scl_o : out std_logic;
i2c_wrflash_scl_t : out std_logic;
i2c_wrflash_sda_i : in std_logic;
i2c_wrflash_sda_o : out std_logic;
i2c_wrflash_sda_t : out std_logic;
aur_refclk_i_clk_p : in std_logic;
aur_refclk_i_clk_n : in std_logic;
aurora_rx_0_rxp : in std_logic;
aurora_rx_0_rxn : in std_logic;
aurora_rx_1_rxp : in std_logic;
aurora_rx_1_rxn : in std_logic;
aurora_rx_2_rxp : in std_logic;
aurora_rx_2_rxn : in std_logic;
aurora_rx_3_rxp : in std_logic;
aurora_rx_3_rxn : in std_logic;
aurora_rx_4_rxp : in std_logic;
aurora_rx_4_rxn : in std_logic;
aurora_rx_5_rxp : in std_logic;
aurora_rx_5_rxn : in std_logic;
aurora_rx_6_rxp : in std_logic;
aurora_rx_6_rxn : in std_logic;
aurora_rx_7_rxp : in std_logic;
aurora_rx_7_rxn : in std_logic;
aurora_tx_0_txp : out std_logic;
aurora_tx_0_txn : out std_logic;
aurora_tx_1_txp : out std_logic;
aurora_tx_1_txn : out std_logic;
aurora_tx_2_txp : out std_logic;
aurora_tx_2_txn : out std_logic;
aurora_tx_3_txp : out std_logic;
aurora_tx_3_txn : out std_logic;
aurora_tx_4_txp : out std_logic;
aurora_tx_4_txn : out std_logic;
aurora_tx_5_txp : out std_logic;
aurora_tx_5_txn : out std_logic;
aurora_tx_6_txp : out std_logic;
aurora_tx_6_txn : out std_logic;
aurora_tx_7_txp : out std_logic;
aurora_tx_7_txn : out std_logic
);
end component diot_v2;
--! Signals backplane servmod
--! @name Signals backplane servmod
signal s_bckpl_servmod_o : std_logic_vector(7 downto 0);
signal s_bckpl_servmod_i : std_logic_vector(7 downto 0);
signal s_bckpl_servmod_t : std_logic_vector(7 downto 0);
--! Signals F RST buffer
--! @name Signals F RST buffer
signal s_f_rst_o : std_logic;
signal s_f_rst_i : std_logic;
signal s_f_rst_t : std_logic;
--! Signals I2C WR FLASH
--! @name Signals I2C WR FLASH
signal s_wrflash_scl_i : std_logic;
signal s_wrflash_scl_o : std_logic;
signal s_wrflash_scl_t : std_logic;
......@@ -123,7 +163,7 @@ architecture structure of diot_v2_top is
signal s_wrflash_sda_o : std_logic;
signal s_wrflash_sda_t : std_logic;
--! Signals I2C Backplane
--! @name Signals I2C Backplane
signal s_bckpl_scl_i : std_logic;
signal s_bckpl_scl_o : std_logic;
signal s_bckpl_scl_t : std_logic;
......@@ -131,7 +171,7 @@ architecture structure of diot_v2_top is
signal s_bckpl_sda_o : std_logic;
signal s_bckpl_sda_t : std_logic;
--! Signals I2C EMIO
--! @name Signals I2C EMIO
signal s_emio_scl_i : std_logic;
signal s_emio_scl_o : std_logic;
signal s_emio_scl_t : std_logic;
......@@ -263,7 +303,41 @@ begin
i2c_wrflash_scl_t => s_wrflash_scl_t,
i2c_wrflash_sda_i => s_wrflash_sda_i,
i2c_wrflash_sda_o => s_wrflash_sda_o,
i2c_wrflash_sda_t => s_wrflash_sda_t
i2c_wrflash_sda_t => s_wrflash_sda_t,
aur_refclk_i_clk_p => aurora_refclk_p,
aur_refclk_i_clk_n => aurora_refclk_n,
aurora_rx_0_rxp => aurora_rx_p(0),
aurora_rx_0_rxn => aurora_rx_n(0),
aurora_rx_1_rxp => aurora_rx_p(1),
aurora_rx_1_rxn => aurora_rx_n(1),
aurora_rx_2_rxp => aurora_rx_p(2),
aurora_rx_2_rxn => aurora_rx_n(2),
aurora_rx_3_rxp => aurora_rx_p(3),