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DIOT Zynq Ultrascale-based System Board
DIOT Zynq Ultrascale-based System Board
Commit a292404f authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch '257-first-gateware-version' into 'master' 

Resolve "first-gateware-version"

Closes #257

See merge request !1
parents bd1726df 77bd121b
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      .gitlab-ci.yml
      View file @ a292404f
      variables:
      GIT_SUBMODULE_STRATEGY: normal
      # Define stages
      stages:
      - compile
      - gateware
      - bootbin
      - release
      job_sw_compile:
      stage: compile
      # Built bistream job
      .build-gw:
      stage: gateware
      variables:
      XILINX_PATH: /opt/Xilinx
      XILINX_VERSION: "2019.2"
      tags:
      - petalinux_2019.2
      # only:
      # - schedules
      - vivado-2019.2
      before_script:
      - source $XILINX_PATH/Vivado/$XILINX_VERSION/settings64.sh
      script:
      - git config --global user.email "OHWR_CI@somewhere.com"
      - git config --global user.name "OHWR_CI"
      - cd sw && export SB_VER=2 && make -j 4
      - cd gw && make $PROJECT.build
      artifacts:
      name: DIOT_SB_CI_$CI_JOB_ID
      when: always
      when: on_success
      paths:
      - gw/output_files/$PROJECT/$PROJECT.bit
      - gw/output_files/$PROJECT/$PROJECT.xsa
      expire_in: 7d
      # Build bitstream for each project
      build_diot_v1:
      extends: .build-gw
      variables:
      PROJECT: diot_v1
      artifacts:
      name: diot_v1-gw-$CI_JOB_ID
      build_diot_v2:
      extends: .build-gw
      variables:
      PROJECT: diot_v2
      artifacts:
      name: diot_v2-gw-$CI_JOB_ID
      # Build OS
      .build-image:
      stage: bootbin
      tags:
      - petalinux-2019.2
      script:
      - git config --global user.email "OHWR_CI@somewhere.com"
      - git config --global user.name "OHWR_CI"
      - cd sw && make -j 4 SB_VER=$BOARD_VERSION
      artifacts:
      when: on_success
      paths:
      - sw/artifacts/BOOT.BIN
      - sw/artifacts/image.ub
      - sw/artifacts/fsbl.elf
      - sw/log/*
      - gw/output_files/$PROJECT/diot_v$BOARD_VERSION.xsa
      expire_in: 7d
      # Build OS for each project
      build-diot-v1-img:
      extends: .build-image
      variables:
      PROJECT: diot_v1
      BOARD_VERSION: 1
      artifacts:
      name: diot_v1-linux-$CI_JOB_ID
      # Build OS for each project
      build-diot-v2-img:
      extends: .build-image
      variables:
      PROJECT: diot_v2
      BOARD_VERSION: 2
      artifacts:
      name: diot_v2-linux-$CI_JOB_ID
      # Define job for release
      release_job:
      stage: release
      image: registry.gitlab.com/gitlab-org/release-cli:latest
      tags:
      - petalinux-2019.2
      script:
      - gitlab-release --zip "diot_v1-${CI_COMMIT_TAG}.zip" gw/output_files/diot_v1 sw/artifacts/BOOT.BIN sw/artifacts/image.ub sw/artifacts/fsbl.elf sw/log/* --link-in-desc --description "Bootable Image V1"
      - gitlab-release --zip "diot_v2-${CI_COMMIT_TAG}.zip" gw/output_files/diot_v2 sw/artifacts/BOOT.BIN sw/artifacts/image.ub sw/artifacts/fsbl.elf sw/log/* --link-in-desc --description "Bootable Image V2"
      only:
      - /^v[0-9]+\.[0-9]+\.[0-9]+$/
      gw/.gitignore 0 → 100644
      View file @ a292404f
      # cache
      .Xil
      # Generated files
      output_files
      # vivado
      *.log
      *.jou
      gw/Makefile 0 → 100644
      View file @ a292404f
      #!/usr/bin/make
      # ##############################################################################
      # Settings
      DOCKER_NAME=vivado-template
      DOCKERFILE_PATH=docker
      XILINX_TOOLS=/opt/Xilinx
      XIL_VER?=2019.2
      SETUP_XIL_ENV=source ${XILINX_TOOLS}/Vivado/${XIL_VER}/settings64.sh
      CALL_VIVADO_DEF=vivado -source build_project.tcl -mode batch -nolog -nojournal -notrace -tclargs
      docker_build:
      docker build -f ${DOCKERFILE_PATH}/Dockerfile -t ${DOCKER_NAME} ${DOCKERFILE_PATH}
      CALL_DOCKER?=docker run -w${CURDIR} \
      -v${CURDIR}:${CURDIR} \
      -v ${HOME}:${HOME} \
      -v /etc/passwd:/etc/passwd:ro \
      -v /etc/shadow:/etc/shadow:ro \
      -v /etc/group:/etc/group:ro \
      -v /tmp:/tmp \
      -v /tmp/.X11-unix:/tmp/.X11-unix \
      -v ${XILINX_TOOLS}:${XILINX_TOOLS} \
      -v /var/run/dbus:/var/run/dbus \
      -e DISPLAY=${DISPLAY} \
      -u $$(id -u):$$(id -g) \
      --privileged \
      -t ${DOCKER_NAME} /bin/bash -c
      ifdef GITLAB_CI
      CMD_DOCKER=eval
      CALL_VIVADO=${CALL_VIVADO_DEF}
      else
      CMD_DOCKER=${CALL_DOCKER}
      CALL_VIVADO=${SETUP_XIL_ENV} && ${CALL_VIVADO_DEF}
      endif
      # ##############################################################################
      # Define project list
      TARGET_LIST:=$(shell ls projects)
      TARGET_BUILD_LIST:=$(addsuffix .build, ${TARGET_LIST})
      TARGET_BD_LIST:=$(addsuffix .bd, ${TARGET_LIST})
      TARGET_CLEAN_LIST:=$(addsuffix .clean, ${TARGET_LIST})
      # ##############################################################################
      # Build Steps
      OUTPUT_PATH=output_files
      ${OUTPUT_PATH}:
      mkdir -p @
      ${TARGET_BUILD_LIST}:
      ${CMD_DOCKER} '${CALL_VIVADO} projects/$(basename $@) build ${OUTPUT_PATH}'
      ${TARGET_BD_LIST}:
      ${CMD_DOCKER} '${CALL_VIVADO} projects/$(basename $@) bd ${OUTPUT_PATH}'
      ${TARGET_CLEAN_LIST}:
      rm -rf ${OUTPUT_PATH}/$(basename $@)
      # ##############################################################################
      # Clean rule
      # ##############################################################################
      clean:
      rm -rf ${OUTPUT_PATH}
      rm -rf *.log *.jou
      gw/README.md 0 → 100644
      View file @ a292404f
      # Gateware
      This repository folder allows you to build the bitstream/XSA file for the DIOT system board version 1 & 2 which based on Xilinx Zynq Ultrascale+ (**xczu7cg-ffvf1517-1-e**)
      ## Requirements Linux
      - Docker:
      - [Install Docker Debian](https://docs.docker.com/engine/install/debian/)
      - [Install Docker Ubuntu](https://docs.docker.com/engine/install/ubuntu/)
      - [Install Docker CentOS](https://docs.docker.com/engine/install/centos/)
      - Vitis **v2019.2**:
      - [Download Vitis 2019.2](https://www.xilinx.com/member/forms/download/xef-vitis.html?filename=Xilinx_Vitis_2019.2_1106_2127.tar.gz)
      - [Install Vitis](https://docs.xilinx.com/v/u/2019.2-English/ug1400-vitis-embedded)
      - Install make Debian/Ubuntu:
      ```console
      sudo apt install -y make
      ```
      - Install make CentOS:
      ```console
      yum install -y make
      ```
      ## Requirements Windows
      Unfortunately Windows is not supported yet
      ## Build Container
      ```console
      make docker_build
      ```
      ## Build Design
      - Build bitstream:
      ```console
      make <project>.build
      ```
      - Build just the block design:
      ```console
      make <project>.bd
      ```
      In both cases the project options are:
      - diot_v1
      - diot_v2
      ## Maintainers
      - [Alén Arias Vázquez](mailto:alen.arias.vazquez@cern.ch)
      - [Greg Daniluk](mailto:grzegorz.daniluk@cern.ch)
      gw/build_project.tcl 0 → 100644
      View file @ a292404f
      ################################################################################
      #
      # Main Script to buil any project in the repository
      #
      ################################################################################
      source functions.tcl -notrace
      write_msg "INFO: Launching Vivado TCL mode" "1"
      if { $::argc == 3 } {
      set target_path [lindex $argv 0]
      set run_type [lindex $argv 1]
      set output_path [lindex $argv 2]
      } else {
      write_msg "ERROR: Bad call to tcl script build_project.tcl" "3"
      return 1
      }
      # Loading project specific config
      source ${target_path}/tcl/project_cfg.tcl -notrace
      set_param general.maxThreads ${max_threads}
      # Set the project name
      set _xil_proj_name_ ${project_name}
      source ${target_path}/tcl/create_bd.tcl -notrace
      # Create project
      create_project ${_xil_proj_name_} ${output_path}/${_xil_proj_name_} -part ${reference_part}
      # Source TCL FPGA Device
      source common-ip/fpga_device/tcl/fpga_device.tcl
      create_fpga_version "${_xil_proj_name_}" "common-ip/fpga_device/src/fpga_device.v" "${output_path}/${_xil_proj_name_}/fpga_device.v"
      add_files -norecurse common-ip/fpga_device/src/dna_reader.v
      add_files -norecurse ${output_path}/${_xil_proj_name_}/fpga_device.v
      # Set Properties from the list
      if [ info exist ::user_list(PROP_NAME) ] {
      set curr_project [ current_project ]
      set list_names [ get_list PROP_NAME ]
      set list_values [ get_list PROP_VAL ]
      set list_names_max_i [ get_list_size PROP_NAME ]
      for { set i 0 } { $i < ${list_names_max_i} } { incr i } {
      set lname [ lindex ${list_names} ${i} ]
      set lvalue [ lindex ${list_values} ${i} ]
      write_msg "INFO: Set property $lname to $lvalue" "1"
      set_property -name $lname -value $lvalue -objects $curr_project
      }
      }
      # Add VHDL
      if [ info exist ::user_list(SRC_VHDL) ] {
      set list_vhdl [ get_list SRC_VHDL ]
      set list_lib [ get_list LIB_VHDL ]
      set list_vhdl_max_i [ get_list_size SRC_VHDL ]
      for { set i 0 } { $i < ${list_vhdl_max_i} } { incr i } {
      set vhdl_src [ lindex ${list_vhdl} ${i} ]
      set vhdl_lib [ lindex ${list_lib} ${i} ]
      write_msg "INFO: Adding VHLD file ${vhdl_src}" "1"
      read_vhdl -library ${vhdl_lib} ${target_path}/src/${vhdl_src}
      }
      }
      # Add VHDL08
      if [ info exist ::user_list(SRC_VHDL08) ] {
      set list_vhdl [ get_list SRC_VHDL08 ]
      set list_lib [ get_list LIB_VHDL08 ]
      set list_vhdl_max_i [ get_list_size SRC_VHDL08 ]
      for { set i 0 } { $i < ${list_vhdl_max_i} } { incr i } {
      set vhdl_src [ lindex ${list_vhdl} ${i} ]
      set vhdl_lib [ lindex ${list_lib} ${i} ]
      write_msg "INFO: Adding VHLD 2008 file ${vhdl_src}" "1"
      read_vhdl -library ${vhdl_lib} -2008 ${target_path}/src/${vhdl_src}
      }
      }
      # Add Verilog/SystemVerilog sources
      if [ info exist ::user_list(SRC_VERILOG) ] {
      set list_ver [ get_list SRC_VERILOG ]
      set list_ver_max_i [ get_list_size SRC_VERILOG ]
      for { set i 0 } { $i < ${list_ver_max_i} } { incr i } {
      set ver_src [ lindex ${list_ver} ${i} ]
      if { [ enable_sv_compilation ${ver_src} ] == 1 } {
      write_msg "INFO: Adding SystemVerilog file ${ver_src}" "1"
      read_verilog -library ${lib_default} -sv ${target_path}/src/${ver_src}
      } else {
      write_msg "INFO: Adding Verilog file ${ver_src}" "1"
      read_verilog -library ${lib_default} ${target_path}/src/${ver_src}
      }
      }
      }
      # Add XDC Files
      if [ info exist ::user_list(CONSTRAINT) ] {
      set list_xdc [ get_list CONSTRAINT ]
      set list_names_max_i [ get_list_size CONSTRAINT ]
      for { set i 0 } { $i < ${list_names_max_i} } { incr i } {
      set file_xdc [ lindex ${list_xdc} ${i} ]
      write_msg "INFO: Adding XDC file ${file_xdc}" "1"
      read_xdc ${target_path}/constraints/${file_xdc}
      }
      }
      # Set the directory path for the new project
      set proj_dir [get_property directory [current_project]]
      # Create 'sources_1' fileset (if not found)
      if {[string equal [get_filesets -quiet sources_1] ""]} {
      create_fileset -srcset sources_1
      }
      update_ip_catalog -rebuild
      set obj [get_filesets sources_1]
      set_property -name "top" -value ${entity_top} -objects $obj
      # ##############################################################################
      # Create Block Design
      # ##############################################################################
      write_msg "INFO: Generating block design" "1"
      create_block_design "" ${_xil_proj_name_} ${target_path}
      update_compile_order -fileset sources_1
      set_property IS_ENABLED "1" [ get_files ${_xil_proj_name_}.bd ]
      set_property REGISTERED_WITH_MANAGER "1" [ get_files ${_xil_proj_name_}.bd ]
      set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [ get_files ${_xil_proj_name_}.bd ]
      # ##############################################################################
      # Launch synthesis & implementation
      # ##############################################################################
      if { [ string equal ${run_type} "build" ] } {
      # Launch Synthesis
      write_msg "INFO: Launch Synthesis" "1"
      launch_runs synth_1 -jobs ${max_threads}
      wait_on_run synth_1
      set status_synth [ get_property STATUS [ get_runs synth_1 ] ]
      if { [ string equal ${status_synth} "synth_design Complete!" ] } {
      write_msg "INFO: ${status_synth}" "1"
      } else {
      write_msg "ERROR: Synthesis run failed" "3"
      write_msg "ERROR: ${status_synth}" "3"
      exit 1
      }
      # Set Implementation Properties
      set obj [ get_runs impl_1 ]
      set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj
      # Launch Implementation & Bitstream
      write_msg "INFO: Launch Implementation & Bistream generation" "1"
      launch_runs impl_1 -to_step write_bitstream -jobs ${max_threads}
      wait_on_run impl_1
      set status_impl_1 [ get_property STATUS [ get_runs impl_1 ] ]
      if { [ string equal ${status_impl_1} "write_bitstream Complete!" ] } {
      write_msg "INFO: ${status_impl_1}" "1"
      } else {
      write_msg "ERROR: Implementation run failed" "3"
      write_msg "ERROR: ${status_impl_1}" "3"
      exit 1
      }
      # Copy Bitstream
      if { [ file exists ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.runs/impl_1/${entity_top}.bit ] } {
      write_msg "INFO: Copy Bistream" "1"
      file copy ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.runs/impl_1/${entity_top}.bit ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.bit
      write_msg "INFO: Generating XSA with bitstream ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.xsa" "1"
      write_hw_platform -force ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.xsa -fixed -include_bit
      } else {
      write_msg "ERROR: Failed Bistream Generation" "3"
      exit 1
      }
      } else {
      # Generate XSA without bistream
      write_msg "INFO: Target Hardware Platform" "1"
      generate_target {synthesis implementation} [get_files ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.srcs/sources_1/bd/${_xil_proj_name_}/${_xil_proj_name_}.bd]
      write_msg "INFO: Generating XSA file ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.xsa" "1"
      write_hw_platform -force ${output_path}/${_xil_proj_name_}/${_xil_proj_name_}.xsa -fixed
      }
      exit 0
      gw/common-ip/fpga_device/src/dna_reader.v 0 → 100644
      View file @ a292404f
      //==============================================================================
      //! @file dna_reader.v
      //==============================================================================
      //------------------------------------------------------------------------------
      // --
      // CERN - DNA Reader Xilinx FPGA --
      // --
      //------------------------------------------------------------------------------
      //
      // unit name: DNA Reader Xilinx FPGA
      //
      //! @brief DNA Reader Xilinx FPGA
      //
      //! @author alen.arias.vazquez@cern.ch
      //
      //! @date 11/05/2022
      //
      //! @details
      //! PL DNA is 96bits width in the Ultrascale/Ultrascale+
      //
      //------------------------------------------------------------------------------
      module dna_reader # (
      parameter g_SIM_DNA_VALUE = 96'hAABBCCDDEEFF112233445566
      )
      (
      input clk_i,
      input rst_n_i,
      output dna_rdy_o,
      output [95:0] dna_o
      );
      //! Status
      localparam [1:0] SET = 2'b00;
      localparam [1:0] UNSET = 2'b01;
      localparam [1:0] COUNT = 2'b11;
      localparam [1:0] DONE = 2'b10;
      (* fsm_encoding = "gray" *) reg [1:0] s_state;
      //! Constants
      localparam [6:0] c_MAX_CTR = 7'd96;
      //! Signals
      reg s_read;
      reg s_shift;
      reg s_dna_rdy;
      reg [6:0] s_shift_c;
      reg [95:0] s_dna;
      wire s_data;
      //! FSM
      always @(posedge clk_i, negedge rst_n_i)
      begin : p_fsm
      if(! rst_n_i) begin
      s_read <= 1'b0;
      s_shift <= 1'b0;
      s_shift_c <= 'h0;
      s_dna_rdy <= 1'b0;
      s_state <= SET;
      end
      else begin
      case (s_state)
      //! State SET
      SET:
      begin
      s_shift_c <= 'h0;
      s_read <= 1'b1;
      s_shift <= 1'b1;
      s_dna_rdy <= 1'b0;
      s_state <= UNSET;
      end
      //! State UNSET
      UNSET:
      begin
      s_shift_c <= 'h0;
      s_read <= 1'b0;
      s_shift <= 1'b1;
      s_dna_rdy <= 1'b0;
      s_state <= COUNT;
      end
      //! State COUNT
      COUNT:
      begin
      s_read <= 1'b0;
      if (s_shift_c < c_MAX_CTR) begin
      s_shift_c <= s_shift_c + 'd1;
      s_shift <= 1'b1;
      s_dna_rdy <= 1'b0;
      end
      else begin
      s_shift <= 1'b0;
      s_shift_c <= 'h0;
      s_dna_rdy <= 1'b1;
      s_state <= DONE;
      end
      end
      //! State DONE
      DONE:
      begin
      s_read <= 1'b0;
      s_shift <= 1'b0;
      s_shift_c <= 'h0;
      s_dna_rdy <= 1'b1;
      s_state <= DONE;
      end
      endcase
      end
      end : p_fsm
      //! Shift Register
      always @(posedge clk_i, negedge rst_n_i)
      begin : p_shift
      if (! rst_n_i)
      s_dna <= 'h0;
      else begin
      if (s_shift)
      s_dna <= {s_data, s_dna[95:1]};
      end
      end : p_shift
      assign dna_rdy_o = s_dna_rdy;
      assign dna_o = s_dna;
      //! Instance Xilinx Macro
      DNA_PORTE2 # (
      .SIM_DNA_VALUE (g_SIM_DNA_VALUE)
      ) i_DNA_PORTE2 (
      .CLK (clk_i),
      .DIN ('h0),
      .READ (s_read), //! input: load DNA
      .SHIFT (s_shift), //! input: shift enable input
      .DOUT (s_data) //! output: DNA output bit
      );
      endmodule
      //------------------------------------------------------------------------------
      //! end module
      //------------------------------------------------------------------------------
      gw/common-ip/fpga_device/src/fpga_device.v 0 → 100644
      View file @ a292404f
      //==============================================================================
      //! @file fpga_device.v
      //==============================================================================
      //------------------------------------------------------------------------------
      // --
      // CERN - FPGA Version Device --
      // --
      //------------------------------------------------------------------------------
      //
      // unit name: fpga_device
      //
      //! @brief FPGA Version Device
      //
      //! @author alen.arias.vazquez@cern.ch
      //
      //! @date 06/05/2022
      //
      //! @details
      //
      //! @URL: https://ohwr.org/project/fpga-dev-id/wikis
      //
      //------------------------------------------------------------------------------
      module fpga_device # (
      parameter g_VENDOR_ID = 32'h0,
      parameter g_DEVICE_ID = 32'h0,
      parameter g_VERSION = 32'h0,
      parameter g_BYTE_ORD_MARK = 32'h0,
      parameter g_SOURCE_ID = 128'h0,
      parameter g_CAP_MASK = 32'h0,
      parameter g_VENDOR_UUID = 128'h0,
      parameter g_CORE_ID = 32'h0,
      parameter g_NAME = 64'h0,
      parameter g_BUILD_DATE = 32'd0,
      parameter g_HASH = 160'h0,
      parameter g_TAG = 64'h0,
      parameter g_S_AXI_DATA_WIDTH = 32,
      parameter g_S_AXI_ADDR_WIDTH = 8,
      parameter g_SIM_DNA_VALUE = 96'hAABBCCDDEEFF112233445566
      )
      (
      // Clock && RESET
      input S_AXI_ARESETN,
      input S_AXI_ACLK,
      //! Slave Interface Write Address Ports
      input [g_S_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
      input [2:0] S_AXI_AWPROT,
      input S_AXI_AWVALID,
      output S_AXI_AWREADY,
      //! Slave Interface Write Data Ports
      input [g_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
      input [(g_S_AXI_DATA_WIDTH/8)-1:0] S_AXI_WSTRB,
      input S_AXI_WVALID,
      output S_AXI_WREADY,
      //! Slave Interface Write Response Ports
      output [1:0] S_AXI_BRESP,
      output S_AXI_BVALID,
      input S_AXI_BREADY,
      //! Slave Interface Read Address Ports
      input [g_S_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
      input [2:0] S_AXI_ARPROT,
      input S_AXI_ARVALID,
      output S_AXI_ARREADY,
      //! Slave Interface Read Data Ports
      output [g_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
      output [1:0] S_AXI_RRESP,
      output S_AXI_RVALID,
      input S_AXI_RREADY
      );
      //! Unused lines WRITE
      assign S_AXI_AWREADY = 1'b0;
      assign S_AXI_WREADY = 1'b0;
      assign S_AXI_BRESP = 2'b0;
      assign S_AXI_BVALID = 1'b0;
      //! Unused lines READ
      assign S_AXI_RRESP = 2'b00;
      //! Constants
      localparam c_ZEROS = {g_S_AXI_DATA_WIDTH{1'b0}};
      localparam c_LSB_ADDR = (g_S_AXI_DATA_WIDTH / 32) + 1;
      localparam c_ADDR_VENDOR_ID = 'h00;
      localparam c_ADDR_DEVICE_ID = 'h01;
      localparam c_ADDR_VERSION = 'h02;
      localparam c_ADDR_BYTE_ORD_MARK = 'h03;
      localparam c_ADDR_SOURCE_ID_0 = 'h04;
      localparam c_ADDR_SOURCE_ID_1 = 'h05;
      localparam c_ADDR_SOURCE_ID_2 = 'h06;
      localparam c_ADDR_SOURCE_ID_3 = 'h07;
      localparam c_ADDR_CAP_MASK = 'h08;
      localparam c_ADDR_VENDOR_UUID_0 = 'h0C;
      localparam c_ADDR_VENDOR_UUID_1 = 'h0D;
      localparam c_ADDR_VENDOR_UUID_2 = 'h0E;
      localparam c_ADDR_VENDOR_UUID_3 = 'h0F;
      localparam c_ADDR_CORE_ID = 'h10;
      localparam c_ADDR_NAME_LSB = 'h11;
      localparam c_ADDR_NAME_MSB = 'h12;
      localparam c_ADDR_BUILD_T = 'h13;
      localparam c_ADDR_HASH_0 = 'h14;
      localparam c_ADDR_HASH_1 = 'h15;
      localparam c_ADDR_HASH_2 = 'h16;
      localparam c_ADDR_HASH_3 = 'h17;
      localparam c_ADDR_HASH_4 = 'h18;
      localparam c_ADDR_DNA_0 = 'h19;
      localparam c_ADDR_DNA_1 = 'h1A;
      localparam c_ADDR_DNA_2 = 'h1B;
      localparam c_ADDR_TAG_LSB = 'h1C;
      localparam c_ADDR_TAG_MSB = 'h1D;
      //! Axi lite auxiliary regs
      reg [g_S_AXI_ADDR_WIDTH-1:0] s_araddr;
      reg s_arready;
      reg s_rvalid;
      //! User lines
      reg [g_S_AXI_DATA_WIDTH-1:0] s_RDATA;
      wire [g_S_AXI_ADDR_WIDTH-c_LSB_ADDR-1:0] s_RADDR;
      wire s_REN;
      //! DNA
      wire [95:0] s_dna;
      //--------------------------------------------------------------------------
      //! ARREADY LOGIC & ARADDR Latch
      always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
      begin : p_arready
      if (! S_AXI_ARESETN) begin
      s_araddr <= 'h0;
      s_arready <= 1'b0;
      end
      else begin
      if (!s_arready && S_AXI_ARVALID) begin
      s_araddr <= S_AXI_ARADDR;
      s_arready <= 1'b1;
      end
      else begin
      s_araddr <= s_araddr;
      s_arready <= 1'b0;
      end
      end
      end : p_arready
      assign S_AXI_ARREADY = s_arready;
      //! RVALID
      always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
      begin : p_rvalid
      if (! S_AXI_ARESETN)
      s_rvalid <= 1'b0;
      else begin
      if (~(s_rvalid) & s_arready & S_AXI_ARVALID)
      s_rvalid <= 1'b1;
      else if (s_rvalid & S_AXI_RREADY)
      s_rvalid <= 1'b0;
      end
      end : p_rvalid
      //! Read assignment
      assign s_RADDR = s_araddr[g_S_AXI_ADDR_WIDTH-1:c_LSB_ADDR];
      assign s_REN = ~(s_rvalid) & s_arready & S_AXI_ARVALID;
      //! Register Access
      always @(posedge S_AXI_ACLK, negedge S_AXI_ARESETN)
      begin : p_read
      if (! S_AXI_ARESETN)
      s_RDATA <= 'h0;
      else begin
      if (s_REN) begin
      case(s_RADDR)
      c_ADDR_VENDOR_ID : s_RDATA <= g_VENDOR_ID;
      c_ADDR_DEVICE_ID : s_RDATA <= g_DEVICE_ID;
      c_ADDR_VERSION : s_RDATA <= g_VERSION;
      c_ADDR_BYTE_ORD_MARK : s_RDATA <= g_BYTE_ORD_MARK;
      c_ADDR_SOURCE_ID_0 : s_RDATA <= g_SOURCE_ID[31:0];
      c_ADDR_SOURCE_ID_1 : s_RDATA <= g_SOURCE_ID[63:32];
      c_ADDR_SOURCE_ID_2 : s_RDATA <= g_SOURCE_ID[95:64];
      c_ADDR_SOURCE_ID_3 : s_RDATA <= g_SOURCE_ID[127:96];
      c_ADDR_CAP_MASK : s_RDATA <= g_CAP_MASK;
      c_ADDR_VENDOR_UUID_0 : s_RDATA <= s_dna[31:0];
      c_ADDR_VENDOR_UUID_1 : s_RDATA <= {g_VENDOR_UUID[63:48],s_dna[47:32]};
      c_ADDR_VENDOR_UUID_2 : s_RDATA <= g_VENDOR_UUID[95:64];
      c_ADDR_VENDOR_UUID_3 : s_RDATA <= g_VENDOR_UUID[127:96];
      c_ADDR_CORE_ID : s_RDATA <= g_CORE_ID;
      c_ADDR_NAME_LSB : s_RDATA <= g_NAME[31:0];
      c_ADDR_NAME_MSB : s_RDATA <= g_NAME[63:32];
      c_ADDR_BUILD_T : s_RDATA <= g_BUILD_DATE;
      c_ADDR_HASH_0 : s_RDATA <= g_HASH[31:0];
      c_ADDR_HASH_1 : s_RDATA <= g_HASH[63:32];
      c_ADDR_HASH_2 : s_RDATA <= g_HASH[95:64];
      c_ADDR_HASH_3 : s_RDATA <= g_HASH[127:96];
      c_ADDR_HASH_4 : s_RDATA <= g_HASH[159:128];
      c_ADDR_DNA_0 : s_RDATA <= s_dna[31:0];
      c_ADDR_DNA_1 : s_RDATA <= s_dna[63:32];
      c_ADDR_DNA_2 : s_RDATA <= s_dna[95:64];
      c_ADDR_TAG_LSB : s_RDATA <= g_TAG[31:0];
      c_ADDR_TAG_MSB : s_RDATA <= g_TAG[63:32];
      default : s_RDATA <= c_ZEROS;
      endcase
      end
      end
      end : p_read
      //! Assign outputs
      assign S_AXI_RDATA = s_RDATA;
      assign S_AXI_RVALID = s_rvalid;
      //--------------------------------------------------------------------------
      dna_reader # (
      .g_SIM_DNA_VALUE (g_SIM_DNA_VALUE)
      ) i_dna_reader (
      .clk_i (S_AXI_ACLK),
      .rst_n_i (S_AXI_ARESETN),
      .dna_rdy_o (),
      .dna_o (s_dna)
      );
      endmodule
      //------------------------------------------------------------------------------
      //! end module
      //------------------------------------------------------------------------------
      gw/common-ip/fpga_device/tb/dna_reader_tb.sv 0 → 100644
      View file @ a292404f
      //==============================================================================
      //! @file dna_reader_tb.sv
      //==============================================================================
      //------------------------------------------------------------------------------
      // --
      // CERN - TestBench DNA Reader Xilinx FPGA --
      // --
      //------------------------------------------------------------------------------
      //
      // unit name: TestBench DNA Reader Xilinx FPGA
      //
      //! @brief TestBench DNA Reader Xilinx FPGA
      //
      //! @author alen.arias.vazquez@cern.ch
      //
      //! @date 12/05/2022
      //
      //------------------------------------------------------------------------------
      module dna_reader_tb # (
      parameter g_SIM_DNA_VALUE = 96'hAABBCCDDEEFF112233445566
      );
      //! Define time units
      timeunit 1ns;
      //! Define stimulus
      wire [95:0] s_dna;
      reg s_clk;
      reg s_rst_n;
      wire s_dna_rdy;
      dna_reader # (
      .g_SIM_DNA_VALUE (g_SIM_DNA_VALUE)
      ) i_dna_reader (
      .clk_i (s_clk),
      .rst_n_i (s_rst_n),
      .dna_rdy_o (s_dna_rdy),
      .dna_o (s_dna)
      );
      //! Initial block
      initial
      begin : p_initial
      s_rst_n = 1'b0;
      s_clk = 1'b0;
      end : p_initial
      //! Clock generator
      always
      begin : p_clock
      #5 s_clk = 1'b1;
      #5 s_clk = 1'b0;
      end : p_clock
      //! Clock generator
      always
      begin : p_rst
      #25 s_rst_n = 1'b1;
      end : p_rst
      //! Check Result
      initial
      begin : p_result
      @(posedge s_dna_rdy)
      assert (s_dna == g_SIM_DNA_VALUE) $display("Result is correct");
      else begin
      $error("Failure in simulation");
      $error("Generic value: %X", g_SIM_DNA_VALUE);
      $error("Expecter Valuer: %X", s_dna);
      end
      end : p_result
      endmodule
      //------------------------------------------------------------------------------
      //! end module
      //------------------------------------------------------------------------------
      gw/common-ip/fpga_device/tcl/fpga_device.tcl 0 → 100644
      View file @ a292404f
      ################################################################################
      #
      # Author: alen.arias.vazquez@cern.ch
      # Date: 10/05/2022
      #
      ################################################################################
      # Get Git Hash
      proc get_git_hash {} {
      return [ exec git rev-parse --short=40 HEAD ]
      }
      # Get Git Tag
      proc get_git_tag {} {
      set git_tag_check [ catch { exec git describe --tags --abbrev=0 --dirty=D } msg ]
      if { $git_tag_check == 1 } {
      write_yellow "Any tag has not been defined yet in the current repository"
      return "v0.0.0"
      } else {
      return $msg
      }
      }
      # Conver Git Tag to number:
      # bits 31-24: major number
      # bits 23-16: minor number
      # bits 15-00: patch number
      proc convert_tag_to_number { tag } {
      # Highest v255.255.65535
      if { [ string range $tag 0 0 ] == "v" } {
      # Remove v
      set tag [ string range $tag 1 end ]
      if { [ string range $tag end end ] == "D" } {
      # Remove Dirty
      set tag [ string range $tag 0 end-1 ]
      }
      set list_num [ split $tag {.} ]
      if { [ llength $list_num ] == 3 } {
      set major [ format %02X [ lindex $list_num 0 ] ]
      set minor [ format %02X [ lindex $list_num 1 ] ]
      set patch [ format %04X [ lindex $list_num 2 ] ]
      return [ concat $major$minor$patch ]
      } else {
      return 0
      }
      } else {
      return 0
      }
      }
      # Convert String to Hex String
      proc convert_string_to_hex { str size } {
      while { $size > [ string length $str ] } {
      set str [ concat -$str ]
      }
      binary scan $str H* hex
      return $hex
      }
      # Generate UUID
      proc generate_uuid {} {
      set str [ info hostname ]
      binary scan $str H* hex_value
      set uuid [ format %2.2x [ clock seconds ]]
      append uuid [ string range [ format %2.2x [ clock clicks ] ] 0 3 ]
      append uuid [ string range [ format %2.2x [ clock clicks ] ] 2 5 ]
      append uuid [ string range [ format %2.2x [ clock clicks ] ] 4 7 ]
      append uuid [ string range $hex_value 0 11]
      return $uuid
      }
      proc print_uuid { hex_uuid } {
      return [ concat [ string range $hex_uuid 0 7 ]-[ string range $hex_uuid 8 11 ]-[ string range $hex_uuid 12 15 ]-[ string range $hex_uuid 16 19 ]-[ string range $hex_uuid 20 end ] ]
      }
      proc create_fpga_version { name ref target } {
      # Parameters that are Constants:
      set vendor_id "FF000000"
      set device_id "44494F5A"
      set byte_ord "FFFE0000"
      set cap_mask "AAAAAAAA"
      # IP CORE ID
      set core_id "46504741"
      # Get git parameters
      set git_hash [ get_git_hash ]
      set git_tag [ get_git_tag ]
      # Get DATE
      set build_date [ clock seconds ]
      # Cut Commit hash
      set source_id [ string range $git_hash 8 end ]
      # UUID
      set uuid [ generate_uuid ]
      # Convert string to hex
      set name_hex [ convert_string_to_hex $name 8 ]
      set git_tag_hex [ convert_string_to_hex $git_tag 8 ]
      set num_version [ convert_tag_to_number $git_tag ]
      # Open input and output file
      set r_file [open $ref r]
      set w_file [open $target w]
      # Map for replace strings
      set map {}
      lappend map "parameter g_VENDOR_ID = 32'h0," "parameter g_VENDOR_ID = 32'h$vendor_id,"
      lappend map "parameter g_DEVICE_ID = 32'h0," "parameter g_DEVICE_ID = 32'h$device_id,"
      lappend map "parameter g_VERSION = 32'h0," "parameter g_VERSION = 32'h$num_version,"
      lappend map "parameter g_BYTE_ORD_MARK = 32'h0," "parameter g_BYTE_ORD_MARK = 32'h$byte_ord,"
      lappend map "parameter g_SOURCE_ID = 128'h0," "parameter g_SOURCE_ID = 128'h$source_id,"
      lappend map "parameter g_CAP_MASK = 32'h0," "parameter g_CAP_MASK = 32'h$cap_mask,"
      lappend map "parameter g_VENDOR_UUID = 128'h0," "parameter g_VENDOR_UUID = 128'h$uuid,"
      lappend map "parameter g_CORE_ID = 32'h0," "parameter g_CORE_ID = 32'h$core_id,"
      lappend map "parameter g_NAME = 64'h0," "parameter g_NAME = 64'h$name_hex,"
      lappend map "parameter g_BUILD_DATE = 32'd0," "parameter g_BUILD_DATE = 32'd$build_date,"
      lappend map "parameter g_HASH = 160'h0," "parameter g_HASH = 160'h$git_hash,"
      lappend map "parameter g_TAG = 64'h0," "parameter g_TAG = 64'h$git_tag_hex,"
      write_green ""
      write_green "Fpga Device Generation:"
      write_green "Vendor ID: 0x$vendor_id"
      write_green "Device ID: 0x$device_id"
      write_green "Number Version: 0x$num_version"
      write_green "Byte Order Mark: 0x$byte_ord"
      write_green "Source ID: $source_id"
      write_green "Capability Mask: 0x$cap_mask"
      write_green "Vendor UUID: [ print_uuid $uuid ]"
      write_green "IP Core ID: 0x$core_id"
      write_green "Project name: $name"
      write_green "Build Date: [ clock format $build_date -format "%Y-%m-%d %H:%M:%S" ]"
      write_green "Git Hash: $git_hash"
      write_green "Git Tag: $git_tag"
      write_green ""
      # Copy files
      while { [ gets $r_file r_line ] >= 0 } {
      set w_line [ string map $map $r_line]
      puts $w_file $w_line
      }
      # Closes files
      close $r_file
      close $w_file
      }
      gw/docker/Dockerbuild.sh 0 → 100644
      View file @ a292404f
      #!/bin/sh
      docker build -f Dockerfile -t vivado .
      gw/docker/Dockerfile 0 → 100644
      View file @ a292404f
      FROM ubuntu:18.04
      ENV TERM xterm
      RUN dpkg --add-architecture i386
      RUN echo 'APT::Install-Recommends "0";\nAPT::Install-Suggests "0";' > /etc/apt/apt.conf.d/01norecommend
      RUN apt-get update
      ENV DEBIAN_FRONTEND=noninteractive
      RUN apt-get -y install locales
      RUN export LC_ALL=en_US.UTF-8
      RUN export LANG=en_US.UTF-8
      RUN locale-gen en_US.UTF-8
      RUN apt-get -y install bzip2 \
      libc6-i386 \
      libprotobuf-dev \
      libxtst6 \
      libxrender-dev \
      libxext6 \
      libx11-6 \
      libfontconfig1 \
      libglib2.0-0 \
      libxext6 \
      libxrender1 \
      libxtst6 \
      libgtk2.0-0 \
      build-essential \
      net-tools \
      pkg-config \
      xauth \
      xvfb \
      bash-completion \
      ssh \
      bc \
      tmux \
      x11-utils \
      dbus-x11 \
      ca-certificates \
      libswt-gtk-4-java \
      libswt-gtk-4-jni \
      gcc-multilib \
      g++-multilib \
      git \
      vim
      RUN apt-get -y install libstdc++6:i386
      RUN apt-get -y install libgtk2.0-0:i386
      RUN apt-get -y install dpkg-dev:i386
      RUN apt-get -y install libtinfo5 libncurses5
      RUN apt-get clean autoclean
      RUN apt-get autoremove -y
      RUN ln -s /usr/bin/make /usr/bin/gmake
      gw/docker/docker_run.sh 0 → 100644
      View file @ a292404f
      #!/usr/bin/env sh
      XILINX_TOOLS=/opt/Xilinx
      docker run \
      -v "$HOME":"$HOME" \
      -v /etc/passwd:/etc/passwd:ro \
      -v /etc/shadow:/etc/shadow:ro \
      -v /etc/group:/etc/group:ro \
      -v ${XILINX_TOOLS}:${XILINX_TOOLS} \
      -v /tmp/.X11-unix:/tmp/.X11-unix \
      -v /tmp:/tmp \
      -e DISPLAY=$DISPLAY \
      --privileged \
      --net=host \
      -i -w "$PWD" -u $(id -u):$(id -g) -t --rm \
      vivado bash
      gw/functions.tcl 0 → 100644
      View file @ a292404f
      ################################################################################
      #
      # Common functions for different projects
      #
      ################################################################################
      # Write console message in red
      proc write_red { msg } {
      puts -nonewline "\033\[1;31m"
      puts $msg
      puts -nonewline "\033\[0m"
      }
      # Write console message in green
      proc write_green { msg } {
      puts -nonewline "\033\[1;32m"
      puts $msg
      puts -nonewline "\033\[0m"
      }
      # Write console message in green
      proc write_yellow { msg } {
      puts -nonewline "\033\[1;33m"
      puts $msg
      puts -nonewline "\033\[0m"
      }
      # Write console message in green
      proc write_blue { msg } {
      puts -nonewline "\033\[1;34m"
      puts $msg
      puts -nonewline "\033\[0m"
      }
      # Write console message in different colors
      proc write_msg { msg severity } {
      switch ${severity} {
      "1" {
      write_green $msg
      }
      "2" {
      write_yellow $msg
      }
      "3" {
      write_red $msg
      }
      default {
      write_blue $msg
      }
      }
      }
      # Returns the number of CPUs for the build
      # To set the build number of threads in Vivado
      proc get_number_cpus {} {
      global tcl_platform env
      switch ${tcl_platform(platform)} {
      "windows" {
      return $env(NUMBER_OF_PROCESSORS)
      }
      "unix" {
      if {![catch {open "/proc/cpuinfo"} f]} {
      set cores [regexp -all -line {^processor\s} [read $f]]
      close $f
      if {$cores > 0} {
      return $cores
      }
      }
      }
      default {
      write_msg "Unknown System" "3"
      return 1
      }
      }
      }
      # Define Vhdl src
      proc add_vhdl_src { lib src} {
      lappend ::user_list(SRC_VHDL) ${src}
      lappend ::user_list(LIB_VHDL) ${lib}
      }
      # Define Vhdl08 src
      proc add_vhdl08_src { lib src} {
      lappend ::user_list(SRC_VHDL08) ${src}
      lappend ::user_list(LIB_VHDL08) ${lib}
      }
      # Define Verilog/SystemVerilog src
      proc add_source { src } {
      lappend ::user_list(SRC_VERILOG) ${src}
      }
      # Define Constraint files
      proc add_constraint { file } {
      lappend ::user_list(CONSTRAINT) ${file}
      }
      # Define array property
      proc set_user_property { name value } {
      lappend ::user_list(PROP_NAME) ${name}
      lappend ::user_list(PROP_VAL) ${value}
      }
      # Return list
      proc get_list { list_name } {
      return [ set ::user_list(${list_name}) ]
      }
      # Return list size
      proc get_list_size { list_name } {
      return [ llength [ get_list ${list_name} ] ]
      }
      # Check if verilog source is SystemVerilog
      proc enable_sv_compilation { filename } {
      set extension [ file extension $filename ]
      if { [ string equal ${extension} ".sv" ] } {
      return 1
      } else {
      return 0
      }
      }
      gw/projects/diot_v1/constraints/diot_v1.xdc 0 → 100644
      View file @ a292404f
      ################################################################################
      #
      # Constraints for DIOT System Board Version 1
      #
      ################################################################################
      set_property PACKAGE_PIN AJ4 [get_ports sfp_rxp]
      set_property PACKAGE_PIN AJ3 [get_ports sfp_rxn]
      set_property PACKAGE_PIN AJ8 [get_ports sfp_txp]
      set_property PACKAGE_PIN AJ7 [get_ports sfp_txn]
      set_property PACKAGE_PIN K22 [get_ports {emio_i2c_scl[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {emio_i2c_scl[0]}]
      set_property PACKAGE_PIN J20 [get_ports {emio_i2c_sda[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {emio_i2c_sda[0]}]
      #gtref_clock
      set_property PACKAGE_PIN AH10 [get_ports gtrefclk_in_clk_p]
      #125 MHz
      create_clock -period 8.000 -name gt_ref_clk -waveform {0.000 4.000} [get_ports gtrefclk_in_clk_p]
      set_property IOSTANDARD LVCMOS18 [get_ports *led]
      #GPIO_LED[1]
      #From SFP_ACT_LED from schematic
      set_property PACKAGE_PIN J30 [get_ports {link_status_led[0]}]
      #GPIO_LED[2]
      #From SFP_LINK_LED from schematic
      #GPIO_LED[4]
      #From USER_LED2 from schematic
      set_property PACKAGE_PIN AL26 [get_ports pl_reset_led]
      #GPIO_LED[5]
      #From USER_LED1 from schematic
      set_property PACKAGE_PIN AT27 [get_ports {mdc_clk_led[0]}]
      set_property PACKAGE_PIN K27 [get_ports {link_sync_led[0]}]
      set_property PACKAGE_PIN A11 [get_ports {M_SCL_0[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {M_SCL_0[0]}]
      set_property PACKAGE_PIN A12 [get_ports {M_SDA_0[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {M_SDA_0[0]}]
      set_property PACKAGE_PIN H14 [get_ports {p_pres_i_0[1]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {p_pres_i_0[1]}]
      set_property PACKAGE_PIN G14 [get_ports {p_pres_i_0[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {p_pres_i_0[0]}]
      set_property PACKAGE_PIN A31 [get_ports pwr_cycle_req_o_0]
      set_property IOSTANDARD LVCMOS18 [get_ports pwr_cycle_req_o_0]
      set_property PACKAGE_PIN AL12 [get_ports {wrflash_scl[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {wrflash_scl[0]}]
      set_property PACKAGE_PIN AT15 [get_ports {wrflash_sda[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {wrflash_sda[0]}]
      set_property PACKAGE_PIN B15 [get_ports {bckpl_servmod_b[0]}]
      set_property PACKAGE_PIN A13 [get_ports {bckpl_servmod_b[1]}]
      set_property PACKAGE_PIN B13 [get_ports {bckpl_servmod_b[2]}]
      set_property PACKAGE_PIN B14 [get_ports {bckpl_servmod_b[3]}]
      set_property PACKAGE_PIN C14 [get_ports {bckpl_servmod_b[4]}]
      set_property PACKAGE_PIN C13 [get_ports {bckpl_servmod_b[5]}]
      set_property PACKAGE_PIN D14 [get_ports {bckpl_servmod_b[6]}]
      set_property PACKAGE_PIN A15 [get_ports {bckpl_servmod_b[7]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[7]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[6]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[5]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[4]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[3]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[2]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[1]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {bckpl_servmod_b[0]}]
      set_property PACKAGE_PIN H11 [get_ports bckpl_rst_n_o]
      set_property IOSTANDARD LVCMOS33 [get_ports bckpl_rst_n_o]
      set_property PACKAGE_PIN AR8 [get_ports psu_alert_i]
      set_property IOSTANDARD LVCMOS18 [get_ports psu_alert_i]
      set_property IOSTANDARD LVCMOS33 [get_ports bckpl_scl]
      set_property IOSTANDARD LVCMOS33 [get_ports bckpl_sda]
      set_property PACKAGE_PIN F15 [get_ports bckpl_scl]
      set_property PACKAGE_PIN G15 [get_ports bckpl_sda]
      set_property PULLUP true [get_ports {bckpl_servmod_b[7]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[6]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[5]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[4]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[3]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[2]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[1]}]
      set_property PULLUP true [get_ports {bckpl_servmod_b[0]}]
      set_property PACKAGE_PIN AW5 [get_ports {clk_src_sel_o[1]}]
      set_property PACKAGE_PIN AH17 [get_ports {clk_src_sel_o[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {clk_src_sel_o[1]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {clk_src_sel_o[0]}]
      set_property PACKAGE_PIN J10 [get_ports f_rst]
      set_property IOSTANDARD LVCMOS33 [get_ports f_rst]
      gw/projects/diot_v1/src/constants.vhd 0 → 100644
      View file @ a292404f
      ----------------------------------------------------------------------------------
      -- Company:
      -- Engineer:
      --
      -- Create Date: 06/28/2021 04:30:23 PM
      -- Design Name:
      -- Module Name: constants - Behavioral
      -- Project Name:
      -- Target Devices:
      -- Tool Versions:
      -- Description:
      --
      -- Dependencies:
      --
      -- Revision:
      -- Revision 0.01 - File Created
      -- Additional Comments:
      --
      ----------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      -- Uncomment the following library declaration if instantiating
      -- any Xilinx leaf cells in this code.
      --library UNISIM;
      --use UNISIM.VComponents.all;
      entity constants is
      generic (
      g_phyaddr : integer := 9;
      g_config_vector : integer := 0;
      g_config_valid : integer := 0;
      g_signal_detect : integer := 1);
      Port (
      pl_clk_i : in std_logic;
      -- Vector indicating status. We need bits 0 and 1 of the vector
      status_vector : in std_logic_vector(15 downto 0);
      -- Management clock, (<= 2.5MHz)
      mdc_i : in std_logic;
      mdc_clk_led : out std_logic;
      -- Reset of the module, coming from PS
      pl_resetn_i : in std_logic;
      reset_o : out std_logic;
      -- Autoneg
      an_config_o : out std_logic;
      an_config_vec_o : out std_logic_vector(15 downto 0);
      -- EMIO GPIOs
      p_pres_i : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o : out std_logic;
      bckpl_servmod_i : in std_logic_vector(7 downto 0);
      bckpl_servmod_o : out std_logic_vector(7 downto 0);
      bckpl_servmod_t_o : out std_logic_vector(7 downto 0);
      bckpl_rst_n_o : out std_logic;
      psu_alert_i : in std_logic;
      f_rst_i : in std_logic;
      f_rst_o : out std_logic;
      f_rst_t_o : out std_logic;
      ps_emio_o : out std_logic_vector(15 downto 0);
      ps_emio_i : in std_logic_vector(15 downto 0);
      ps_emio_t_i : in std_logic_vector(15 downto 0);
      -- I2C busses
      wrflash_i2c_irq_i : in std_logic;
      m_i2c_irq_i : in std_logic;
      bckpl_i2c_irq_i : in std_logic;
      ps_irq_o : out std_logic_vector(2 downto 0);
      -- Constants module
      -- Addr of the PHY device(slave). A constant number
      phyaddr : out std_logic_vector(4 downto 0);
      configuration_vector : out std_logic_vector(4 downto 0);
      configuration_valid : out std_logic_vector(0 downto 0);
      --'1' (if not connected to an optical module), otherwise, default is '0'
      signal_detect : out std_logic_vector(0 downto 0);
      -- Slices module
      link_status_led : out std_logic;
      link_sync_led : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0));
      end constants;
      architecture Behavioral of constants is
      -- Because we want to check if mdc_i<=2.5MHz, cnt must be up to 4096
      signal s_cnt : unsigned(11 downto 0);
      signal s_mdc_led_o : std_logic;
      type t_pwr_state is (IDLE, RST);
      signal pwr_state : t_pwr_state;
      signal ps_emio2_d0 : std_logic;
      signal ps_emio2_p : std_logic;
      begin
      an_config_o <= '0';
      an_config_vec_o <= x"D801";
      phyaddr <= std_logic_vector(to_unsigned(g_phyaddr, phyaddr'length));
      configuration_vector <= std_logic_vector(to_unsigned(g_config_vector, configuration_vector'length));
      configuration_valid <= std_logic_vector(to_unsigned(g_config_valid, configuration_valid'length));
      signal_detect <= std_logic_vector(to_unsigned(g_signal_detect, signal_detect'length));
      reset_o <= '1' when (pl_resetn_i = '0') else
      '0';
      link_status_led <= status_vector(0);
      link_sync_led <= status_vector(1);
      clk_src_sel_o <= "11";
      calc_mdc:process(mdc_i, pl_resetn_i)
      begin
      if (pl_resetn_i = '0') then
      s_cnt <= (others=>'0');
      s_mdc_led_o <= '0';
      elsif (rising_edge(mdc_i)) then
      if (s_cnt = 4096-2) then
      s_cnt <= (others=>'0');
      s_mdc_led_o <= '1';
      else
      s_mdc_led_o <= '0';
      s_cnt <= s_cnt + 1;
      end if;
      end if;
      end process;
      mdc_clk_led <= s_mdc_led_o;
      -- EMIO -> PL GPIO
      ps_emio_o(4 downto 0) <= p_pres_i(1 downto 0) & "000";
      ps_emio2_p <= '1' when (ps_emio2_d0 = '0' and ps_emio_i(2) = '1') else
      '0';
      process(pl_clk_i)
      begin
      if rising_edge(pl_clk_i) then
      ps_emio2_d0 <= ps_emio_i(2);
      if pl_resetn_i = '0' or (ps_emio2_p = '1' and ps_emio_i(1) = '1') then
      pwr_state <= IDLE;
      pwr_cycle_req_o <= '0';
      else
      if pwr_state = IDLE then
      pwr_cycle_req_o <= '0';
      if ps_emio2_p = '1' and ps_emio_i(1) = '0' then
      pwr_state <= RST;
      end if;
      elsif pwr_state = RST then
      pwr_cycle_req_o <= '1';
      end if;
      end if;
      end if;
      end process;
      -- EMIO 83..90
      ps_emio_o(12 downto 5) <= bckpl_servmod_i(7 downto 0);
      bckpl_servmod_o(7 downto 0) <= ps_emio_i(12 downto 5);
      bckpl_servmod_t_o(7 downto 0) <= ps_emio_t_i(12 downto 5);
      -- EMIO 91
      ps_emio_o(13) <= ps_emio_i(13);
      bckpl_rst_n_o <= ps_emio_i(13);
      -- EMIO 92
      ps_emio_o(14) <= psu_alert_i;
      -- EMIO 93
      ps_emio_o(15) <= f_rst_i;
      f_rst_o <= ps_emio_i(15);
      f_rst_t_o <= ps_emio_t_i(15);
      -- I2C irqs
      ps_irq_o(2 downto 0) <= bckpl_i2c_irq_i & m_i2c_irq_i & wrflash_i2c_irq_i;
      end Behavioral;
      gw/projects/diot_v1/src/diot_v1_top.vhd 0 → 100644
      View file @ a292404f
      --==============================================================================
      --! @file diot_v1_top.vhd
      --==============================================================================
      --------------------------------------------------------------------------------
      -- --
      -- CERN - DIOT V1 --
      -- --
      --------------------------------------------------------------------------------
      --
      -- unit name: diot_v1_top
      --
      --! @brief top level DIOT system board Version 1 based in ZynqMP+
      --
      --! @author alen.arias.vazquez@cern.ch
      --
      --! @date 05/04/2022
      --
      --------------------------------------------------------------------------------
      library ieee;
      library unisim;
      use ieee.std_logic_1164.all;
      use unisim.vcomponents.all;
      --==============================================================================
      --! Entity declaration for diot_v1_top
      --==============================================================================
      entity diot_v1_top is
      port (
      emio_i2c_scl : inout std_logic_vector(0 downto 0);
      emio_i2c_sda : inout std_logic_vector(0 downto 0);
      M_SCL_0 : inout std_logic_vector(0 downto 0);
      M_SDA_0 : inout std_logic_vector(0 downto 0);
      wrflash_scl : inout std_logic_vector(0 downto 0);
      wrflash_sda : inout std_logic_vector(0 downto 0);
      gtrefclk_in_clk_n : in std_logic;
      gtrefclk_in_clk_p : in std_logic;
      link_status_led : out std_logic_vector(0 downto 0);
      link_sync_led : out std_logic_vector(0 downto 0);
      mdc_clk_led : out std_logic_vector(0 downto 0);
      pl_reset_led : out std_logic;
      p_pres_i_0 : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o_0 : out std_logic;
      bckpl_servmod_b : inout std_logic_vector(7 downto 0);
      bckpl_rst_n_o : out std_logic;
      bckpl_scl : inout std_logic;
      bckpl_sda : inout std_logic;
      psu_alert_i : in std_logic;
      f_rst : inout std_logic;
      sfp_rxn : in std_logic;
      sfp_rxp : in std_logic;
      sfp_txn : out std_logic;
      sfp_txp : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0)
      );
      end diot_v1_top;
      --==============================================================================
      --! Architecture declaration
      --==============================================================================
      architecture structure of diot_v1_top is
      component diot_v1 is
      port (
      link_status_led : out std_logic_vector(0 downto 0);
      link_sync_led : out std_logic_vector(0 downto 0);
      mdc_clk_led : out std_logic_vector(0 downto 0);
      emio_i2c_sda : inout std_logic_vector(0 downto 0);
      emio_i2c_scl : inout std_logic_vector(0 downto 0);
      M_SDA_0 : inout std_logic_vector(0 downto 0);
      M_SCL_0 : inout std_logic_vector(0 downto 0);
      wrflash_scl : inout std_logic_vector(0 downto 0);
      wrflash_sda : inout std_logic_vector(0 downto 0);
      pl_reset_led : out std_logic;
      gtrefclk_in_clk_n : in std_logic;
      gtrefclk_in_clk_p : in std_logic;
      p_pres_i_0 : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o_0 : out std_logic;
      bckpl_servmod_b : inout std_logic_vector(7 downto 0);
      bckpl_rst_n_o : out std_logic;
      bckpl_scl : inout std_logic_vector(0 downto 0);
      bckpl_sda : inout std_logic_vector(0 downto 0);
      psu_alert_i : in std_logic;
      f_rst : inout std_logic_vector(0 downto 0);
      sfp_rxn : in std_logic;
      sfp_rxp : in std_logic;
      sfp_txn : out std_logic;
      sfp_txp : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0)
      );
      end component diot_v1;
      --==============================================================================
      --! Architecture begin
      --==============================================================================
      begin
      design_1_i: component diot_v1
      port map (
      emio_i2c_scl(0) => emio_i2c_scl(0),
      emio_i2c_sda(0) => emio_i2c_sda(0),
      M_SCL_0(0) => M_SCL_0(0),
      M_SDA_0(0) => M_SDA_0(0),
      wrflash_scl(0) => wrflash_scl(0),
      wrflash_sda(0) => wrflash_sda(0),
      gtrefclk_in_clk_n => gtrefclk_in_clk_n,
      gtrefclk_in_clk_p => gtrefclk_in_clk_p,
      link_status_led(0) => link_status_led(0),
      link_sync_led(0) => link_sync_led(0),
      mdc_clk_led(0) => mdc_clk_led(0),
      pl_reset_led => pl_reset_led,
      p_pres_i_0 => p_pres_i_0,
      pwr_cycle_req_o_0 => pwr_cycle_req_o_0,
      bckpl_servmod_b => bckpl_servmod_b,
      bckpl_rst_n_o => bckpl_rst_n_o,
      bckpl_scl(0) => bckpl_scl,
      bckpl_sda(0) => bckpl_sda,
      psu_alert_i => psu_alert_i,
      f_rst(0) => f_rst,
      sfp_rxn => sfp_rxn,
      sfp_rxp => sfp_rxp,
      sfp_txn => sfp_txn,
      sfp_txp => sfp_txp,
      clk_src_sel_o => clk_src_sel_o
      );
      end architecture structure;
      --==============================================================================
      -- architecture end
      --==============================================================================
      gw/projects/diot_v1/tcl/create_bd.tcl 0 → 100644
      View file @ a292404f
      This diff is collapsed.
      gw/projects/diot_v1/tcl/project_cfg.tcl 0 → 100644
      View file @ a292404f
      # Custom project settings
      set reference_part "xczu7cg-ffvf1517-1-e"
      set project_name "diot_v1"
      set entity_top "diot_v1_top"
      # Hardcoded to 8 to work fine in CI set max_threads [get_number_cpus]
      set max_threads 8
      set project_language "VHDL"
      set lib_default xil_defaultlib
      # Add properties
      set_user_property "default_lib" "xil_defaultlib"
      set_user_property "enable_vhdl_2008" "1"
      set_user_property "xpm_libraries" "XPM_CDC XPM_FIFO XPM_MEMORY"
      # Top Level
      add_vhdl_src ${lib_default} ../src/${entity_top}.vhd
      # Vhdl Src
      add_vhdl_src ${lib_default} ../src/constants.vhd
      # Add Constraints
      add_constraint diot_v1.xdc
      gw/projects/diot_v1/tcl/ps_cfg.tcl 0 → 100644
      View file @ a292404f
      This diff is collapsed.
      gw/projects/diot_v2/constraints/diot_v2.xdc 0 → 100644
      View file @ a292404f
      # ##############################################################################
      #
      # Constraints for DIOT System Board Version 2
      #
      # ##############################################################################
      # ------------------------------------------------------------------------------
      # GT REG CLK: 125 MHz
      set_property PACKAGE_PIN AH10 [get_ports {gtrefclk_in_clk_p}]
      create_clock -period 8.000 -name gt_ref_clk -waveform {0.000 4.000} [get_ports {gtrefclk_in_clk_p}]
      # ------------------------------------------------------------------------------
      # Clock Selector
      set_property -dict {PACKAGE_PIN AW5 IOSTANDARD LVCMOS18} [get_ports {clk_src_sel_o[1]}]
      set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVCMOS18} [get_ports {clk_src_sel_o[0]}]
      # ------------------------------------------------------------------------------
      # Power Cycle Request
      set_property -dict {PACKAGE_PIN A31 IOSTANDARD LVCMOS18} [get_ports {pwr_cycle_req_o_0}]
      # ------------------------------------------------------------------------------
      # BUS Monitor
      set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports {f_rst_b}]
      set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {p_pres_i_0[0]}]
      set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {p_pres_i_0[1]}]
      # ------------------------------------------------------------------------------
      # LEDs:
      # SFP_ACT_LED
      set_property -dict {PACKAGE_PIN J30 IOSTANDARD LVCMOS18} [get_ports {link_status_led}]
      # From USER_LED2 from schematic
      set_property -dict {PACKAGE_PIN AL26 IOSTANDARD LVCMOS18} [get_ports {pl_reset_led}]
      # From USER_LED1 from schematic
      set_property -dict {PACKAGE_PIN AT27 IOSTANDARD LVCMOS18} [get_ports {mdc_clk_led}]
      set_property -dict {PACKAGE_PIN K27 IOSTANDARD LVCMOS18} [get_ports {link_sync_led}]
      # ------------------------------------------------------------------------------
      # PSU Alert
      set_property -dict {PACKAGE_PIN AR8 IOSTANDARD LVCMOS18} [get_ports {psu_alert_i}]
      # ------------------------------------------------------------------------------
      # I2C EMIO
      set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS18} [get_ports {emio_scl_b}]
      set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS18} [get_ports {emio_sda_b}]
      # ------------------------------------------------------------------------------
      # I2C wr Flash
      set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS18} [get_ports {wrflash_scl_b}]
      set_property -dict {PACKAGE_PIN AT15 IOSTANDARD LVCMOS18} [get_ports {wrflash_sda_b}]
      # ------------------------------------------------------------------------------
      # I2C Backplane
      set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN F15} [get_ports {bckpl_scl_b}]
      set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN G15} [get_ports {bckpl_sda_b}]
      # ------------------------------------------------------------------------------
      # SFP
      set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS33} [get_ports {tx_disable_o}]
      set_property PACKAGE_PIN AJ4 [get_ports sfp_rxp]
      set_property PACKAGE_PIN AJ3 [get_ports sfp_rxn]
      set_property PACKAGE_PIN AJ8 [get_ports sfp_txp]
      set_property PACKAGE_PIN AJ7 [get_ports sfp_txn]
      # ------------------------------------------------------------------------------
      # Backplain
      set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[0]}]
      set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[1]}]
      set_property -dict {PACKAGE_PIN B13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[2]}]
      set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[3]}]
      set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[4]}]
      set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[5]}]
      set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[6]}]
      set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {bckpl_servmod_b[7]}]
      set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports {bckpl_rst_n_o}]
      gw/projects/diot_v2/src/constants.vhd 0 → 100644
      View file @ a292404f
      ----------------------------------------------------------------------------------
      -- Company:
      -- Engineer:
      --
      -- Create Date: 06/28/2021 04:30:23 PM
      -- Design Name:
      -- Module Name: constants - Behavioral
      -- Project Name:
      -- Target Devices:
      -- Tool Versions:
      -- Description:
      --
      -- Dependencies:
      --
      -- Revision:
      -- Revision 0.01 - File Created
      -- Additional Comments:
      --
      ----------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      --==============================================================================
      --! Entity declaration for constants
      --==============================================================================
      entity constants is
      generic (
      g_phyaddr : integer := 9;
      g_config_vector : integer := 0;
      g_config_valid : integer := 0;
      g_signal_detect : integer := 1
      );
      port (
      pl_clk_i : in std_logic;
      --! Vector indicating status. We need bits 0 and 1 of the vector
      status_vector : in std_logic_vector(15 downto 0);
      --! Management clock, (<= 2.5MHz)
      mdc_i : in std_logic;
      mdc_clk_led : out std_logic;
      --! Reset of the module, coming from PS
      pl_resetn_i : in std_logic;
      reset_o : out std_logic;
      --! Autoneg
      an_config_o : out std_logic;
      an_config_vec_o : out std_logic_vector(15 downto 0);
      tx_disable_o : out std_logic;
      --! EMIO GPIOs
      p_pres_i : in std_logic_vector(1 downto 0);
      pwr_cycle_req_o : out std_logic;
      bckpl_servmod_i : in std_logic_vector(7 downto 0);
      bckpl_servmod_o : out std_logic_vector(7 downto 0);
      bckpl_servmod_t_o : out std_logic_vector(7 downto 0);
      bckpl_rst_n_o : out std_logic;
      psu_alert_i : in std_logic;
      f_rst_i : in std_logic;
      f_rst_o : out std_logic;
      f_rst_t_o : out std_logic;
      ps_emio_o : out std_logic_vector(15 downto 0);
      ps_emio_i : in std_logic_vector(15 downto 0);
      ps_emio_t_i : in std_logic_vector(15 downto 0);
      --! I2C busses
      wrflash_i2c_irq_i : in std_logic;
      bckpl_i2c_irq_i : in std_logic;
      ps_irq_o : out std_logic_vector(1 downto 0);
      --! Constants module
      --! Addr of the PHY device(slave). A constant number
      phyaddr : out std_logic_vector(4 downto 0);
      configuration_vector : out std_logic_vector(4 downto 0);
      configuration_valid : out std_logic_vector(0 downto 0);
      --!'1' (if not connected to an optical module), otherwise, default is '0'
      signal_detect : out std_logic_vector(0 downto 0);
      --! Slices module
      link_status_led : out std_logic;
      link_sync_led : out std_logic;
      clk_src_sel_o : out std_logic_vector(1 downto 0)
      );
      end constants;
      --==============================================================================
      --! Architecture declaration
      --==============================================================================
      architecture Behavioral of constants is
      --! Because we want to check if mdc_i<=2.5MHz, cnt must be up to 4096
      signal s_cnt : unsigned(11 downto 0);
      signal s_mdc_led_o : std_logic;
      type t_pwr_state is (IDLE, RST);
      signal pwr_state : t_pwr_state;
      signal ps_emio2_d0 : std_logic;
      signal ps_emio2_p : std_logic;
      --==============================================================================
      --! Architecture begin
      --==============================================================================
      begin
      an_config_o <= '0';
      an_config_vec_o <= x"D801";
      tx_disable_o <= '0';
      phyaddr <= std_logic_vector(to_unsigned(g_phyaddr, phyaddr'length));
      configuration_vector <= std_logic_vector(to_unsigned(g_config_vector, configuration_vector'length));
      configuration_valid <= std_logic_vector(to_unsigned(g_config_valid, configuration_valid'length));
      signal_detect <= std_logic_vector(to_unsigned(g_signal_detect, signal_detect'length));
      reset_o <= '1' when (pl_resetn_i = '0') else '0';
      link_status_led <= status_vector(0);
      link_sync_led <= status_vector(1);
      clk_src_sel_o <= "11";
      p_calc_mdc: process(mdc_i, pl_resetn_i)
      begin
      if (pl_resetn_i = '0') then
      s_cnt <= (others=>'0');
      s_mdc_led_o <= '0';
      elsif (rising_edge(mdc_i)) then
      if (s_cnt = 4096-2) then
      s_cnt <= (others=>'0');
      s_mdc_led_o <= '1';
      else
      s_mdc_led_o <= '0';
      s_cnt <= s_cnt + 1;
      end if;
      end if;
      end process p_calc_mdc;
      mdc_clk_led <= s_mdc_led_o;
      --! EMIO -> PL GPIO
      ps_emio_o(4 downto 0) <= p_pres_i(1 downto 0) & "000";
      ps_emio2_p <= '1' when (ps_emio2_d0 = '0' and ps_emio_i(2) = '1') else '0';
      p_pwr: process(pl_clk_i)
      begin
      if rising_edge(pl_clk_i) then
      ps_emio2_d0 <= ps_emio_i(2);
      if pl_resetn_i = '0' or (ps_emio2_p = '1' and ps_emio_i(1) = '1') then
      pwr_state <= IDLE;
      pwr_cycle_req_o <= '0';
      else
      if pwr_state = IDLE then
      pwr_cycle_req_o <= '0';
      if ps_emio2_p = '1' and ps_emio_i(1) = '0' then
      pwr_state <= RST;
      end if;
      elsif pwr_state = RST then
      pwr_cycle_req_o <= '1';
      end if;
      end if;
      end if;
      end process p_pwr;
      --! EMIO 83..90
      ps_emio_o(12 downto 5) <= bckpl_servmod_i(7 downto 0);
      bckpl_servmod_o(7 downto 0) <= ps_emio_i(12 downto 5);
      bckpl_servmod_t_o(7 downto 0) <= ps_emio_t_i(12 downto 5);
      --! EMIO 91
      ps_emio_o(13) <= ps_emio_i(13);
      bckpl_rst_n_o <= ps_emio_i(13);
      --! EMIO 92
      ps_emio_o(14) <= psu_alert_i;
      --! EMIO 93
      ps_emio_o(15) <= f_rst_i;
      f_rst_o <= ps_emio_i(15);
      f_rst_t_o <= ps_emio_t_i(15);
      --! I2C irqs
      ps_irq_o(1 downto 0) <= bckpl_i2c_irq_i & wrflash_i2c_irq_i;
      end Behavioral;
      --==============================================================================
      -- architecture end
      --==============================================================================
      gw/projects/diot_v2/src/diot_v2_top.vhd 0 → 100644
      View file @ a292404f
      This diff is collapsed.
      gw/projects/diot_v2/tcl/create_bd.tcl 0 → 100644
      View file @ a292404f
      This diff is collapsed.
      gw/projects/diot_v2/tcl/project_cfg.tcl 0 → 100644
      View file @ a292404f
      # Custom project settings
      set reference_part "xczu7cg-ffvf1517-1-e"
      set project_name "diot_v2"
      set entity_top "diot_v2_top"
      # Hardcoded to 8 to work fine in CI set max_threads [get_number_cpus]
      set max_threads 8
      set project_language "VHDL"
      set lib_default xil_defaultlib
      # Common IP directory
      set COMMON_IP ../../../common-ip
      # Add properties
      set_user_property "default_lib" "xil_defaultlib"
      set_user_property "enable_vhdl_2008" "1"
      set_user_property "xpm_libraries" "XPM_CDC XPM_FIFO XPM_MEMORY"
      # Top Level
      add_vhdl_src ${lib_default} ../src/${entity_top}.vhd
      # Vhdl Src
      add_vhdl_src ${lib_default} ../src/constants.vhd
      # Add Constraints
      add_constraint diot_v2.xdc
      gw/projects/diot_v2/tcl/ps_cfg.tcl 0 → 100644
      View file @ a292404f
      This diff is collapsed.
      sw/Makefile
      View file @ a292404f
      ......@@ -43,7 +43,7 @@ endif
      DTC_BIN=artifacts/dtc
      GW_XSA=gw/hw_v$(SB_VER)/diot_sb_golden_hw_v$(SB_VER).xsa
      GW_XSA=../gw/output_files/diot_v$(SB_VER)/diot_v$(SB_VER).xsa
      export CROSS_COMPILE=aarch64-none-elf-
      export ARCH=aarch64
      CROSS_COMPILE_MICROBLAZE=mb-
      ......@@ -111,7 +111,6 @@ fetch: \
      # check the availability of commands
      $(XSCT_BIN) $(BOOTGEN_BIN) $(PETALINUX_BUILD_BIN) $(PETALINUX_CONFIG_BIN):
      $(if $(shell which $@),,$(error "$(@) not found"))
      ############################## u-boot #########################################
      ......@@ -231,12 +230,12 @@ fsbl_config: bootfw_patch $(XSCT_BIN) $(GW_XSA)
      $(VT)echo -e "$(CO)Configuring fsbl...$(NC)" $(LOGT)
      # gives erros like:
      # WARNING: sysconfig command is DEPRECATED.
      #
      #
      # Only one system configuration will be allowed in a platform.
      # If no system configuration is present, creating a domain will create the system configuration.
      #
      # ERROR:set_bsp_conf set periph_type_overrides {{BOARD template}}: Cannot set Property "periph_type_overrides" with {BOARD template}
      #
      #
      # ERROR:set_bsp_conf set periph_type_overrides {{BOARD template}}: Cannot set Property "periph_type_overrides" with {BOARD template}
      #
      # ERROR: Could not find the bsp config parameter.
      # to get the list of valida parameters on "os" run "bsp listparams -os"
      # to get the list of valida parameters on "processor" instance run "bsp listparams -proc"
      ......@@ -289,12 +288,12 @@ pmufw_config: bootfw_patch $(XSCT_BIN) $(GW_XSA)
      $(VT)echo -e "$(CO)Configuring pmufw...$(NC)" $(LOGT)
      # gives erros like:
      # WARNING: sysconfig command is DEPRECATED.
      #
      #
      # Only one system configuration will be allowed in a platform.
      # If no system configuration is present, creating a domain will create the system configuration.
      #
      # ERROR:set_bsp_conf set periph_type_overrides {{BOARD template}}: Cannot set Property "periph_type_overrides" with {BOARD template}
      #
      #
      # ERROR:set_bsp_conf set periph_type_overrides {{BOARD template}}: Cannot set Property "periph_type_overrides" with {BOARD template}
      #
      # ERROR: Could not find the bsp config parameter.
      # to get the list of valida parameters on "os" run "bsp listparams -os"
      # to get the list of valida parameters on "processor" instance run "bsp listparams -proc"
      ......@@ -655,7 +654,6 @@ bootbin_distclean:
      $(V) rm -f _done/bootbin_artifacts _done/bootbin_build _done/bootbin_config $(LOG)
      $(VT)echo -e "$(CO)Distclean boot.bin... done$(NC)" $(LOGT)
      ############################## boot image (image.ub) ##########################
      image_ub: image_ub_artifacts
      ......
      sw/configs/linux/linux_config
      View file @ a292404f
      ......@@ -1914,8 +1914,8 @@ CONFIG_VT_CONSOLE_SLEEP=y
      CONFIG_HW_CONSOLE=y
      CONFIG_VT_HW_CONSOLE_BINDING=y
      CONFIG_UNIX98_PTYS=y
      CONFIG_LEGACY_PTYS=y
      CONFIG_LEGACY_PTY_COUNT=256
      # CONFIG_LEGACY_PTYS is not set
      # CONFIG_LEGACY_PTY_COUNT is not set
      # CONFIG_SERIAL_NONSTANDARD is not set
      # CONFIG_NOZOMI is not set
      # CONFIG_N_GSM is not set
      ......
      sw/gw/hw_v1/diot_sb_golden_hw_v1.xsa deleted 120000 → 0
      View file @ bd1726df
      ../../gw_all/diot_sb_v1_golden_211215.xsa
      \ No newline at end of file
      sw/gw/hw_v2/diot_sb_golden_hw_v2.xsa deleted 120000 → 0
      View file @ bd1726df
      ../../gw_all/diot_sb_v2_golden_211217.xsa
      \ No newline at end of file
      sw/petalinux/project-spec/meta-user/recipes-apps/diot-util/diot-util.bb
      View file @ a292404f
      ......@@ -32,6 +32,8 @@ SRC_URI = " \
      file://term.h \
      file://util.c \
      file://util.h \
      file://fpga_device.h \
      file://fpga_device.c \
      "
      DEPENDS = "libgpiod readline lmsensors i2c-tools"
      ......@@ -47,7 +49,6 @@ do_compile() {
      do_install() {
      install -d ${D}${bindir}
      install -m 0755 ${S}/diot_util ${D}${bindir}
      }
      do_compile_prepend() {
      ......
      sw/petalinux/project-spec/meta-user/recipes-apps/diot-util/files/Makefile
      View file @ a292404f
      ......@@ -13,6 +13,7 @@ APP_OBJS = \
      fru_utils.o \
      term.o \
      util.o \
      fpga_device.o \
      LDLIBS+=-lgpiod -lreadline -lsensors -li2c
      CFLAGS+=-Wall -ggdb -g -O2 \
      ......
      sw/petalinux/project-spec/meta-user/recipes-apps/diot-util/files/diot_util.c
      View file @ a292404f
      ......@@ -29,6 +29,7 @@
      #include "util.h"
      #include "fru_utils.h"
      #include "fpga_device.h"
      #define DTB_HW_VER_FILE "/sys/firmware/devicetree/base/chosen/hw_ver"
      #define DTB_MODEBOOT_FILE "/sys/firmware/devicetree/base/chosen/modeboot"
      ......@@ -38,6 +39,8 @@
      #define READLINE_PROMPT "diot_util> "
      #define FPGA_DEVICE_ADDR 0x80000000
      #define RED_CHECK(x) x ? COLOR_RED: ""
      #define RED_OFF(x) x ? COLOR_OFF: ""
      ......@@ -70,7 +73,6 @@ struct string_map boot_mode_db[] = {
      { "nandboot", "nand" },
      };
      struct command_entry commands_list[] = {
      { .cmd_name = "status", .cmd_func = cmd_print_status, .cmd_help_string = "Print status\n", .cmd_params = NULL},
      { .cmd_name = "exit", .cmd_func = cmd_exit, .cmd_help_string = "quit program\n", .cmd_params = NULL},
      ......@@ -88,25 +90,33 @@ struct command_entry commands_list[] = {
      { .cmd_name = "fantray", .cmd_func = cmd_fantray, .cmd_help_string = "Commands for fantray module. Type \"help "
      "fantray\" for more information about "
      "subcommands\n", .cmd_params = NULL},
      { .cmd_name = "gateware", .cmd_func = cmd_fpga, .cmd_help_string = "Print information related to the gateware. Type help for more information\n", .cmd_params = NULL},
      { .cmd_name = NULL }
      };
      int cmd_help(char *params)
      {
      struct command_entry *entry = commands_list;
      struct command_entry *entry;
      char buf[50];
      /* Print fantray's help if requested */
      if (params && !strncmp(params, "fantray", strlen("fantray")))
      entry = commands_list_fantray;
      printf("diot_util for HW version %d\n", SB_VER);
      printf("Avaiable commands:\n");
      printf("Available commands:\n");
      if (params && !strncmp(params, "fantray", strlen("fantray"))) {
      /* Print fantray's help if requested */
      entry = commands_list_fantray;
      } else if (params && !strncmp(params, "gateware", strlen("gateware"))) {
      /* Print gateware if requested */
      entry = commands_list_fpga_device;
      } else {
      entry = commands_list;
      }
      while (entry->cmd_name) {
      sprintf(buf, "%s %s", entry->cmd_name,
      entry->cmd_params ? entry->cmd_params : "");
      printf("%-18s - %s", buf, entry->cmd_help_string);
      entry++;
      sprintf(buf, "%s %s", entry->cmd_name,
      entry->cmd_params ? entry->cmd_params : "");
      printf("%-18s - %s", buf, entry->cmd_help_string);
      entry++;
      }
      return 0;
      ......@@ -379,6 +389,9 @@ int cmd_print_status(char *params)
      printf("----------------------------+--------------+\n");
      printf("\n");
      get_fpga_status(false);
      printf("\n");
      print_slot_status();
      printf("\n");
      print_fmc_status();
      ......@@ -476,7 +489,7 @@ int main(int argc, char **argv)
      /* Copy command like readline would do */
      line_read = strndup(curr_script_cmd, cmd_len);
      }
      } else {
      } else {
      /* Get a line from the user. */
      line_read = readline (READLINE_PROMPT);
      }
      ......@@ -536,6 +549,9 @@ int main(int argc, char **argv)
      char *
      command_name_generator_fantray(const char *text, int state);
      char *
      command_name_generator_gateware(const char *text, int state);
      char **
      command_completion(const char *text, int start, int end)
      {
      ......@@ -543,13 +559,17 @@ command_completion(const char *text, int start, int end)
      rl_attempted_completion_over = 1;
      /* Call completion function if the first word */
      if (start == 0)
      return rl_completion_matches(text, command_name_generator);
      if (start == 0){
      return rl_completion_matches(text, command_name_generator);
      }
      if (!strncmp(rl_line_buffer, "fantray load_fw", strlen("fantray load_fw"))) {
      return rl_completion_matches(text, rl_filename_completion_function);
      return rl_completion_matches(text, rl_filename_completion_function);
      }
      if (!strncmp(rl_line_buffer, "fantray", strlen("fantray"))) {
      return rl_completion_matches(text, command_name_generator_fantray);
      return rl_completion_matches(text, command_name_generator_fantray);
      }
      if (!strncmp(rl_line_buffer, "gateware", strlen("gateware"))) {
      return rl_completion_matches(text, command_name_generator_gateware);
      }
      return NULL;
      }
      ......@@ -593,3 +613,23 @@ char *command_name_generator_fantray(const char *text, int state)
      return NULL;
      }
      /* command name generator for gateware */
      char *command_name_generator_gateware(const char *text, int state)
      {
      static int list_index, len;
      char *name;
      if (!state) {
      list_index = 0;
      len = strlen(text);
      }
      while ((commands_list_fpga_device[list_index].cmd_name) && (name = commands_list_fpga_device[list_index++].cmd_name)) {
      if (strncmp(name, text, len) == 0) {
      return strdup(name);
      }
      }
      return NULL;
      }
      \ No newline at end of file
      sw/petalinux/project-spec/meta-user/recipes-apps/diot-util/files/fpga_device.h 0 → 100644
      View file @ a292404f
      /** @file fpga_device.h
      *
      * @brief Library for FPGA device Convention
      *
      * @author alen.arias.vazquez@cern.ch
      * @date 12/05/2022
      * @url https://ohwr.org/project/fpga-dev-id/wikis/home
      *
      */
      #ifndef __FPGA_DEVICE_H
      #define __FPGA_DEVICE_H
      #ifdef __cplusplus
      extern "C" {
      #endif
      /***************************** Include Files **********************************/
      #include <limits.h>
      #include <stdlib.h>
      #include <stdio.h>
      #include <stdint.h>
      #include <string.h>
      #include <time.h>
      #include <unistd.h>
      #include <byteswap.h>
      #include <fcntl.h>
      #include <sys/stat.h>
      #include <sys/mman.h>
      #include <errno.h>
      #include <stdbool.h>
      #include "diot_util.h"
      /************************** Constant Definitions ******************************/
      /***************** Macros (Inline Functions) Definitions **********************/
      #define c_ADDR_VENDOR_ID 0x00
      #define c_ADDR_DEVICE_ID 0x01
      #define c_ADDR_VERSION 0x02
      #define c_ADDR_BYTE_ORD_MARK 0x03
      #define c_ADDR_SOURCE_ID_0 0x04
      #define c_ADDR_SOURCE_ID_1 0x05
      #define c_ADDR_SOURCE_ID_2 0x06
      #define c_ADDR_SOURCE_ID_3 0x07
      #define c_ADDR_CAP_MASK 0x08
      #define c_ADDR_VENDOR_UUID_0 0x0C
      #define c_ADDR_VENDOR_UUID_1 0x0D
      #define c_ADDR_VENDOR_UUID_2 0x0E
      #define c_ADDR_VENDOR_UUID_3 0x0F
      #define c_ADDR_CORE_ID 0x10
      #define c_ADDR_NAME_LSB 0x11
      #define c_ADDR_NAME_MSB 0x12
      #define c_ADDR_BUILD_T 0x13
      #define c_ADDR_HASH_0 0x14
      #define c_ADDR_HASH_1 0x15
      #define c_ADDR_HASH_2 0x16
      #define c_ADDR_HASH_3 0x17
      #define c_ADDR_HASH_4 0x18
      #define c_ADDR_DNA_0 0x19
      #define c_ADDR_DNA_1 0x1A
      #define c_ADDR_DNA_2 0x1B
      #define c_ADDR_TAG_LSB 0x1C
      #define c_ADDR_TAG_MSB 0x1D
      #define c_ADDR_IP_CORE 0x80000000
      #define c_SIZE_BYTES c_ADDR_TAG_MSB*4
      /**************************** Type Definitions ********************************/
      /******************************** Structs *************************************/
      extern struct command_entry commands_list_fpga_device[];
      /************************** Variable Definitions ******************************/
      /************************** Function Prototypes *******************************/
      int cmd_fpga (char *params);
      int get_fpga_status(bool full_info);
      #ifdef __cplusplus
      }
      #endif
      #endif /* __FPGA_DEVICE_H */
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