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DIOT Zynq Ultrascale-based System Board
Commits
44244476
Commit
44244476
authored
Oct 07, 2022
by
Grzegorz Daniluk
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gw: drive low unused FanTray/Monimod SWD pins for proper power-cycling
parent
a292404f
Pipeline
#4002
passed with stages
in 125 minutes and 30 seconds
Changes
4
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1
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4 changed files
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18 additions
and
0 deletions
+18
-0
diot_v2.xdc
gw/projects/diot_v2/constraints/diot_v2.xdc
+2
-0
constants.vhd
gw/projects/diot_v2/src/constants.vhd
+6
-0
diot_v2_top.vhd
gw/projects/diot_v2/src/diot_v2_top.vhd
+6
-0
create_bd.tcl
gw/projects/diot_v2/tcl/create_bd.tcl
+4
-0
No files found.
gw/projects/diot_v2/constraints/diot_v2.xdc
View file @
44244476
...
...
@@ -23,6 +23,8 @@ set_property -dict {PACKAGE_PIN A31 IOSTANDARD LVCMOS18} [get_ports {pwr_cycle_r
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports {f_rst_b}]
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS33} [get_ports {p_pres_i_0[0]}]
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports {p_pres_i_0[1]}]
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS33} [get_ports {f_swclk_o}]
set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS33} [get_ports {f_swdio_o}]
# ------------------------------------------------------------------------------
# LEDs:
...
...
gw/projects/diot_v2/src/constants.vhd
View file @
44244476
...
...
@@ -58,6 +58,8 @@ entity constants is
f_rst_i
:
in
std_logic
;
f_rst_o
:
out
std_logic
;
f_rst_t_o
:
out
std_logic
;
f_swclk_o
:
out
std_logic
;
f_swdio_o
:
out
std_logic
;
ps_emio_o
:
out
std_logic_vector
(
15
downto
0
);
ps_emio_i
:
in
std_logic_vector
(
15
downto
0
);
ps_emio_t_i
:
in
std_logic_vector
(
15
downto
0
);
...
...
@@ -100,6 +102,10 @@ begin
an_config_o
<=
'0'
;
an_config_vec_o
<=
x"D801"
;
tx_disable_o
<=
'0'
;
-- FanTray SWD currently not used, so drive it to 0 to avoid powering
-- FanTray through I/Os when power cycling monimod.
f_swclk_o
<=
'0'
;
f_swdio_o
<=
'0'
;
phyaddr
<=
std_logic_vector
(
to_unsigned
(
g_phyaddr
,
phyaddr
'length
));
configuration_vector
<=
std_logic_vector
(
to_unsigned
(
g_config_vector
,
configuration_vector
'length
));
...
...
gw/projects/diot_v2/src/diot_v2_top.vhd
View file @
44244476
...
...
@@ -29,6 +29,8 @@ use unisim.vcomponents.all;
entity
diot_v2_top
is
port
(
f_rst_b
:
inout
std_logic
;
f_swclk_o
:
out
std_logic
;
f_swdio_o
:
out
std_logic
;
psu_alert_i
:
in
std_logic
;
p_pres_i_0
:
in
std_logic_vector
(
1
downto
0
);
pwr_cycle_req_o_0
:
out
std_logic
;
...
...
@@ -65,6 +67,8 @@ architecture structure of diot_v2_top is
f_rst_i
:
in
std_logic
;
f_rst_o
:
out
std_logic
;
f_rst_t
:
out
std_logic
;
f_swclk_o
:
out
std_logic
;
f_swdio_o
:
out
std_logic
;
psu_alert_i
:
in
std_logic
;
p_pres_i_0
:
in
std_logic_vector
(
1
downto
0
);
pwr_cycle_req_o_0
:
out
std_logic
;
...
...
@@ -227,6 +231,8 @@ begin
f_rst_i
=>
s_f_rst_i
,
f_rst_o
=>
s_f_rst_o
,
f_rst_t
=>
s_f_rst_t
,
f_swclk_o
=>
f_swclk_o
,
f_swdio_o
=>
f_swdio_o
,
psu_alert_i
=>
psu_alert_i
,
p_pres_i_0
=>
p_pres_i_0
,
pwr_cycle_req_o_0
=>
pwr_cycle_req_o_0
,
...
...
gw/projects/diot_v2/tcl/create_bd.tcl
View file @
44244476
...
...
@@ -37,6 +37,8 @@ proc create_block_design { parentCell design_name target_path } {
set f_rst_i
[
create_bd_port -dir I f_rst_i
]
set f_rst_o
[
create_bd_port -dir O f_rst_o
]
set f_rst_t
[
create_bd_port -dir O f_rst_t
]
set f_swclk_o
[
create_bd_port -dir O f_swclk_o
]
set f_swdio_o
[
create_bd_port -dir O f_swdio_o
]
set p_pres_i_0
[
create_bd_port -dir I -from 1 -to 0 p_pres_i_0
]
# PSU alert
...
...
@@ -173,6 +175,8 @@ proc create_block_design { parentCell design_name target_path } {
connect_bd_net
[
get_bd_pins constants_and_slices/f_rst_i
]
[
get_bd_ports f_rst_i
]
connect_bd_net
[
get_bd_pins constants_and_slices/f_rst_o
]
[
get_bd_ports f_rst_o
]
connect_bd_net
[
get_bd_pins constants_and_slices/f_rst_t_o
]
[
get_bd_ports f_rst_t
]
connect_bd_net
[
get_bd_pins constants_and_slices/f_swclk_o
]
[
get_bd_ports f_swclk_o
]
connect_bd_net
[
get_bd_pins constants_and_slices/f_swdio_o
]
[
get_bd_ports f_swdio_o
]
connect_bd_net
[
get_bd_pins constants_and_slices/bckpl_servmod_i
]
[
get_bd_ports bckpl_servmod_i
]
connect_bd_net
[
get_bd_pins constants_and_slices/bckpl_servmod_o
]
[
get_bd_ports bckpl_servmod_o
]
connect_bd_net
[
get_bd_pins constants_and_slices/bckpl_servmod_t_o
]
[
get_bd_ports bckpl_servmod_t
]
...
...
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