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DIOT Igloo2-based radiation-tolerant System Board
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DIOT Igloo2-based radiation-tolerant System Board
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Change the capacitor tying GND to CHASSIS with one of a higher voltage rating
#34
· opened
Nov 03, 2020
by
Christos Gentsos
sch v1.0
minor
CLOSED
2
updated
Nov 06, 2020
I'd add I2C/SPI I/O expander to encode with resistor net version of the board and some unique ID chip.
#33
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
minor
CLOSED
0
updated
Nov 11, 2020
relicense to CERN-OHL-W v2
#32
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
cosmetics
CLOSED
0
updated
Oct 27, 2020
aligning net labels
#31
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
cosmetics
CLOSED
1
updated
Nov 11, 2020
FPGA_Banks_6_7: connecting FMC clocks
#30
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
question
CLOSED
1
updated
Nov 10, 2020
FPGA_Banks_6_7: I guess we don't need the filter circuit for SERDES_0_L23_*
#29
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
question
CLOSED
2
updated
Nov 04, 2020
FPGA_Banks_6_7: serdes Tx/Rx shall be AC-coupled
#28
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
1
updated
Nov 03, 2020
Translate_GPIO_to_2V5: more uniform translation circuits
#27
· opened
Oct 27, 2020
by
Grzegorz Daniluk
sch v1.0
minor
CLOSED
3
updated
Nov 11, 2020
Monitoring: ATSAMD21G18 is known to freeze in radiation, we should also have a power cycle/reset line from FPGA
#26
· opened
Oct 26, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
5
updated
Nov 12, 2020
Top_Misc: STRIP3 shall be also connected to the front panel i.e. CHASSIS net
#25
· opened
Oct 26, 2020
by
Grzegorz Daniluk
sch v1.0
minor
CLOSED
0
updated
Nov 05, 2020
Connect DEVRST_N to PGOOD.P1V2
#24
· opened
Oct 23, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
0
updated
Nov 05, 2020
Fix JTAG pull-down and DEVRST_N pull-up values
#23
· opened
Oct 23, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
1
updated
Nov 03, 2020
Go through the design checklist in AC393
#22
· opened
Oct 23, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
1
updated
Nov 13, 2020
Powering: Do we need 12V brownout detection circuit?
#21
· opened
Oct 23, 2020
by
Grzegorz Daniluk
sch v1.0
question
CLOSED
4
updated
Nov 04, 2020
FPGA_Bank1 cannot be used with LVDS signals, only single-ended or SSTL
#20
· opened
Oct 23, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
2
updated
Nov 09, 2020
CPCI-S_Backplane_P4-P6: add note that LVDS_17_P/N from all slots shall be length matched
#19
· opened
Oct 23, 2020
by
Grzegorz Daniluk
sch v1.0
minor
CLOSED
1
updated
Nov 04, 2020
CPCI-S_Backplane_P1-P3: some signals missing ESD protection
2 of 3 tasks completed
#18
· opened
Oct 23, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
2
updated
Oct 27, 2020
Fiducial targets
#17
· opened
Oct 23, 2020
by
Paul PERONNARD
sch v1.0
minor
CLOSED
0
updated
Nov 03, 2020
OPA192 power supply
#16
· opened
Oct 23, 2020
by
Paul PERONNARD
sch v1.0
minor
CLOSED
1
updated
Nov 03, 2020
12V input power connector
#15
· opened
Oct 23, 2020
by
Paul PERONNARD
sch v1.0
minor
CLOSED
3
updated
Nov 03, 2020
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