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DIOT Igloo2-based radiation-tolerant System Board
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DIOT Igloo2-based radiation-tolerant System Board
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Wrong pull ups at voltage translators (IC7)
#69
· opened
Dec 14, 2020
by
Volker Schramm
layout v1.0
Dec 18, 2020
critical
CLOSED
2
updated
Jan 28, 2021
Missing return vias (GND Vias) on serdes signals
#111
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 17, 2021
JTAG pull-ups and pull-downs
#71
· opened
Feb 04, 2021
by
Christos Gentsos
layout v1.0
critical
CLOSED
1
updated
Apr 01, 2021
Routing of VDDPLL and PLLVSSA should be done with Planes not traces
#106
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 21, 2021
C180 is placed Under FPGA and not IC32
#116
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 19, 2021
Stray line on SD_PLL_VSSA
#107
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 17, 2021
Different kind of Vias...
#120
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 19, 2021
Different packages used for IC4 and IC5 (both TPS7A4901)
#70
· opened
Jan 27, 2021
by
Christos Gentsos
layout v1.0
minor
CLOSED
1
updated
Jan 28, 2021
P2V5 supply not well connected
#96
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
1
updated
May 17, 2021
improve layout for some pairs
#81
· opened
May 04, 2021
by
Paul PERONNARD
layout v1.0
CLOSED
2
updated
May 18, 2021
Acid Traps
#103
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 19, 2021
P2V5_A rail is unused, it has to be removed
#122
· opened
May 20, 2021
by
Christos Gentsos
layout v1.0
minor
CLOSED
0
updated
May 21, 2021
IC6: missing input voltage
#72
· opened
Mar 16, 2021
by
Grzegorz Daniluk
layout v1.0
critical
CLOSED
1
updated
Apr 01, 2021
bottom ground plane
#83
· opened
May 04, 2021
by
Paul PERONNARD
layout v1.0
CLOSED
1
updated
May 18, 2021
L1 Common mode choke connection is not ok
#98
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 17, 2021
L4 (X:192mm Y:54mm) P3V3 plane unnecessairly cuts into PPERIPH plane and therefore cuts plane below L3 signals
#92
· opened
May 07, 2021
by
Grzegorz Daniluk
layout v1.0
critical
CLOSED
0
updated
May 18, 2021
Capacitor V-Ratings
#1
· opened
Oct 13, 2020
by
Volker Schramm
layout v1.0
critical
CLOSED
2
updated
Apr 01, 2021
Stack Up Layer Legend does not match the stack up
#119
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
CLOSED
0
updated
May 17, 2021
PWR_FAIL_N missing pull-up
#75
· opened
Apr 01, 2021
by
Christos Gentsos
layout v1.0
minor
CLOSED
1
updated
Apr 01, 2021
IC6: TPS7A4533 Does not have enough copper at Pad 6 for heat dissipation.
#100
· opened
May 17, 2021
by
Spyridon Georgakakis
layout v1.0
minor
CLOSED
1
updated
May 17, 2021
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