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DIOT Igloo2-based radiation-tolerant System Board
DIOT Igloo2-based radiation-tolerant System Board
Commit 8ee50fb0 authored by Tristan Gingold's avatar Tristan Gingold
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hdl: make var3_rdy sticky, add a bit to clear it

parent 94aaed92
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hdl/rtl/fip_urv_regs.cheby
View file @ 8ee50fb0
......@@ -32,7 +32,8 @@ memory-map:
name: var3_rdy
description: |-
Set by HW when var3 can be written.
Cleared when nanofip is transmitting it.
Cleared when nanofip is transmitting it or when fip_var3.clr is set.
The SW must wait for it before writting var3
range: 1
- reg:
name: fip_var1
......@@ -45,13 +46,22 @@ memory-map:
range: 0
- reg:
name: fip_var3
description: Set access to var 1
description: Set access to var 3
width: 32
access: rw
children:
- field:
name: acc
description: Tell nanofip var3 is being written
range: 0
- field:
name: clr
description: Clear the sticky var3_rdy
range: 1
x-hdl:
type: wire
x-hdl:
write-strobe: true
- reg:
name: fip_err
description: Number of worldfip errors; write to clear
......
hdl/rtl/fip_urv_regs.vhd
View file @ 8ee50fb0
-- Do not edit. Generated by cheby 1.6.dev0 using these options:
-- -i fip_urv_regs.cheby --gen-hdl fip_urv_regs.vhd
-- Generated on Wed Mar 01 17:05:32 2023 by tgingold
-- Generated on Tue Mar 14 14:33:15 2023 by tgingold
library ieee;
......@@ -71,14 +71,20 @@ entity fip_urv_regs is
-- Cleared when the software is reading it.
fip_status_var1_rdy_i : in std_logic;
-- Set by HW when var3 can be written.
-- Cleared when nanofip is transmitting it.
-- Cleared when nanofip is transmitting it or when fip_var3.clr is set.
-- The SW must wait for it before writting var3
fip_status_var3_rdy_i : in std_logic;
-- Set access to var 1
fip_var1_acc_o : out std_logic;
-- Set access to var 1
-- Set access to var 3
-- Tell nanofip var3 is being written
fip_var3_acc_o : out std_logic;
-- Clear the sticky var3_rdy
fip_var3_clr_i : in std_logic;
fip_var3_clr_o : out std_logic;
fip_var3_wr_o : out std_logic;
-- Number of worldfip errors; write to clear
fip_err_i : in std_logic_vector(31 downto 0);
......@@ -412,6 +418,7 @@ begin
-- Register fip_var3
fip_var3_acc_o <= fip_var3_acc_reg;
fip_var3_clr_o <= wr_dat_d0(1);
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
......@@ -425,6 +432,7 @@ begin
end if;
end if;
end process;
fip_var3_wr_o <= fip_var3_wack;
-- Register fip_err
fip_err_o <= wr_dat_d0;
......@@ -1197,40 +1205,40 @@ begin
-- Process for read requests.
process (adr_int, rd_req_int, fip_var_length_reg, fip_status_var1_rdy_i,
fip_status_var3_rdy_i, fip_var1_acc_reg, fip_var3_acc_reg, fip_err_i,
leds_val_reg, servmod_line_i, servmod_ctrl_dir_reg, psu_stat_pres_i,
psu_ctrl_pwr_cyc_req_reg, restart_cfg_iram_copy_reg,
restart_cfg_dram_clear_reg, restart_cfg_iram_err_reg,
restart_cfg_iram_src_reg, restart_cfg_iram_page_reg,
restart_cfg_src_page_reg, reset_count_i, monimod_shdn_val_reg,
fan_ctrl_io0_reg, fan_ctrl_io1_reg, fan_ctrl_rstn_reg,
i2c_off_monimod_reg, i2c_off_fantray_reg, app_0_cr_sys_rst_reg,
app_0_cr_cpu_rst_reg, app_i(0).sr_fault, app_i(0).reset_cause,
app_i(0).iram_ecc_se, app_i(0).iram_scrub_cycle,
app_i(0).iram_scrub_se, app_i(0).iram_scrub_de_last,
app_i(0).dram_ecc_se, app_i(0).dram_scrub_cycle,
app_i(0).dram_scrub_se, app_i(0).dram_scrub_de_last,
app_i(0).scrub_cfg_iram_en, app_i(0).scrub_cfg_dram_en,
app_i(0).nbr_cpu_fault, app_i(0).mailboxes_mboxout,
app_i(0).mailboxes_mboxin, app_i(0).mailboxes_status_mbin,
app_i(0).mailboxes_status_mbout, app_1_cr_sys_rst_reg,
app_1_cr_cpu_rst_reg, app_i(1).sr_fault, app_i(1).reset_cause,
app_i(1).iram_ecc_se, app_i(1).iram_scrub_cycle,
app_i(1).iram_scrub_se, app_i(1).iram_scrub_de_last,
app_i(1).dram_ecc_se, app_i(1).dram_scrub_cycle,
app_i(1).dram_scrub_se, app_i(1).dram_scrub_de_last,
app_i(1).scrub_cfg_iram_en, app_i(1).scrub_cfg_dram_en,
app_i(1).nbr_cpu_fault, app_i(1).mailboxes_mboxout,
app_i(1).mailboxes_mboxin, app_i(1).mailboxes_status_mbin,
app_i(1).mailboxes_status_mbout, boards_0_pins_i, boards_1_pins_i,
boards_2_pins_i, boards_3_pins_i, boards_4_pins_i, boards_5_pins_i,
boards_6_pins_i, boards_7_pins_i, shmem_regs_ram_ecc_se_i,
shmem_regs_ram_scrub_cycle_i, shmem_regs_ram_scrub_se_i,
shmem_regs_ram_scrub_de_last_i, shmem_regs_scrub_cfg_ram_en_i,
shmem_regs_ram_scrub_period_reg, shmem_regs_ecc_mask_reg, i2c_i.dat,
i2c_rack, spi_i.dat, spi_rack, fip_reg_i.dat, fip_reg_rack, sh_mem_i.dat,
sh_mem_rack, app0_mem_i.dat, app0_mem_rack, app1_mem_i.dat,
app1_mem_rack) begin
fip_status_var3_rdy_i, fip_var1_acc_reg, fip_var3_acc_reg,
fip_var3_clr_i, fip_err_i, leds_val_reg, servmod_line_i,
servmod_ctrl_dir_reg, psu_stat_pres_i, psu_ctrl_pwr_cyc_req_reg,
restart_cfg_iram_copy_reg, restart_cfg_dram_clear_reg,
restart_cfg_iram_err_reg, restart_cfg_iram_src_reg,
restart_cfg_iram_page_reg, restart_cfg_src_page_reg, reset_count_i,
monimod_shdn_val_reg, fan_ctrl_io0_reg, fan_ctrl_io1_reg,
fan_ctrl_rstn_reg, i2c_off_monimod_reg, i2c_off_fantray_reg,
app_0_cr_sys_rst_reg, app_0_cr_cpu_rst_reg, app_i(0).sr_fault,
app_i(0).reset_cause, app_i(0).iram_ecc_se,
app_i(0).iram_scrub_cycle, app_i(0).iram_scrub_se,
app_i(0).iram_scrub_de_last, app_i(0).dram_ecc_se,
app_i(0).dram_scrub_cycle, app_i(0).dram_scrub_se,
app_i(0).dram_scrub_de_last, app_i(0).scrub_cfg_iram_en,
app_i(0).scrub_cfg_dram_en, app_i(0).nbr_cpu_fault,
app_i(0).mailboxes_mboxout, app_i(0).mailboxes_mboxin,
app_i(0).mailboxes_status_mbin, app_i(0).mailboxes_status_mbout,
app_1_cr_sys_rst_reg, app_1_cr_cpu_rst_reg, app_i(1).sr_fault,
app_i(1).reset_cause, app_i(1).iram_ecc_se,
app_i(1).iram_scrub_cycle, app_i(1).iram_scrub_se,
app_i(1).iram_scrub_de_last, app_i(1).dram_ecc_se,
app_i(1).dram_scrub_cycle, app_i(1).dram_scrub_se,
app_i(1).dram_scrub_de_last, app_i(1).scrub_cfg_iram_en,
app_i(1).scrub_cfg_dram_en, app_i(1).nbr_cpu_fault,
app_i(1).mailboxes_mboxout, app_i(1).mailboxes_mboxin,
app_i(1).mailboxes_status_mbin, app_i(1).mailboxes_status_mbout,
boards_0_pins_i, boards_1_pins_i, boards_2_pins_i, boards_3_pins_i,
boards_4_pins_i, boards_5_pins_i, boards_6_pins_i, boards_7_pins_i,
shmem_regs_ram_ecc_se_i, shmem_regs_ram_scrub_cycle_i,
shmem_regs_ram_scrub_se_i, shmem_regs_ram_scrub_de_last_i,
shmem_regs_scrub_cfg_ram_en_i, shmem_regs_ram_scrub_period_reg,
shmem_regs_ecc_mask_reg, i2c_i.dat, i2c_rack, spi_i.dat, spi_rack,
fip_reg_i.dat, fip_reg_rack, sh_mem_i.dat, sh_mem_rack, app0_mem_i.dat,
app0_mem_rack, app1_mem_i.dat, app1_mem_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
app_o(0).mailboxes_mboxin_rd <= '0';
......@@ -1268,7 +1276,8 @@ begin
-- Reg fip_var3
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= fip_var3_acc_reg;
rd_dat_d0(31 downto 1) <= (others => '0');
rd_dat_d0(1) <= fip_var3_clr_i;
rd_dat_d0(31 downto 2) <= (others => '0');
when "100" =>
-- Reg fip_err
rd_ack_d0 <= rd_req_int;
......
hdl/top/diot_hydra2/diot_hydra2_top.vhd
View file @ 8ee50fb0
......@@ -155,7 +155,7 @@ architecture rtl of diot_hydra2_top is
signal slots_loops : t_slot_vec;
signal slots_relays : t_slot_vec;
signal var1_rdy2 : std_logic;
signal var1_rdy2, var3_rdy2, var3_clr_out, var3_clr_wr : std_logic;
signal wb_fip_in : t_wishbone_slave_in;
signal wb_fip_out : t_wishbone_slave_out;
......@@ -165,7 +165,7 @@ architecture rtl of diot_hydra2_top is
signal u_errflag, u_errflag_d : std_logic;
signal var1_acc, var1_rdy, var1_read : std_logic;
signal var3_acc, var3_rdy : std_logic;
signal var3_acc, var3_rdy, var3_written : std_logic;
-- shmem
signal sh_mem_mgmt_in : t_wishbone_slave_in;
......@@ -256,6 +256,7 @@ begin
if gbl_rst_n = '0' then
-- Variable was not read.
var1_read <= '0';
var3_written <= '0';
else
if var1_rdy = '0' then
-- A new value will be written.
......@@ -264,12 +265,19 @@ begin
-- Variable is (being) read.
var1_read <= '1';
end if;
if var3_acc = '1' or (var3_clr_out = '1' and var3_clr_wr = '1') then
var3_written <= '1';
elsif var3_rdy = '0' then
var3_written <= '0';
end if;
end if;
end if;
end process;
-- A variable is ready if it the data are ready from nanofip and not yet read.
var1_rdy2 <= var1_rdy and not var1_read;
var3_rdy2 <= var3_rdy and not var3_written;
-------------------------------------------------------------------------------
......@@ -362,9 +370,12 @@ begin
wb_o => wb_fip_out,
fip_var_length_o => p3_lgth_o,
fip_status_var1_rdy_i => var1_rdy2,
fip_status_var3_rdy_i => var3_rdy,
fip_status_var3_rdy_i => var3_rdy2,
fip_var1_acc_o => var1_acc,
fip_var3_acc_o => var3_acc,
fip_var3_clr_i => '0',
fip_var3_clr_o => var3_clr_out,
fip_var3_wr_o => var3_clr_wr,
app_i => app_regs_in,
app_o => app_regs_out,
......
sw/fip_urv/fip_urv_regs.h
View file @ 8ee50fb0
......@@ -18,9 +18,10 @@
#define FIP_URV_REGS_FIP_VAR1 0x8UL
#define FIP_URV_REGS_FIP_VAR1_ACC 0x1UL
/* Set access to var 1 */
/* Set access to var 3 */
#define FIP_URV_REGS_FIP_VAR3 0xcUL
#define FIP_URV_REGS_FIP_VAR3_ACC 0x1UL
#define FIP_URV_REGS_FIP_VAR3_CLR 0x2UL
/* Number of worldfip errors; write to clear */
#define FIP_URV_REGS_FIP_ERR 0x10UL
......@@ -212,7 +213,7 @@ struct fip_urv_regs {
/* [0x8]: REG (rw) Set access to var 1 */
uint32_t fip_var1;
/* [0xc]: REG (rw) Set access to var 1 */
/* [0xc]: REG (rw) Set access to var 3 */
uint32_t fip_var3;
/* [0x10]: REG (rw) Number of worldfip errors; write to clear */
......
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