Add layout work

645e20a4 · brecordo · Christos Gentsos · 11c8b3c1 · 645e20a4 · 645e20a4
Commit 645e20a4 authored Dec 07, 2020 by brecordo Committed by Christos Gentsos May 06, 2021
20 changed files
--- a/hw/EDA-04326-V1-0_project.PrjPcb
+++ b/hw/EDA-04326-V1-0_project.PrjPcb
--- a/hw/EDA-04326-V1-0_project.PrjPcbStructure
+++ b/hw/EDA-04326-V1-0_project.PrjPcbStructure
--- a/hw/PCB-Layout/EDA-04326-V1-0_pcb.PcbDoc
+++ b/hw/PCB-Layout/EDA-04326-V1-0_pcb.PcbDoc
--- a/hw/Schematics/CPCI-S_Backplane_P1-P3.SchDoc
+++ b/hw/Schematics/CPCI-S_Backplane_P1-P3.SchDoc
--- a/hw/Schematics/CPCI-S_Backplane_P4-P6.SchDoc
+++ b/hw/Schematics/CPCI-S_Backplane_P4-P6.SchDoc
--- a/hw/Schematics/Constrain_Periph_Nets.SchDoc
+++ b/hw/Schematics/Constrain_Periph_Nets.SchDoc
--- a/hw/Schematics/DIOT-sb-igl_top.SchDoc
+++ b/hw/Schematics/DIOT-sb-igl_top.SchDoc
--- a/hw/Schematics/FMC.SchDoc
+++ b/hw/Schematics/FMC.SchDoc
--- a/hw/Schematics/FPGA.SchDoc
+++ b/hw/Schematics/FPGA.SchDoc
--- a/hw/Schematics/FPGA_Banks_0_3_5_8.SchDoc
+++ b/hw/Schematics/FPGA_Banks_0_3_5_8.SchDoc
--- a/hw/Schematics/FPGA_Banks_1_2.SchDoc
+++ b/hw/Schematics/FPGA_Banks_1_2.SchDoc
--- a/hw/Schematics/FPGA_Banks_6_7.SchDoc
+++ b/hw/Schematics/FPGA_Banks_6_7.SchDoc
--- a/hw/Schematics/FPGA_Config.SchDoc
+++ b/hw/Schematics/FPGA_Config.SchDoc
--- a/hw/Schematics/FPGA_Power.SchDoc
+++ b/hw/Schematics/FPGA_Power.SchDoc
--- a/hw/Schematics/JTAG.SchDoc
+++ b/hw/Schematics/JTAG.SchDoc
--- a/hw/Schematics/Monitoring.SchDoc
+++ b/hw/Schematics/Monitoring.SchDoc
--- a/hw/Schematics/Powering.SchDoc
+++ b/hw/Schematics/Powering.SchDoc
--- a/hw/Schematics/Top_Misc.SchDoc
+++ b/hw/Schematics/Top_Misc.SchDoc
--- a/hw/Schematics/Translate_2V5_to_PPERIPH.SchDoc
+++ b/hw/Schematics/Translate_2V5_to_PPERIPH.SchDoc
--- a/hw/Schematics/Translate_OD_3V3_to_2V5.SchDoc
+++ b/hw/Schematics/Translate_OD_3V3_to_2V5.SchDoc