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DIOT Igloo2-based radiation-tolerant System Board
DIOT Igloo2-based radiation-tolerant System Board
Commit 5ad5ecd6 authored by Christos Gentsos's avatar Christos Gentsos
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Initial commit, lots of things still missing

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.gitignore 0 → 100644
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DIOT-sb-igl.PrjPcb 0 → 100644
View file @ 5ad5ecd6
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DIOT-sb-igl.PrjPcbStructure 0 → 100644
View file @ 5ad5ecd6
Record=TopLevelDocument|FileName=DIOT-sb-igl_top.SchDoc
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=JTAG.SchDoc|SymbolType=Normal|RawFileName=JTAG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=Powering_2.SchDoc|SymbolType=Normal|RawFileName=Powering_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=CPCI-S_Backplane_P4-P6.SchDoc|SymbolType=Normal|RawFileName=CPCI-S_Backplane_P4-P6.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=Top_Misc.SchDoc|SymbolType=Normal|RawFileName=Top_Misc.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FMC.SchDoc|SymbolType=Normal|RawFileName=FMC.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=CPCI-S_Backplane_P1-P3.SchDoc|SymbolType=Normal|RawFileName=CPCI-S_Backplane_P1-P3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=Monitoring.SchDoc|SymbolType=Normal|RawFileName=Monitoring.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA.SchDoc|SymbolType=Normal|RawFileName=FPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=Powering.SchDoc|SymbolType=Normal|RawFileName=Powering.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_5_8.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_5_8.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Config.SchDoc|SymbolType=Normal|RawFileName=FPGA_Config.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_6_7.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_6_7.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_1_2.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_1_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_0_3.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_0_3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Power.SchDoc|SymbolType=Normal|RawFileName=FPGA_Power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Schematics/CPCI-S_Backplane_P1-P3.Harness 0 → 100644
View file @ 5ad5ecd6
SB-GPIO=M_SCL,M_SDA,P_RST,P_IO0,P_IO1,P_IO2,P_PRES0,P_PRES1,F_RST,F_IO0,F_IO1
Schematics/FPGA_Banks_0_3.Harness 0 → 100644
View file @ 5ad5ecd6
PERIPH_CONN=S0_P,S0_N,S1_P,S1_N,S2_P,S2_N,S3_P,S3_N,S4_P,S4_N,S5_P,S5_N,S6_P,S6_N,S7_P,S7_N,S8_P,S8_N,S9_P,S9_N,S10_P,S10_N,S11_P,S11_N,S12_P,S12_N,S13_P,S13_N,S14_P,S14_N,S15_P,S15_N,S16_P,S16_N,S17_P,S17_N,SERVMOD_N
Schematics/FPGA_Banks_1_2.Harness 0 → 100644
View file @ 5ad5ecd6
FMC-LA=P[33..0],N[33..0]
I2C=SCL,SDA
Schematics/JTAG.Harness 0 → 100644
View file @ 5ad5ecd6
JTAG=TCK,TDI,TDO,TMS,TRST_N
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