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DIOT Igloo2-based radiation-tolerant System Board
DIOT Igloo2-based radiation-tolerant System Board
Commit 3dbf0a26 authored by Christos Gentsos's avatar Christos Gentsos
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Add voltage translators for SERVMOD_N, rules for FMC diff pairs

parent f719436e
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Showing with 511 additions and 143 deletions
DIOT-sb-igl.PrjPcb
View file @ 3dbf0a26
......@@ -12,8 +12,8 @@ SeparateFolders=1
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......@@ -106,7 +106,7 @@ GenerateClassCluster=0
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......@@ -123,23 +123,6 @@ GenerateClassCluster=0
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......@@ -156,7 +139,7 @@ DItemRevisionGUID=
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......@@ -190,7 +173,7 @@ DItemRevisionGUID=
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......@@ -1231,7 +1366,7 @@ Type6=2
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ParameterName4=Color
ParameterName4=ClassName
ParameterUpdate4=1
ParameterName5=Comment
ParameterName5=Color
ParameterUpdate5=1
ParameterName6=Component Kind
ParameterName6=Comment
ParameterUpdate6=1
ParameterName7=Component Type
ParameterName7=Component Kind
ParameterUpdate7=1
ParameterName8=ComponentHeight
ParameterName8=Component Type
ParameterUpdate8=1
ParameterName9=ComponentLink1Description
ParameterName9=ComponentHeight
ParameterUpdate9=1
ParameterName10=ComponentLink1URL
ParameterName10=ComponentLink1Description
ParameterUpdate10=1
ParameterName11=ComponentLink2Description
ParameterName11=ComponentLink1URL
ParameterUpdate11=1
ParameterName12=ComponentLink2URL
ParameterName12=ComponentLink2Description
ParameterUpdate12=1
ParameterName13=CreateDate
ParameterName13=ComponentLink2URL
ParameterUpdate13=1
ParameterName14=Description
ParameterName14=CreateDate
ParameterUpdate14=1
ParameterName15=Device
ParameterName15=Description
ParameterUpdate15=1
ParameterName16=Family
ParameterName16=Designator
ParameterUpdate16=1
ParameterName17=HelpURL
ParameterName17=Device
ParameterUpdate17=1
ParameterName18=LatestRevisionDate
ParameterName18=Family
ParameterUpdate18=1
ParameterName19=Library Reference
ParameterName19=HelpURL
ParameterUpdate19=1
ParameterName20=Manufacturer
ParameterName20=LatestRevisionDate
ParameterUpdate20=1
ParameterName21=Manufacturer Part Number
ParameterName21=Library Reference
ParameterUpdate21=1
ParameterName22=Manufacturer1 ComponentHeight
ParameterName22=Manufacturer
ParameterUpdate22=1
ParameterName23=Manufacturer1 Example
ParameterName23=Manufacturer Part Number
ParameterUpdate23=1
ParameterName24=Manufacturer1 Part Number
ParameterName24=Manufacturer1 ComponentHeight
ParameterUpdate24=1
ParameterName25=Mounted
ParameterName25=Manufacturer1 Example
ParameterUpdate25=1
ParameterName26=PackageDescription
ParameterName26=Manufacturer1 Part Number
ParameterUpdate26=1
ParameterName27=Part Description
ParameterName27=Mounted
ParameterUpdate27=1
ParameterName28=Part Number
ParameterName28=PackageDescription
ParameterUpdate28=1
ParameterName29=Pin Count
ParameterName29=Part Description
ParameterUpdate29=1
ParameterName30=Power
ParameterName30=Part Number
ParameterUpdate30=1
ParameterName31=PressFit
ParameterName31=Pin Count
ParameterUpdate31=1
ParameterName32=Resistance
ParameterName32=Placement Comment
ParameterUpdate32=1
ParameterName33=SCEM
ParameterName33=Placement Order ID
ParameterUpdate33=1
ParameterName34=Sense
ParameterName34=Placement Order Modifier
ParameterUpdate34=1
ParameterName35=SMD
ParameterName35=Power
ParameterUpdate35=1
ParameterName36=Socket
ParameterName36=PressFit
ParameterUpdate36=1
ParameterName37=Status
ParameterName37=Resistance
ParameterUpdate37=1
ParameterName38=Table
ParameterName38=SCEM
ParameterUpdate38=1
ParameterName39=TC
ParameterName39=Sense
ParameterUpdate39=1
ParameterName40=Tolerance
ParameterName40=SMD
ParameterUpdate40=1
ParameterName41=Value
ParameterName41=Socket
ParameterUpdate41=1
ParameterName42=Voltage
ParameterName42=Status
ParameterUpdate42=1
ParameterName43=Status Comment
ParameterUpdate43=1
ParameterName44=Table
ParameterUpdate44=1
ParameterName45=TC
ParameterUpdate45=1
ParameterName46=Tolerance
ParameterUpdate46=1
ParameterName47=Value
ParameterUpdate47=1
ParameterName48=Voltage
ParameterUpdate48=1
ModelTypeGroup0=PCBLIB
ModelTypeUpdate0=1
ModelType0=PCBLIB
......@@ -1622,29 +1931,80 @@ ModelType7=PCBLIB
ModelName7=CAPC1005X55N
ModelUpdate7=1
ModelType8=PCBLIB
ModelName8=CAPC3225X280N
ModelName8=CAPC1608X87N
ModelUpdate8=1
ModelType9=PCBLIB
ModelName9=FUSE_LITTELFUSE_0154
ModelName9=CAPC1709X100N
ModelUpdate9=1
ModelType10=PCBLIB
ModelName10=IND_MURATA_DLW5BS
ModelName10=CAPC3225X280N
ModelUpdate10=1
ModelType11=PCBLIB
ModelName11=LEDC1608X80N_RED
ModelName11=CAPMP6032X280N
ModelUpdate11=1
ModelType12=PCBLIB
ModelName12=PCBM_CERN_FEASTMP_V3_KIT
ModelName12=CAPMP7343X310N
ModelUpdate12=1
ModelType13=PCBLIB
ModelName13=RESC_VISHAY_WSL2512_0R007-0R5
ModelName13=FUSE_LITTELFUSE_0154
ModelUpdate13=1
ModelType14=PCBLIB
ModelName14=RESC1005X40N
ModelName14=IND_MURATA_DLW5BS
ModelUpdate14=1
ModelType15=PCBLIB
ModelName15=RESC3216X65N
ModelName15=INDC2012X105N
ModelUpdate15=1
ModelType16=PCBLIB
ModelName16=LEDC1608X80N_RED
ModelUpdate16=1
ModelType17=PCBLIB
ModelName17=MTG270_500
ModelUpdate17=1
ModelType18=PCBLIB
ModelName18=MTG300_600
ModelUpdate18=1
ModelType19=PCBLIB
ModelName19=PCBM_CERN_FEASTMP_V3_KIT
ModelUpdate19=1
ModelType20=PCBLIB
ModelName20=RESC_VISHAY_WSL2512_0R007-0R5
ModelUpdate20=1
ModelType21=PCBLIB
ModelName21=RESC1005X35N
ModelUpdate21=1
ModelType22=PCBLIB
ModelName22=RESC1005X40N
ModelUpdate22=1
ModelType23=PCBLIB
ModelName23=RESC2012X60N
ModelUpdate23=1
ModelType24=PCBLIB
ModelName24=RESC2113X55N
ModelUpdate24=1
ModelType25=PCBLIB
ModelName25=RESC3216X65N
ModelUpdate25=1
ModelType26=PCBLIB
ModelName26=SAMTEC_ASP-134603-01
ModelUpdate26=1
ModelType27=PCBLIB
ModelName27=SAMTEC_HTSW-101-23-L-S
ModelUpdate27=1
ModelType28=PCBLIB
ModelName28=SAMTEC_HTSW-103-23-L-S
ModelUpdate28=1
ModelType29=PCBLIB
ModelName29=SOP65P400X130-8N
ModelUpdate29=1
ModelType30=PCBLIB
ModelName30=STELVIO-KONTEK_3131730000400
ModelUpdate30=1
ModelType31=PCBLIB
ModelName31=TO170P1394X457-6N-R900X1060
ModelUpdate31=1
ModelType32=PCBLIB
ModelName32=XTAL_ABRACON_ABS09
ModelUpdate32=1
[DatabaseUpdateOptions]
SelectedOnly=0
......
DIOT-sb-igl.PrjPcbStructure
View file @ 3dbf0a26
......@@ -8,9 +8,16 @@ Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|S
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=Monitoring.SchDoc|SymbolType=Normal|RawFileName=Monitoring.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA.SchDoc|SymbolType=Normal|RawFileName=FPGA.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=DIOT-sb-igl_top.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=Powering.SchDoc|SymbolType=Normal|RawFileName=Powering.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_5_8.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_5_8.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Config.SchDoc|SymbolType=Normal|RawFileName=FPGA_Config.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_6_7.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_6_7.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_1_2.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_1_2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_0_3.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_0_3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Banks_0_3_5_8.SchDoc|SymbolType=Normal|RawFileName=FPGA_Banks_0_3_5_8.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA.SchDoc|Designator=Designator|SchDesignator=Designator|FileName=FPGA_Power.SchDoc|SymbolType=Normal|RawFileName=FPGA_Power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans1|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans2|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans3|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans4|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans5|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans6|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans7|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=FPGA_Banks_1_2.SchDoc|Designator=Trans8|SchDesignator=REPEAT(Trans,1,8)|FileName=Translate_2V5_to_PPERIPH_1b.SchDoc|SymbolType=Normal|RawFileName=Translate_2V5_to_PPERIPH_1b.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Schematics/FMC.SchDoc
View file @ 3dbf0a26
No preview for this file type
Schematics/FPGA.SchDoc
View file @ 3dbf0a26
No preview for this file type
Schematics/FPGA_Banks_1_2.Harness
View file @ 3dbf0a26
FMC-LA=P[33..0],N[33..0]
FMC-LA=D_N[33..0],D_P[33..0]
FMC-SIGS=PRSNT,{I2C:I2C},{LA:FMC-LA}
I2C=SCL,SDA
Schematics/JTAG.SchDoc
View file @ 3dbf0a26
No preview for this file type
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