Grzegorz DanilukDIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
The DI/OT FMC Carrier Peripheral Board is one of the main components of the Distributed I/O Tier project ecosystem. The board allows hosting HPC and LPC FMC mezzanines in peripheral slots of a DI/OT, provides a DDR4 SODIMM slot and FPGA (Kintex Ultrascale) for early data storage, processing and communication over the backplane with the DI/OT System Board. This board is mechanically and electrically compliant with the Compact PCI Serial standard (CPCI-S.0).
Main Features
- Xilinx Kintex UltraScale FPGA (XCKU035-1FFVA1156C)
- SODIMM DDR4 slot
- NOR Flash for storing FPGA bitstream
- On-board temperature sensors
- Programmable SI5341 clock generator
- 2 multi purpose LEMO I/Os
- FMC slot with high pin count (HPC) connector
- Vadj 1.8V
- LA, HA, HB banks connected to FPGA I/Os
- 10 MGT Tx/Rx lanes connected to FPGA GTH
- DI/OT backplane connectors including
- 16 LVDS lanes
- 1 MGT lane
- Low skew clock distribution from the System Board
- Identification I2C bus
- P4 RTM connector
Related links and documents
Contacts
- Greg Daniluk - CERN
Status
| Date | Event |
|---|---|
| May-2020 | Project starts, gathering specification |
| Aug-2020 | Schematics design started |
| Nov-2020 | Review of schematics v1.0 |
| Feb-2021 | Approved schematics v1.0, layout starts |
| Jul-2021 | Review of layout v1.0 |
| Sep-2021 | Fixes to layout finalized, production of prototypes starts |
| 21-02-2022 | 14 v1.0 prototypes built. 10 will be shipped to CERN |
| 14-03-2022 | 7 v1.0 prototypes arrived at CERN |
| Apr-2024 | Launching v2.0 design |
| Jun-2024 | Finished design of FMC Carrier v2 |
| Nov-2024 | FMC Carrier v2 design published in CERN EDMS |