Specification
Wherever possible, the same components shall be used as in the DI/OT ZU7 System Board
Components
FPGA
-
Kintex Ultrascale - XCKU035-1FFVA1156C
- Example I/O assignment to various HP/HR I/O banks
Bank | Voltage | Assignment |
---|---|---|
64 (HR) | * | P4 signals, peripherals |
65 (HR) | * | DI/OT backplane P1 slow I/Os, peripherals, thermometers, LEDs |
66 (HP) | 1.2V | DDR4 |
67 (HP) | 1.2V | DDR4 |
68 (HP) | 1.2V | DDR4 |
44 (HP) | 1.8V | DI/OT backplane P1/P6 LVDS lanes, CLK |
45 (HP) | Vadj | FMC HPC LA/HA/HB/CLK |
46 (HP) | Vadj | FMC HPC LA/HA/HB/CLK |
47 (HP) | Vadj | FMC HPC LA/HA/HB/CLK |
48 (HP) | Vadj | FMC HPC LA/HA/HB/CLK |
FMC
- HPC with 8 MGTs - to e.g. host COTS ADC FMCs, DACs with JESD204B
- Vadj 1.8V enabled/disabled by FPGA pin
DI/OT backplane connectors
-
P1 fully populated:
- MGT_Tx/MGT_Rx lanes connected to FPGA transceiver
- LVDS lanes (DIFF0..10) connected to FPGA I/Os, from those DIFF0 and DIFF8 connected to clock-capable FPGA I/Os
- Geographical addressing pins (GA0..3) connected to FPGA I/Os
- SHARED_BUS0..4 connected to FPGA I/Os
- RST_N connected to FPGA I/O
- SYSEN_N connected to FPGA I/O
- CLK_P/CLK_N connected to Si5341
-
P6:
- LVDS lanes (DIFF11..14) connected to FPGA I/Os
-
P4 populated depending on FPGA I/Os availability:
- RTM_SHARED_BUS0..7 connected to FPGA I/Os through switches (e.g. 74HC4066PW) all enabled from 1 FPGA pin - to allow peripheral board to be dynamically attached to the P4 shared bus.
- RTM I/Os connected to FPGA I/Os depending on available I/Os
Connectivity
- front-panel, ideally includes
- LEDs connected to FPGA I/Os (4-6? depending how many can be fit in the front panel)
- a DIO with lemo-00
Memories
- DDR4 SO-DIMM slot - not all applications will need external memory + it will make memory obsolescence handling easier
- QSPI Flash - for FPGA bitstream
- 24AA025E48-I/SN EEPROM with unique ID attached to backplane I2C and GA0..2, used also to store FRU information (like in FMC mezzanines) containing version of the board (see details on Peripheral Boards identification )
- [optional] eMMC / microSD card slot - if spare FPGA pins are available
Clock generation
- Si5341 for main FPGA clock, DDR clock, MGT clocks
- operating in zero delay mode (external feedback loop from out9 to fb_in)
- local oscillator or CLK_P/N from DI/OT backplane as possible clock inputs
- optional DRTIO oscillators
Power
- IRPS5401 PMIC
- separate DC/DC for Vadj generation; its enable input shall be controlled by FPGA. The same Vadj shall power FPGA I/O banks that are connected to FMC I/Os so that Vadj can be turned on ONLY when FMC mezzanine supported voltages match carrier supported voltage (1.8V).
Miscellaneous
- Xilinx JTAG connector: MOLEX 87832-1420
- Thermometers
- LEDs in the front panel
- FPGA heatsink (same as on DI/OT ZU7 System Board)
- External power connector to run the board without DI/OT crate (4-pin Molex same as on DI/OT ZU7 System Board)
Mechanical
- 100mm x 220mm
- P1, P4 and P6 backplane connectors
- cut-out in PCB under the FMC slot (like in SPEC board, for better cooling).
- DIO 16ch opt 24V as mechanical reference
Requirements
- The board shall have EEPROM-based identification mechanism implemented according to Peripheral Boards identification procedure
- the same SERVMOD_N signal shall drive:
- analog switches to dynamically attach identification EEPROM to the backplane I2C bus
- multiplexers selecting P1 I/Os assigment between FPGA JTAG TAP and regular I/Os
- Backplane P1 connector pins shall have dual IO/JTAG function (selectable with SERVMOD_N):
- A3 - TDI
- D3 - TDO
- B4 - TMS
- H4 - TCK
- K4 - nTRST
- MGT backplane lanes (P1.A5,A6,D5,E5) shall be connected to FPGA MGT
To be defined:
- Q: remote FPGA programming, only remote update by writing to flash, or also connect JTAG to backplane lines?
- A TE/ABT: JTAG to backplane please