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DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
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DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
Issues
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19
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100
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119
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TDA21240 is obsolete
#119
· opened
Apr 29, 2024
by
Grzegorz Daniluk
v2.0
CLOSED
2
updated
Apr 29, 2024
LVDS pins clock capable not routed or connected to non clock capable pins
#107
· opened
Nov 13, 2023
by
Alén Arias Vázquez
CLOSED
3
updated
Apr 08, 2024
236 DRC errors, mostly on length matching but also on front panel LEMO collision
#78
· opened
Jul 14, 2021
by
Grzegorz Daniluk
layout-v1.0
major
CLOSED
8
updated
Sep 24, 2021
Add copper balancing pattern on L1 and L12
#94
· opened
Jul 21, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
CLOSED
5
updated
Sep 16, 2021
FPGA_Bank_44-46_48_FMC: Verify schematics note
#99
· opened
Sep 08, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
1
updated
Sep 16, 2021
Remove 2 unnecessary mounting holes
#97
· opened
Sep 08, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
0
updated
Sep 16, 2021
Power_Supply_2: can we add an optional pull-up on EN_P1V8_FMC?
#100
· opened
Sep 08, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
CLOSED
0
updated
Sep 16, 2021
Silkscreen: add hyperlinks
#98
· opened
Sep 08, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
0
updated
Sep 16, 2021
Restore components designators
#80
· opened
Jul 20, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
CLOSED
3
updated
Sep 07, 2021
connect style for power SMDs
#86
· opened
Jul 21, 2021
by
Paul PERONNARD
CLOSED
1
updated
Sep 07, 2021
Consider modifying the board stack-up
#85
· opened
Jul 20, 2021
by
Christos Gentsos
layout-v1.0
CLOSED
2
updated
Sep 07, 2021
DDR4 routing
#87
· opened
Jul 21, 2021
by
Paul PERONNARD
major
CLOSED
1
updated
Sep 07, 2021
Backplane MGT vs LVDS lanes routing
#77
· opened
Jul 07, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
major
CLOSED
6
updated
Sep 07, 2021
Some return vias are missing
#93
· opened
Jul 21, 2021
by
Christos Gentsos
layout-v1.0
Done
CLOSED
3
updated
Sep 07, 2021
Increase clearance between traces and FMC mounting holes
#92
· opened
Jul 21, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
major
CLOSED
1
updated
Sep 07, 2021
track width power SMDs
#89
· opened
Jul 21, 2021
by
Paul PERONNARD
Done
CLOSED
0
updated
Sep 07, 2021
L3: effective width of FMC_VREFA_M2C and FMC_VREFB_M2C polygons
#83
· opened
Jul 20, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
2
updated
Sep 07, 2021
Some traces are very close to FPGA heatsink mounting holes
#91
· opened
Jul 21, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
major
CLOSED
1
updated
Sep 07, 2021
Acid traps
3 of 3 tasks completed
#79
· opened
Jul 19, 2021
by
Grzegorz Daniluk
layout-v1.0
Done
minor
CLOSED
0
updated
Sep 06, 2021
Change J9 to 2.54 mm pitch
#95
· opened
Aug 13, 2021
by
Paweł Kulik
layout-v1.0
Done
CLOSED
2
updated
Sep 06, 2021
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