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DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
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DIOT Kintex Ultrascale-based Peripheral Board FMC Carrier
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CPCIS_Connectors_P1_P4_P6: Fix JTAG lines assignment to BP_DUAL diff pairs
3 of 5 tasks completed
#74
· opened
Jan 28, 2021
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
0
updated
Feb 04, 2021
FPGA_Bank_44_64_65: LED_USER0 could be moved to Bank44
#73
· opened
Jan 28, 2021
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Feb 04, 2021
RTM connector pinout proposal
#72
· opened
Dec 15, 2020
by
Grzegorz Daniluk
sch v1.0
Done
question
13
updated
Apr 18, 2024
Optimise bill-of-materials
10 of 10 tasks completed
#71
· opened
Dec 03, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
1
updated
Jan 28, 2021
Connect SERVMOD also to FPGA pin
#70
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
1
updated
Jan 28, 2021
FPGA_Bank_44_64_65: BP_IO.LVDS_P/N_12 isn't connected to FPGA diff pair
#69
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
0
updated
Jan 28, 2021
USB_Quad and Power_Supply_3 could use the same LDO to produce 3V3 from 5V
#68
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
1
updated
Jan 28, 2021
Re-annotate the whole schematics
#67
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
4
updated
Jan 27, 2021
Add a startup oscillator that could be easily used before/instead programming Si5341
#66
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
4
updated
Jan 27, 2021
Sensors: why they are powered from P3V3_reg and not from P3V3?
#65
· opened
Dec 02, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
3
updated
Jan 27, 2021
FPGA_BANK_66_67_68_DDR: random indentation of net labels?
#63
· opened
Nov 23, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Jan 27, 2021
FPGA_Bank_44_64_65: rename UART signals
2 of 2 tasks completed
#61
· opened
Nov 23, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Jan 27, 2021
FPGA_Bank_44_64_65: SD_DETECT missing pull-up
#60
· opened
Nov 23, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
1
updated
Jan 27, 2021
FPGA_Bank_0_CFG: "Connect RST_N to PROGRAM_B?" note
#59
· opened
Nov 23, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Jan 27, 2021
DDR_SODIMM: orientation of pull-up and pull-down banks
#58
· opened
Nov 23, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Jan 27, 2021
DDR4_SODIMM: VDDSPD should be P2V5
#57
· opened
Nov 23, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
0
updated
Jan 27, 2021
BP_IO.GA0..3 shall be pulled-up on this board
#56
· opened
Nov 20, 2020
by
Grzegorz Daniluk
sch v1.0
Done
major
CLOSED
2
updated
Jan 27, 2021
CPCIS_Connectors_P1_P4_P6: BP_DUAL and BP_IO LVDS diff pairs numbering shall reflect the cross-over in the backplane
#55
· opened
Nov 20, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
3
updated
Jan 28, 2021
CPCIS_Connectors_P1_P4_P6: remove no-ERC directives from P4 connector row 6
#54
· opened
Nov 20, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Jan 27, 2021
CPCIS_Connectors_P1_P4_P6: remove DECT_RIO and DECT_BPR as these signals are not used
#51
· opened
Nov 19, 2020
by
Grzegorz Daniluk
sch v1.0
Done
minor
CLOSED
0
updated
Jan 27, 2021
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