DDR4_SODIMM: VDDSPD should be P2V5
e.g. Micron SODIMMs expect VDDSPD to be P2V5. It looks that VDDSPD on Xilinx devkit is indeed at P3V3 because they use specific SODIMM that is compatible with higher voltage. See here: https://forums.xilinx.com/t5/Xilinx-Evaluation-Boards/Zynq-UltraScale-ZCU102-DDR4-VDDSPD-Voltage/td-p/814539