CPCIS_Connectors_P1_P4_P6: BP_DUAL and BP_IO LVDS diff pairs numbering shall reflect the cross-over in the backplane
e.g. BP_DUAL_1 should be connected to A3/B3 of P1 and BP_DUAL_0 to D3/E3 of P1
This way FPGA designer can assign I/Os to their design without tracing the connections from the System Board schematics, through Backplane schematics to Peripheral Board schematics.