Skip to content
Snippets Groups Projects
Commit 17d20ae6 authored by Christos Gentsos's avatar Christos Gentsos
Browse files

Btldr: make the bl use the 8MHz XTAL, present in all variations

parent 091cc5a2
Branches
No related merge requests found
Hide whitespace changes
Inline Side-by-side
bootloader/atmel_start_prj/config/hpl_gclk_config.h
+ 2
− 2
View file @ 17d20ae6
...@@ -142,7 +142,7 @@ ...@@ -142,7 +142,7 @@
// <i> This defines the clock source for generic clock generator 1 // <i> This defines the clock source for generic clock generator 1
// <id> gclk_gen_1_oscillator // <id> gclk_gen_1_oscillator
#ifndef CONF_GCLK_GEN_1_SRC #ifndef CONF_GCLK_GEN_1_SRC
#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC32K #define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC
#endif #endif
// </h> // </h>
...@@ -151,7 +151,7 @@ ...@@ -151,7 +151,7 @@
// <i> // <i>
// <id> gclk_gen_1_div // <id> gclk_gen_1_div
#ifndef CONF_GCLK_GEN_1_DIV #ifndef CONF_GCLK_GEN_1_DIV
#define CONF_GCLK_GEN_1_DIV 1 #define CONF_GCLK_GEN_1_DIV 256
#endif #endif
// </h> // </h>
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment