From 17d20ae6cb78468abefe54c8746c58b9b6dc9e38 Mon Sep 17 00:00:00 2001
From: Christos Gentsos <christos.gentsos@cern.ch>
Date: Wed, 11 Aug 2021 17:01:46 +0200
Subject: [PATCH] Btldr: make the bl use the 8MHz XTAL, present in all
 variations

---
 bootloader/atmel_start_prj/config/hpl_gclk_config.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/bootloader/atmel_start_prj/config/hpl_gclk_config.h b/bootloader/atmel_start_prj/config/hpl_gclk_config.h
index 6a6a5fe..a29dfd5 100644
--- a/bootloader/atmel_start_prj/config/hpl_gclk_config.h
+++ b/bootloader/atmel_start_prj/config/hpl_gclk_config.h
@@ -142,7 +142,7 @@
 // <i> This defines the clock source for generic clock generator 1
 // <id> gclk_gen_1_oscillator
 #ifndef CONF_GCLK_GEN_1_SRC
-#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC32K
+#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC
 #endif
 // </h>
 
@@ -151,7 +151,7 @@
 // <i>
 // <id> gclk_gen_1_div
 #ifndef CONF_GCLK_GEN_1_DIV
-#define CONF_GCLK_GEN_1_DIV 1
+#define CONF_GCLK_GEN_1_DIV 256
 #endif
 
 // </h>
-- 
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