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DIOT CompactPCI Serial crate hardware
DIOT CompactPCI Serial crate hardware
Commit 24ac5c0e authored by Michal Gaska's avatar Michal Gaska
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footprints issue solved

parent 19055978
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pcb/cpcis_backplane/CPCI Backplane-rescue.lib
View file @ 24ac5c0e
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# P12V-power2-CPCI-Backplane-rescue
#
DEF P12V-power2-CPCI-Backplane-rescue #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "P12V-power2-CPCI-Backplane-rescue" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X P12V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# P5V-power2-CPCI-Backplane-rescue
#
DEF P5V-power2-CPCI-Backplane-rescue #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "P5V-power2-CPCI-Backplane-rescue" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X P5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# Vext1-powerMG
#
DEF Vext1-powerMG #PWR 0 0 Y Y 1 F P
......@@ -31,4 +61,64 @@ X Vext2 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# WURTH_7461057-Fasteners_&_Fixings-CPCI-Backplane-rescue
#
DEF WURTH_7461057-Fasteners_&_Fixings-CPCI-Backplane-rescue BUSH 0 50 Y Y 1 L N
F0 "BUSH" 150 100 50 H V L CNN
F1 "WURTH_7461057-Fasteners_&_Fixings-CPCI-Backplane-rescue" 0 -145 50 H I L CNN
F2 "Fasteners & Fixings:WURTH_7461057" 0 -220 50 H I L CNN
F3 " " 0 -295 50 H I L CNN
F4 "M3" 600 100 50 H V L CNN "Val"
F5 "WURTH_7461057" 0 -370 50 H I L CNN "Part Number"
F6 "Bush" 0 -445 50 H I L CNN "Library Ref"
F7 "SchLib\\Fasteners & Fixings.SchLib" 0 -520 50 H I L CNN "Library Path"
F8 "M3" 0 -595 50 H I L CNN "Comment"
F9 "Standard" 0 -670 50 H I L CNN "Component Kind"
F10 "Standard" 0 -745 50 H I L CNN "Component Type"
F11 "6" 0 -820 50 H I L CNN "Pin Count"
F12 " " 0 -895 50 H I L CNN "Case"
F13 "PcbLib\\Fasteners & Fixings.PcbLib" 0 -970 50 H I L CNN "Footprint Path"
F14 "WURTH_7461057" 0 -1045 50 H I L CNN "Footprint Ref"
F15 "7x7x6mm REDCUBE Press-Fit with Internsl Threaded Hole M3,Two Rows Pin-Plate WP-BUTR" 0 -1120 50 H I L CNN "PackageDescription"
F16 " " 0 -1195 50 H I L CNN "Family"
F17 "Yes" 0 -1270 50 H I L CNN "Mounted"
F18 "No" 0 -1345 50 H I L CNN "Socket"
F19 "No" 0 -1420 50 H I L CNN "SMD"
F20 "Yes" 0 -1495 50 H I L CNN "PressFit"
F21 "No" 0 -1570 50 H I L CNN "Sense"
F22 " " 0 -1645 50 H I L CNN "Sense Comment"
F23 "None" 0 -1720 50 H I L CNN "Status"
F24 " " 0 -1795 50 H I L CNN "Status Comment"
F25 " " 0 -1870 50 H I L CNN "SCEM"
F26 "REDCUBE Press-Fit Bush With Threaded Hole M3 and Two Rows Pin-Plate WP-BUTR" 0 -1945 50 H I L CNN "Part Description"
F27 "WURTH" 0 -2020 50 H I L CNN "Manufacturer"
F28 "7461057" 0 -2095 50 H I L CNN "Manufacturer Part Number"
F29 "6mm" 0 -2170 50 H I L CNN "ComponentHeight"
F30 " " 0 -2245 50 H I L CNN "Manufacturer1 Example"
F31 " " 0 -2320 50 H I L CNN "Manufacturer1 Part Number"
F32 " " 0 -2395 50 H I L CNN "Manufacturer1 ComponentHeight"
F33 " " 0 -2470 50 H I L CNN "ComponentLink1Description"
F34 " " 0 -2545 50 H I L CNN "ComponentLink2Description"
F35 "CERN DEM JLC" 0 -2620 50 H I L CNN "Author"
F36 "08/13/18 00:00:00" 0 -2695 50 H I L CNN "CreateDate"
F37 "08/13/18 00:00:00" 0 -2770 50 H I L CNN "LatestRevisionDate"
F38 "Fasteners & Fixings" 0 -2845 50 H I L CNN "Database Table Name"
F39 "Eletro-mechanical.DbLib" 0 -2920 50 H I L CNN "Library Name"
F40 "Fasteners & Fixings" 0 -2995 50 H I L CNN "Footprint Library"
F41 "This work is licensed under the Creative Commons CC-BY-SA 4.0 License. To the extent that circuit schematics that use Licensed Material can be considered to be ‘Adapted Material’, then the copyright holder waives article 3.b of the license with respect to these schematics." 0 -3070 50 H I L CNN "License"
DRAW
P 2 0 1 10 0 50 100 50 N
P 2 0 1 0 20 100 20 150 N
P 2 0 1 0 25 80 25 150 N
P 2 0 1 0 25 80 50 70 N
P 2 0 1 0 75 80 25 80 N
P 2 0 1 0 75 80 50 70 N
P 2 0 1 0 75 80 75 150 N
P 2 0 1 0 80 100 20 100 N
P 2 0 1 0 80 100 80 150 N
P 6 0 1 10 0 50 0 140 10 150 90 150 100 140 100 50 N
X 1 1 0 0 50 U 0 0 0 1 B
ENDDRAW
ENDDEF
#
#End Library
pcb/cpcis_backplane/fp-info-cache
View file @ 24ac5c0e
149226210840645
MOLEX THD
MOLEX_22-04-1021
2.5mm (.100") Pitch KK® Header, Single Row, Vertical, 2 Circuits
18717252144585
NetTie
NetTie-2_SMD_Pad0.5mm
Net tie, 2 pin, 0.5mm square SMD pads
net tie
0
2
2
MOLEX THD
MOLEX_22-04-1031
2.5mm (.100") Pitch KK® Header, Single Row, Vertical, 3 Circuits
0
3
3
MOLEX THD
MOLEX_22-04-1041
2.5mm (.100") Pitch KK® Header, Single Row, Vertical, 4 Circuits
0
4
4
MOLEX THD
MOLEX_22-04-1071
2.5mm (.100") Pitch KK® Header, Single Row, Vertical, 7 Circuits
0
7
7
MOLEX THD
MOLEX_22-05-3151
2.54mm (.100") Pitch KK® Wire-To-Board Header, Right Angle, With Friction Lock, 15 Circuits
0
15
15
MOLEX THD
MOLEX_22-05-7028
2.54mm (.100") Pitch KK® Wire-To-Board Header, Right Angle, With Friction Lock, 2 Circuits
NetTie
NetTie-2_SMD_Pad2.0mm
Net tie, 2 pin, 2.0mm square SMD pads
net tie
0
2
2
MOLEX THD
MOLEX_22-05-7038
2.54mm (.100") Pitch KK® Wire-To-Board Header, Right Angle, With Friction Lock, 3 Circuits
0
3
3
MOLEX THD
MOLEX_22-05-7078
2.54mm (.100") Pitch KK® Wire-To-Board Header, Right Angle, With Friction Lock, 7 Circuits
0
7
7
MOLEX THD
MOLEX_22-11-2032
2.54mm (.100") Pitch KK® 254 Vertical Wire-to-Board Header, with Friction Lock, 3 Circuits, Gold (Au) Plating
0
3
3
MOLEX THD
MOLEX_22-27-2021
2.54mm (.100") Pitch KK® Header, Single Row, Vertical, 2 Circuits
NetTie
NetTie-2_THT_Pad0.3mm
Net tie, 2 pin, 0.3mm round THT pads
net tie
0
2
2
MOLEX THD
MOLEX_22-27-2031
2.54mm (.100") Pitch KK® Header, Single Row, Vertical, 3 Circuits
0
3
3
MOLEX THD
MOLEX_22-27-2041
2.54mm (.100") Pitch KK® Header, Single Row, Vertical, 4 Circuits
0
4
4
MOLEX THD
MOLEX_22-27-2051
2.54mm (.100") Pitch KK® Header, Single Row, Vertical, 5 Circuits
0
5
5
MOLEX THD
MOLEX_22-27-2061
2.54mm (.100") Pitch KK® Header, Single Row, Vertical, 6 Circuits
0
6
6
MOLEX THD
MOLEX_22-27-2081
2.54mm (.100") Pitch KK® Header, Single Row, Vertical, 8 Circuits
0
8
8
MOLEX THD
MOLEX_26-48-1135
3.96mm (.156") Pitch KK® Header, Breakaway, Vertical, Square Pin, with Friction Lock, 13 Circuits, Tin (Sn) Plating
0
13
13
MOLEX THD
MOLEX_26-60-3040
3.96mm (.156") Pitch KK® Solid Header,Right Angle, 4 Circuits, Tin (Sn) Plating
0
4
4
MOLEX THD
MOLEX_26-60-4020
3.96mm (.156") Pitch KK® Solid Header, Vertical, Friction Lock, 2 Circuits, Tin (Sn) Plating
NetTie
NetTie-2_THT_Pad1.0mm
Net tie, 2 pin, 1.0mm round THT pads
net tie
0
2
2
MOLEX THD
MOLEX_26-60-4030
3.96mm (.156") Pitch KK® Solid Header, Vertical, Friction Lock, 3 Circuits, Tin (Sn) Plating
NetTie
NetTie-3_SMD_Pad0.5mm
Net tie, 3 pin, 0.5mm square SMD pads
net tie
0
3
3
MOLEX THD
MOLEX_26-60-4040
3.96mm (.156") Pitch KK® Solid Header, Vertical, Friction Lock, 4 Circuits, Tin (Sn) Plating
0
4
4
MOLEX THD
MOLEX_26-60-4050
3.96mm (.156") Pitch KK® Solid Header, Vertical, Friction Lock, 5 Circuits, Tin (Sn) Plating
0
5
5
MOLEX THD
MOLEX_26-60-4060
3.96mm (.156") Pitch KK® Solid Header, Vertical, Friction Lock, 6 Circuits, Tin (Sn) Plating
0
6
6
MOLEX THD
MOLEX_26-60-4070
3.96mm (.156") Pitch KK® Solid Header, Vertical, Friction Lock, 7 Circuits, Tin (Sn) Plating
0
7
7
MOLEX THD
MOLEX_26-60-5030
3 Circuits, 3.96mm (.156) Pitch KK® Wire-To-Board Right Angle Header With Friction Lock
NetTie
NetTie-3_SMD_Pad2.0mm
Net tie, 3 pin, 2.0mm square SMD pads
net tie
0
3
3
MOLEX THD
MOLEX_26-60-5040
3.96mm (.156") Pitch KK® Solid Header,Right Angle, 4 Circuits, Tin (Sn) Plating
0
4
4
MOLEX THD
MOLEX_26-62-4030
3.96mm (.156") Pitch KK® Solid Header, Vertical, Friction Lock, 3 Circuits Without Contact Number 2, Tin (Sn) Plating
0
2
2
MOLEX THD
MOLEX_39-28-1023
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Vertical, without Snap-in Plastic Peg PCB Lock, 2 Circuits
0
2
2
MOLEX THD
MOLEX_39-28-1043
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Vertical, without Snap-in Plastic Peg PCB Lock, 4 Circuits
0
4
4
MOLEX THD
MOLEX_39-28-1063
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Vertical, without Snap-in Plastic Peg PCB Lock, 6 Circuits
0
6
6
MOLEX THD
MOLEX_39-28-1083
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Vertical, without Snap-in Plastic Peg PCB Lock, 8 Circuits
0
8
8
MOLEX THD
MOLEX_39-28-1103
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Vertical, without Snap-in Plastic Peg PCB Lock, 10 Circuits
NetTie
NetTie-3_THT_Pad0.3mm
Net tie, 3 pin, 0.3mm round THT pads
net tie
0
10
10
MOLEX THD
MOLEX_39-28-1123
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Vertical, without Snap-in Plastic Peg PCB Lock, 12 Circuits
0
12
12
MOLEX THD
MOLEX_39-28-1163
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Vertical, without Snap-in Plastic Peg PCB Lock, 16 Circuits
0
16
16
MOLEX THD
MOLEX_39-28-1183
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Vertical, without Snap-in Plastic Peg PCB Lock, 18 Circuits
0
18
18
MOLEX THD
MOLEX_39-28-1203
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Vertical, without Snap-in Plastic Peg PCB Lock, 20 Circuits
0
20
20
MOLEX THD
MOLEX_39-28-1223
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Vertical, without Snap-in Plastic Peg PCB Lock, 22 Circuits
0
22
22
MOLEX THD
MOLEX_39-29-1028
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Right Angle, with PCB Mounting Flange, 2 Circuits
0
4
4
MOLEX THD
MOLEX_39-29-1087
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Right Angle, with PCB Mounting Flange, 8 Circuits
0
10
10
MOLEX THD
MOLEX_39-30-0040
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Right Angle with Snap-in Plastic Peg PCB Lock, 4 Circuits
0
4
4
MOLEX THD
MOLEX_39-30-0060
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Right Angle with Snap-in Plastic Peg PCB Lock, 8 Circuits
0
6
6
MOLEX THD
MOLEX_39-30-1080
4.20mm (.165") Pitch Mini-Fit Jr. Header, Dual Row, Right Angle with Snap-in Plastic Peg PCB Lock, 8 Circuits
0
8
8
MOLEX THD
MOLEX_39-30-3045
4.20mm (.165") Pitch Mini-Fit Jr. Header, Single Row, Right Angle, with Snap-in Plastic Peg PCB Lock, 4 Circuits
0
4
4
MOLEX THD
MOLEX_42819-3223
50A, 600V, 10mm Pitch, 3 Circuits Single Row Mini-Fit Sr. Vertical Power Header
3
3
NetTie
NetTie-3_THT_Pad1.0mm
Net tie, 3 pin, 1.0mm round THT pads
net tie
0
8
5
MOLEX THD
MOLEX_43045-0401
3.00mm (.118") Pitch Micro-Fit 3.0™ Header, Dual Row, Right Angled, with PCB Polarizing Peg, 4 Circuits
3
3
NetTie
NetTie-4_SMD_Pad0.5mm
Net tie, 4 pin, 0.5mm square SMD pads
net tie
0
4
4
MOLEX THD
MOLEX_43045-0800
3.00mm (.118") Pitch Micro-Fit 3.0™ Header, Dual Row, Righ Angled, with PCB Polarizing Peg, 8 Circuits
0
8
8
MOLEX THD
MOLEX_43045-1012
3.00mm (.118") Pitch Micro-Fit 3.0™ Header, Dual Row, Vertical, with PCB Polarizing Peg, 10 Circuits
0
10
10
MOLEX THD
MOLEX_43045-1200
3.00mm (.118") Pitch Micro-Fit 3.0™ Header, Dual Row, Righ Angled, with PCB Polarizing Peg, 12 Circuits
0
12
12
MOLEX THD
MOLEX_43045-1212
3.00mm (.118") Pitch Micro-Fit 3.0™ Header, Dual Row, Vertical, with PCB Polarizing Peg, 12 Circuits
0
12
12
MOLEX THD
MOLEX_43045-2012
3.00mm (.118") Pitch Micro-Fit 3.0™ Header, Dual Row, Vertical, with PCB Polarizing Peg, 20 Circuits
0
20
20
MOLEX THD
MOLEX_43160-2104
7.50mm Pitch 4 Circuits Sabre™ Vertical Header (Glow Wire Compatible) with Board Lock
0
10
6
MOLEX THD
MOLEX_43650-0200
3.00mm (.118") Pitch Micro-Fit 3.0™ Header, Single Row, Right Angled, with PCB Polarizing Peg, 2 Circuits
0
2
2
MOLEX THD
MOLEX_43650-0400
3.00mm (.118") Pitch Micro-Fit 3.0™ Header, Single Row, Right Angled, with PCB Polarizing Peg, 4 Circuits
NetTie
NetTie-4_SMD_Pad2.0mm
Net tie, 4 pin, 2.0mm square SMD pads
net tie
0
4
4
MOLEX THD
MOLEX_43879-0022
4.20mm Pitch, Mini-Fit® CPI (Compliant Pin Interface) 4 Circuits Dual Row Vertical Header
NetTie
NetTie-4_THT_Pad0.3mm
Net tie, 4 pin, 0.3mm round THT pads
net tie
0
4
4
MOLEX THD
MOLEX_44428-1201
3.00mm (.118") Pitch Micro-Fit 3.0™ Header, Dual Row, Righ Angled, with Snap-in Plastic Peg PCB Lock, 12 Circuits
0
12
12
MOLEX THD
MOLEX_45984-4141
4 Power Contacts + 24 Signals Contacts, EXTreme LPHPower™ Low-Profile Right Angle Receptacle Header
0
44
28
MOLEX THD
MOLEX_46114-4240
4 Power Contacts + 24 Signals Contacts, EXTreme LPHPower™ Low-Profile Vertical Receptacle Header
0
40
28
MOLEX THD
MOLEX_48037-0001
Right Angled Through Hole Shielded USB Plug, Type A
0
8
7
MOLEX THD
MOLEX_52030-0629
6 Contacts, 1.0mm Pitch, Vertical Through-Hole FCC/FPC Connector
0
6
6
MOLEX THD
MOLEX_53047-0210
1.25mm Pitch PicoBlade™ Wire-to-Board 2 Circuits Vertical Header with Friction Lock
0
2
2
MOLEX THD
MOLEX_53047-0410
1.25mm Pitch PicoBlade™ Wire-to-Board 4 Circuits Vertical Header with Friction Lock
NetTie
NetTie-4_THT_Pad1.0mm
Net tie, 4 pin, 1.0mm round THT pads
net tie
0
4
4
MOLEX THD
MOLEX_53047-0510
1.25mm Pitch PicoBlade™ Wire-to-Board 5 Circuits Vertical Header with Friction Lock
0
5
5
MOLEX THD
MOLEX_55932-0710
2.00mm Pitch MicroClasp Wire-to-Board Header, Single Row, Vertical, 7 Circuits, with PCB Locator
0
7
7
MOLEX THD
MOLEX_70246-1004
2.54mm Pitch C-Grid® Header, Low Profile, Dual Row, Vertical, Shrouded Header
0
10
10
MOLEX THD
MOLEX_71430-0008
68 Positions, Pitch 0.8mm, Very Hight Density Right Angle Receptacle, VHDCI Standard (Recommended PCB Thickness: 1.6mm)
0
70
70
MOLEX THD
MOLEX_71430-0012
68 Positions, Pitch 0.8mm, Very Hight Density Right Angle Receptacle, VHDCI Standard (Recommended PCB Thickness: 2.36mm)
0
70
70
MOLEX THD
MOLEX_71430-0013
68 Positions, Pitch 0.8mm, Very Hight Density Right Angle Receptacle, VHDCI Standard (Recommended PCB Thickness: 1.6mm)
0
70
70
MOLEX THD
MOLEX_74337-0015
2x68 Positions, Pitch 0.8mm, Very Hight Density Right Angle Dual Stacked VHDCI Receptacle
0
140
140
MOLEX THD
MOLEX_74737-0009
SFP+ 1x1 Press Fit Cage
0
20
20
MOLEX THD
MOLEX_74737-0111
SFP+ 1x1 Cage
0
20
20
MOLEX THD
MOLEX_75640-5001
Stacked 2x1 SFP Cage, Medium Height Assembly, Press Fit Tails with 4 Light Pipes
0
53
53
MOLEX THD
MOLEX_76001-0010
250V 50A Press-Fit Tails (10) Screw Terminal (M3) EXTreme ZPower™ Connector for 3.18mm Thick PC Board
0
10
1
MOLEX THD
MOLEX_76825-0002
2 Circuits, MEGA-FIT® Right-Angle Power Header
0
2
2
MOLEX THD
MOLEX_76825-0008
8 Circuits, 5.7mm Pitch, MEGA-FIT® Right-Angle Power Header
0
8
8
MOLEX THD
MOLEX_76829-0106
6 Circuits, 5.7mm Pitch, MEGA-FIT® Vertical Power Header
0
6
6
MOLEX THD
MOLEX_76866-1011
1x1 iPass™ HD Cage and Receptacle, Lead-Free
0
43
43
MOLEX THD
MOLEX_79107-7006
2.00mm (.079") Pitch Milli-Grid™ Receptacle, Vertical, Through Hole, Dual Row, 14 Circuits
0
14
14
MOLEX THD
MOLEX_83611-9006
1.27mm Pitch Commercial Micro D, PCB Mount, Right Angle Plug, 9 Circuits
0
11
11
MOLEX THD
MOLEX_83612-9020
1.27mm Pitch Commercial Micro D, PCB Mount, Right Angle Plug, 15 Circuits
0
17
17
MOLEX THD
MOLEX_83614-9012
1.27mm Pitch Commercial Micro D, PCB Mount, Right Angle Plug, 25 Circuits
0
27
27
MOLEX THD
MOLEX_87831-1420
2.00mm (.079") Pitch Milli-Grid™ Header, Vertical, Shrouded, Center Polarization Slot, Locking Window, 14 Circuits
0
14
14
MOLEX THD
MOLEX_87833-1420
2.00mm (.079") Pitch Milli-Grid™ Header, Right Angle, Shrouded, Center Polarization Slot, Locking Window, 14 Circuits
0
14
14
MOLEX THD
MOLEX_87833-1420_a
2.00mm (.079") Pitch Milli-Grid™ Header, Right Angle, Shrouded, Center Polarization Slot, Locking Window, 14 Circuits
0
14
14
MOLEX THD
MOLEX_90121-0763
2.54mm (.100") Pitch, 3 Circuits Single Row Right Angle C-Grid III Header
0
3
3
MOLEX THD
MOLEX_90121-0772
2.54mm (.100") Pitch, 12 Circuits Single Row Right Angle C-Grid III Header
0
12
12
MOLEX THD
MOLEX_90130-1220
2.54mm (.100") Pitch C-Grid III Header, Dual Row, Vertical, Shrouded, 20 Circuits
0
20
20
MOLEX THD
MOLEX_90136-1206
2.54mm (.100") Pitch C-Grid III Header, Single Row, Vertical, Shrouded, 6 Circuits
0
6
6
MOLEX THD
MOLEX_90136-1212
2.54mm (.100") Pitch C-Grid III Header, Single Row, Vertical, Shrouded, 12 Circuits
0
12
12
MOLEX THD
MOLEX_90136-2205
6 Circuits, 2.54mm (.100") Pitch C-Grid III™ Single Row Right Angle Shrouded Header
0
5
5
MOLEX THD
MOLEX_171856-0006
6 Circuits , 2.54mm (.100") Pitch, Single Row Vertical KK® Header with Friction Lock, Tin (Sn) Plating, Pin Length 12.95mm
0
6
6
MOLEX THD
MOLEX_171856-0008
8 Circuits , 2.54mm (.100") Pitch, Single Row Vertical KK® Header with Friction Lock, Tin (Sn) Plating, Pin Length 12.95mm
0
8
8
MOLEX THD
MOLEX_500075-1517
Straight, USB Serie Mini-B Type 2 Through Hole Receptacle
0
7
6
MOLEX THD
MOLEX_386307810
11.13mm (.438") Pitch Header, BTS 600V No MTG Ends, Std Length (63A5XX-C)
0
10
10
MOLEX THD
MOLEX_462070104
4.2mm Pitch, Mini-Fit Jr, Dual Row, Vertical, with PCB Pegs, 4 Circuits
0
4
4
MOLEX THD
MOLEX_462070106
4.2mm Pitch, Mini-Fit Jr, Dual Row, Vertical, with PCB Pegs, 6 Circuits
0
6
6
MOLEX THD
MOLEX_758000001
0.75mm (.030") Pitch Advanced Mezzanine Card Connector, B+ Style, Right Angle, 170 Circuit, 0.76µm (30µ") Gold (Au), Standard Height, with PCB Locator, Tin (Sn) Tail Plating
0
200
172
pcb/crate_front_panel/Crate-Front-Panel.kicad_pcb
View file @ 24ac5c0e
......@@ -149,6 +149,190 @@
(add_net "Net-(RL2-Pad24)")
)
(module "ICs And Semiconductors SMD:SOD2512X110N" (layer B.Cu) (tedit 0) (tstamp 5E675B38)
(at 173.0756 83.3628 180)
(descr "Small Outline Diode (SOD-323), 1.70mm W X 1.25mm L X 1.10mm H body, IPC Medium Density")
(path /5E654428)
(attr smd)
(fp_text reference D2 (at -3.6068 -0.0508) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value PESD5V0S1UA (at 0 -1.976) (layer B.Fab) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2 -0.95) (end 2 -0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start 2 -0.95) (end 2 0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.95) (end 2 0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.95) (end -2 0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start 0 -0.5) (end 0 0.5) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.5 0) (end 0.5 0) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.85 -0.625) (end 0.85 -0.625) (layer B.Fab) (width 0.1))
(fp_line (start 0.85 -0.625) (end 0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 0.625) (end 0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 -0.625) (end -0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 -0.625) (end -0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.75 -0.625) (end -0.75 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.65 -0.625) (end -0.65 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.55 -0.625) (end -0.55 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.45 -0.625) (end -0.45 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.35 -0.625) (end -0.35 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.25 -0.625) (end -0.25 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.15 -0.625) (end -0.15 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 0.65) (end 0.85 0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.85 -0.65) (end 0.85 -0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.5 -0.65) (end -0.5 0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.3 -0.65) (end -0.3 0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.1 -0.65) (end -0.1 0.65) (layer B.SilkS) (width 0.2))
(fp_circle (center 0 0) (end 0.35 0) (layer B.CrtYd) (width 0.05))
(fp_circle (center -1.5 0.75) (end -1.375 0.75) (layer B.SilkS) (width 0.25))
(pad 1 smd rect (at -1.3 0 180) (size 0.9 0.5) (layers B.Cu B.Paste B.Mask)
(net 17 "Net-(D2-Pad1)"))
(pad 2 smd rect (at 1.3 0 180) (size 0.9 0.5) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
(model "${CERN}/SOD2512X110N(SOD-323).stp"
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module "ICs And Semiconductors SMD:SOD2512X110N" (layer B.Cu) (tedit 0) (tstamp 5E4CDE8C)
(at 107.3658 83.2104)
(descr "Small Outline Diode (SOD-323), 1.70mm W X 1.25mm L X 1.10mm H body, IPC Medium Density")
(path /5E618AD5)
(attr smd)
(fp_text reference D1 (at -3.4036 0) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value PESD5V0S1UA (at 0 -1.976) (layer B.Fab) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2 -0.95) (end 2 -0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start 2 -0.95) (end 2 0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.95) (end 2 0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.95) (end -2 0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start 0 -0.5) (end 0 0.5) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.5 0) (end 0.5 0) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.85 -0.625) (end 0.85 -0.625) (layer B.Fab) (width 0.1))
(fp_line (start 0.85 -0.625) (end 0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 0.625) (end 0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 -0.625) (end -0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 -0.625) (end -0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.75 -0.625) (end -0.75 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.65 -0.625) (end -0.65 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.55 -0.625) (end -0.55 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.45 -0.625) (end -0.45 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.35 -0.625) (end -0.35 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.25 -0.625) (end -0.25 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.15 -0.625) (end -0.15 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 0.65) (end 0.85 0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.85 -0.65) (end 0.85 -0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.5 -0.65) (end -0.5 0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.3 -0.65) (end -0.3 0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.1 -0.65) (end -0.1 0.65) (layer B.SilkS) (width 0.2))
(fp_circle (center 0 0) (end 0.35 0) (layer B.CrtYd) (width 0.05))
(fp_circle (center -1.5 0.75) (end -1.375 0.75) (layer B.SilkS) (width 0.25))
(pad 1 smd rect (at -1.3 0) (size 0.9 0.5) (layers B.Cu B.Paste B.Mask)
(net 4 "Net-(D1-Pad1)"))
(pad 2 smd rect (at 1.3 0) (size 0.9 0.5) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
(model "${CERN}/SOD2512X110N(SOD-323).stp"
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Pads:MTG300_600 (layer F.Cu) (tedit 0) (tstamp 5E224ECF)
(at 78.4118 46.3282)
(descr "Plated Through Hole: Hole Dia.=3.0mm Pad Dia.=6.0mm")
(path /5E2EDAFF)
(fp_text reference B4 (at -0.2306 4.3702) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value PLATED_HOLE3.0_PAD6.0 (at 0 4.102) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Mask)
(net 8 "Net-(B4-Pad1)"))
)
(module Pads:MTG300_600 (layer F.Cu) (tedit 0) (tstamp 5E224ECA)
(at 204.4118 46.3282)
(descr "Plated Through Hole: Hole Dia.=3.0mm Pad Dia.=6.0mm")
(path /5E2EBCD9)
(fp_text reference B3 (at 0.236 5.0052) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value PLATED_HOLE3.0_PAD6.0 (at 0 4.102) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Mask)
(net 7 "Net-(B3-Pad1)"))
)
(module Pads:MTG300_600 (layer F.Cu) (tedit 0) (tstamp 5E224EC5)
(at 204.4118 90.3282)
(descr "Plated Through Hole: Hole Dia.=3.0mm Pad Dia.=6.0mm")
(path /5E2E9F5D)
(fp_text reference B2 (at 0 -4.102) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value PLATED_HOLE3.0_PAD6.0 (at 0 4.102) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Mask)
(net 6 "Net-(B2-Pad1)"))
)
(module Pads:MTG300_600 (layer F.Cu) (tedit 0) (tstamp 5E224EC0)
(at 78.4118 90.3282)
(descr "Plated Through Hole: Hole Dia.=3.0mm Pad Dia.=6.0mm")
(path /5E2D9D8A)
(fp_text reference B1 (at 0 -4.102) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value PLATED_HOLE3.0_PAD6.0 (at 0 4.102) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Mask)
(net 5 "Net-(B1-Pad1)"))
)
(module "Resistors SMD:RESC3216X65N" (layer B.Cu) (tedit 0) (tstamp 5E221A12)
(at 107.3658 86.1314 180)
(descr "Chip Resistor, EIA 1206, Metric 3216, Body 3.2x1.6mm, IPC Medium Density")
(path /5E235334)
(attr smd)
(fp_text reference R1 (at 3.429 0.0254) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value R1206_10R_1%_0.25W_200PPM (at 0 -2.176) (layer B.Fab) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2.3 -1.15) (end -2.3 1.15) (layer B.CrtYd) (width 0.05))
(fp_line (start 2.3 -1.15) (end 2.3 1.15) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 1.15) (end 2.3 1.15) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 -1.15) (end 2.3 -1.15) (layer B.CrtYd) (width 0.05))
(fp_line (start 0 -0.3) (end 0 0.3) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.3 0) (end 0.3 0) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.6 -0.8) (end -1.6 0.8) (layer B.Fab) (width 0.1))
(fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer B.Fab) (width 0.1))
(fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer B.Fab) (width 0.1))
(fp_line (start -1.6 0.8) (end 1.6 0.8) (layer B.Fab) (width 0.1))
(fp_line (start -0.5 0.9) (end 0.5 0.9) (layer B.SilkS) (width 0.2))
(fp_line (start -0.5 -0.9) (end 0.5 -0.9) (layer B.SilkS) (width 0.2))
(pad 1 smd rect (at -1.45 0 180) (size 1.15 1.8) (layers B.Cu B.Paste B.Mask)
(net 20 /RST_IN))
(pad 2 smd rect (at 1.45 0 180) (size 1.15 1.8) (layers B.Cu B.Paste B.Mask)
(net 4 "Net-(D1-Pad1)"))
(model ${CERN}/RESC3216X65N.stp
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module "MOLEX THD:MOLEX_22-27-2021" (layer B.Cu) (tedit 0) (tstamp 5E639633)
(at 139.7254 84.6582 90)
(descr "2.54mm (.100\") Pitch KK® Header, Single Row, Vertical, 2 Circuits")
......@@ -324,7 +508,7 @@
(net 20 /RST_IN))
(pad 2 smd rect (at 1.45 0) (size 1.15 1.8) (layers B.Cu B.Paste B.Mask)
(net 17 "Net-(D2-Pad1)"))
(model RESC3216X65N.stp
(model ${CERN}/RESC3216X65N.stp
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
......@@ -765,87 +949,6 @@
)
)
(module "ICs And Semiconductors SMD:SOD2512X110N" (layer B.Cu) (tedit 0) (tstamp 5E675B38)
(at 173.0756 83.3628 180)
(descr "Small Outline Diode (SOD-323), 1.70mm W X 1.25mm L X 1.10mm H body, IPC Medium Density")
(path /5E654428)
(attr smd)
(fp_text reference D2 (at -3.683 -0.1778 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value PESD5V0S1UA (at 0 -1.976 180) (layer B.Fab) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2 -0.95) (end 2 -0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start 2 -0.95) (end 2 0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.95) (end 2 0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.95) (end -2 0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start 0 -0.5) (end 0 0.5) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.5 0) (end 0.5 0) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.85 -0.625) (end 0.85 -0.625) (layer B.Fab) (width 0.1))
(fp_line (start 0.85 -0.625) (end 0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 0.625) (end 0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 -0.625) (end -0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 -0.625) (end -0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.75 -0.625) (end -0.75 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.65 -0.625) (end -0.65 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.55 -0.625) (end -0.55 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.45 -0.625) (end -0.45 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.35 -0.625) (end -0.35 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.25 -0.625) (end -0.25 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.15 -0.625) (end -0.15 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 0.65) (end 0.85 0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.85 -0.65) (end 0.85 -0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.5 -0.65) (end -0.5 0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.3 -0.65) (end -0.3 0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.1 -0.65) (end -0.1 0.65) (layer B.SilkS) (width 0.2))
(fp_circle (center 0 0) (end 0.35 0) (layer B.CrtYd) (width 0.05))
(fp_circle (center -1.5 0.75) (end -1.375 0.75) (layer B.SilkS) (width 0.25))
(pad 1 smd rect (at -1.3 0 180) (size 0.9 0.5) (layers B.Cu B.Paste B.Mask)
(net 17 "Net-(D2-Pad1)"))
(pad 2 smd rect (at 1.3 0 180) (size 0.9 0.5) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
)
(module "ICs And Semiconductors SMD:SOD2512X110N" (layer B.Cu) (tedit 0) (tstamp 5E4CDE8C)
(at 107.3658 83.2104)
(descr "Small Outline Diode (SOD-323), 1.70mm W X 1.25mm L X 1.10mm H body, IPC Medium Density")
(path /5E618AD5)
(attr smd)
(fp_text reference D1 (at 3.429 0.0762) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value PESD5V0S1UA (at 0 -1.976) (layer B.Fab) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2 -0.95) (end 2 -0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start 2 -0.95) (end 2 0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.95) (end 2 0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.95) (end -2 0.95) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.85 -0.625) (end 0.85 -0.625) (layer B.Fab) (width 0.1))
(fp_line (start 0.85 -0.625) (end 0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 0.625) (end 0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 -0.625) (end -0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 -0.625) (end -0.85 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.75 -0.625) (end -0.75 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.65 -0.625) (end -0.65 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.55 -0.625) (end -0.55 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.45 -0.625) (end -0.45 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.35 -0.625) (end -0.35 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.25 -0.625) (end -0.25 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.15 -0.625) (end -0.15 0.625) (layer B.Fab) (width 0.1))
(fp_line (start -0.85 0.65) (end 0.85 0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.85 -0.65) (end 0.85 -0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.5 -0.65) (end -0.5 0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.3 -0.65) (end -0.3 0.65) (layer B.SilkS) (width 0.2))
(fp_line (start -0.1 -0.65) (end -0.1 0.65) (layer B.SilkS) (width 0.2))
(fp_circle (center -1.5 0.75) (end -1.375 0.75) (layer B.SilkS) (width 0.25))
(pad 1 smd rect (at -1.3 0) (size 0.9 0.5) (layers B.Cu B.Paste B.Mask)
(net 4 "Net-(D1-Pad1)"))
(pad 2 smd rect (at 1.3 0) (size 0.9 0.5) (layers B.Cu B.Paste B.Mask)
(net 3 GND))
)
(module Relays:REL_FINDER_40.52 locked (layer B.Cu) (tedit 0) (tstamp 5E4C1409)
(at 106.3752 64.4888 90)
(descr "8 Leads, 2 Pole 16A Relay, FINDER 40.52 Series, Body 29mm x 12.4mm")
......@@ -1142,95 +1245,6 @@
)
)
(module Pads:MTG300_600 (layer F.Cu) (tedit 0) (tstamp 5E224ECF)
(at 78.4118 46.3282)
(descr "Plated Through Hole: Hole Dia.=3.0mm Pad Dia.=6.0mm")
(path /5E2EDAFF)
(fp_text reference B4 (at 4.4938 0.103) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value PLATED_HOLE3.0_PAD6.0 (at 0 4.102) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Mask)
(net 8 "Net-(B4-Pad1)"))
)
(module Pads:MTG300_600 (layer F.Cu) (tedit 0) (tstamp 5E224ECA)
(at 204.4118 46.3282)
(descr "Plated Through Hole: Hole Dia.=3.0mm Pad Dia.=6.0mm")
(path /5E2EBCD9)
(fp_text reference B3 (at -4.567 0.0522) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value PLATED_HOLE3.0_PAD6.0 (at 0 4.102) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Mask)
(net 7 "Net-(B3-Pad1)"))
)
(module Pads:MTG300_600 (layer F.Cu) (tedit 0) (tstamp 5E224EC5)
(at 204.4118 90.3282)
(descr "Plated Through Hole: Hole Dia.=3.0mm Pad Dia.=6.0mm")
(path /5E2E9F5D)
(fp_text reference B2 (at -4.4376 0.045) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value PLATED_HOLE3.0_PAD6.0 (at 0 4.102) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Mask)
(net 6 "Net-(B2-Pad1)"))
)
(module Pads:MTG300_600 (layer F.Cu) (tedit 0) (tstamp 5E224EC0)
(at 78.4118 90.3282)
(descr "Plated Through Hole: Hole Dia.=3.0mm Pad Dia.=6.0mm")
(path /5E2D9D8A)
(fp_text reference B1 (at 4.5192 0.045) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value PLATED_HOLE3.0_PAD6.0 (at 0 4.102) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 0) (size 6 6) (drill 3) (layers *.Cu *.Mask)
(net 5 "Net-(B1-Pad1)"))
)
(module Marble:RESC3216X65N (layer B.Cu) (tedit 5CACA4AC) (tstamp 5E221A12)
(at 107.3658 86.1314 180)
(descr "Chip Resistor, EIA 1206, Metric 3216, Body 3.2x1.6mm, IPC Medium Density")
(path /5E235334)
(fp_text reference R1 (at -3.4544 0.2286) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value R1206_10R_1%_0.25W_200PPM (at 0 -2.176) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -2.3 -1.15) (end -2.3 1.15) (layer B.CrtYd) (width 0.05))
(fp_line (start 2.3 -1.15) (end 2.3 1.15) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 1.15) (end 2.3 1.15) (layer B.CrtYd) (width 0.05))
(fp_line (start -2.3 -1.15) (end 2.3 -1.15) (layer B.CrtYd) (width 0.05))
(fp_line (start 0 -0.3) (end 0 0.3) (layer B.Fab) (width 0.05))
(fp_line (start -0.3 0) (end 0.3 0) (layer B.Fab) (width 0.05))
(fp_line (start -1.6 -0.8) (end -1.6 0.8) (layer B.Fab) (width 0.1))
(fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer B.Fab) (width 0.1))
(fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer B.Fab) (width 0.1))
(fp_line (start -1.6 0.8) (end 1.6 0.8) (layer B.Fab) (width 0.1))
(fp_line (start -0.5 0.9) (end 0.5 0.9) (layer B.SilkS) (width 0.2))
(fp_line (start -0.5 -0.9) (end 0.5 -0.9) (layer B.SilkS) (width 0.2))
(pad 1 smd rect (at -1.45 0 180) (size 1.15 1.8) (layers B.Cu B.Paste B.Mask)
(net 20 /RST_IN) (solder_mask_margin 0.102))
(pad 2 smd rect (at 1.45 0 180) (size 1.15 1.8) (layers B.Cu B.Paste B.Mask)
(net 4 "Net-(D1-Pad1)") (solder_mask_margin 0.102))
(model ${CERN}/RESC3216X65N.stp
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module "Miscellaneous THD:WAGO_236-402" (layer B.Cu) (tedit 0) (tstamp 5E2219B0)
(at 85.0392 57.4802 270)
(descr "16A 250VAC 2 Way PCB Terminal Block, Pitch 5mm, CAGE CLAMP® Connection, Wire Size Max: 2.5mm²")
......
pcb/crate_front_panel/Crate-Front-Panel.sch
View file @ 24ac5c0e
......@@ -43,7 +43,7 @@ U 1 1 5E235334
P 4500 3000
F 0 "R1" H 4650 3197 50 0000 C CNN
F 1 "R1206_10R_1%_0.25W_200PPM" H 4500 2790 60 0001 L CNN
F 2 "RESC3216X65N" H 4500 1980 60 0001 L CNN
F 2 "Resistors SMD:RESC3216X65N" H 4500 1980 60 0001 L CNN
F 3 "\\\\cern.ch\\dfs\\Applications\\Altium\\Datasheets\\R1206_NIC_NRC.pdf" H 4500 2610 60 0001 L CNN
F 4 "10" H 4650 3106 50 0000 C CNN "~"
F 5 "R1206_10R_1%_0.25W_200PPM" H 4500 2520 60 0001 L CNN "Part Number"
......@@ -581,7 +581,7 @@ U 1 1 5E6542EE
P 4500 5850
F 0 "R2" H 4650 6047 50 0000 C CNN
F 1 "R1206_10R_1%_0.25W_200PPM" H 4500 5640 60 0001 L CNN
F 2 "RESC3216X65N" H 4500 4830 60 0001 L CNN
F 2 "Resistors SMD:RESC3216X65N" H 4500 4830 60 0001 L CNN
F 3 "\\\\cern.ch\\dfs\\Applications\\Altium\\Datasheets\\R1206_NIC_NRC.pdf" H 4500 5460 60 0001 L CNN
F 4 "10" H 4650 5956 50 0000 C CNN "~"
F 5 "R1206_10R_1%_0.25W_200PPM" H 4500 5370 60 0001 L CNN "Part Number"
......
pcb/crate_front_panel/Crate-Front-Panel.sch-bak
View file @ 24ac5c0e
......@@ -638,50 +638,50 @@ $EndComp
$Comp
L Relays:REL_FINDER_40.52.7.024.0000 RL2
U 1 1 5E654349
P 5400 5850
F 0 "RL2" H 5600 6025 50 0000 C CNN
F 1 "REL_FINDER_40.52.7.005.0000" H 5400 5595 50 0001 L CNN
F 2 "Relays:REL_FINDER_40.52" H 5400 5520 50 0001 L CNN
F 3 " " H 5400 5445 50 0001 L CNN
F 4 " " H 5400 5145 50 0001 L CNN "Comment"
F 5 "REL_FINDER_40.52.7.005.0000" H 5400 5370 50 0001 L CNN "Part Number"
F 6 "REL_FINDER_40.52" H 5400 5295 50 0001 L CNN "Library Ref"
F 7 "SchLib\\Relays.SchLib" H 5400 5220 50 0001 L CNN "Library Path"
F 8 "Standard" H 5400 5070 50 0001 L CNN "Component Kind"
F 9 "Standard" H 5400 4995 50 0001 L CNN "Component Type"
F 10 "8" H 5400 4920 50 0001 L CNN "Pin Count"
F 11 " " H 5400 4845 50 0001 L CNN "Case"
F 12 "PcbLib\\Relays.PcbLib" H 5400 4770 50 0001 L CNN "Footprint Path"
F 13 "REL_FINDER_40.52" H 5400 4695 50 0001 L CNN "Footprint Ref"
F 14 "8 Leads, 2 Poles 8A Relay, FINDER 40.52 Serie, Body 29mm x 12.4mm" H 5400 4620 50 0001 L CNN "PackageDescription"
F 15 " " H 5400 4545 50 0001 L CNN "Family"
F 16 "Yes" H 5400 4470 50 0001 L CNN "Mounted"
F 17 "No" H 5400 4395 50 0001 L CNN "Socket"
F 18 "No" H 5400 4320 50 0001 L CNN "SMD"
F 19 "No" H 5400 4245 50 0001 L CNN "PressFit"
F 20 "Yes" H 5400 4170 50 0001 L CNN "Sense"
F 21 "Non-washable" H 5400 4095 50 0001 L CNN "Sense Comment"
F 22 "Not Recommended" H 5400 4020 50 0001 L CNN "Status"
F 23 "Sensitive (See Sensitive Field)" H 5400 3945 50 0001 L CNN "Status Comment"
F 24 " " H 5400 3870 50 0001 L CNN "SCEM"
F 25 "8A, DPDT PCB Relay, 40 Series" H 5400 3795 50 0001 L CNN "Part Description"
F 26 "FINDER" H 5400 3720 50 0001 L CNN "Manufacturer"
F 27 "40.52.7.005.0000" H 5400 3645 50 0001 L CNN "Manufacturer Part Number"
F 28 "25mm" H 5400 3570 50 0001 L CNN "ComponentHeight"
F 29 " " H 5400 3495 50 0001 L CNN "Manufacturer1 Example"
F 30 " " H 5400 3420 50 0001 L CNN "Manufacturer1 Part Number"
F 31 " " H 5400 3345 50 0001 L CNN "Manufacturer1 ComponentHeight"
F 32 " " H 5400 3270 50 0001 L CNN "ComponentLink1Description"
F 33 " " H 5400 3195 50 0001 L CNN "ComponentLink2Description"
F 34 "CERN DEM JLC" H 5400 3120 50 0001 L CNN "Author"
F 35 "10/03/13 00:00:00" H 5400 3045 50 0001 L CNN "CreateDate"
F 36 "08/30/18 00:00:00" H 5400 2970 50 0001 L CNN "LatestRevisionDate"
F 37 "Relays" H 5400 2895 50 0001 L CNN "Database Table Name"
F 38 "Eletro-mechanical.DbLib" H 5400 2820 50 0001 L CNN "Library Name"
F 39 "Relays" H 5400 2745 50 0001 L CNN "Footprint Library"
F 40 "This work is licensed under the Creative Commons CC-BY-SA 4.0 License. To the extent that circuit schematics that use Licensed Material can be considered to be ‘Adapted Material’, then the copyright holder waives article 3.b of the license with respect to these schematics." H 5400 2670 50 0001 L CNN "License"
1 5400 5850
1 0 0 -1
P 5800 5850
F 0 "RL2" H 6000 6025 50 0000 C CNN
F 1 "REL_FINDER_40.52.7.005.0000" H 5800 5595 50 0001 L CNN
F 2 "Relays:REL_FINDER_40.52" H 5800 5520 50 0001 L CNN
F 3 " " H 5800 5445 50 0001 L CNN
F 4 " " H 5800 5145 50 0001 L CNN "Comment"
F 5 "REL_FINDER_40.52.7.005.0000" H 5800 5370 50 0001 L CNN "Part Number"
F 6 "REL_FINDER_40.52" H 5800 5295 50 0001 L CNN "Library Ref"
F 7 "SchLib\\Relays.SchLib" H 5800 5220 50 0001 L CNN "Library Path"
F 8 "Standard" H 5800 5070 50 0001 L CNN "Component Kind"
F 9 "Standard" H 5800 4995 50 0001 L CNN "Component Type"
F 10 "8" H 5800 4920 50 0001 L CNN "Pin Count"
F 11 " " H 5800 4845 50 0001 L CNN "Case"
F 12 "PcbLib\\Relays.PcbLib" H 5800 4770 50 0001 L CNN "Footprint Path"
F 13 "REL_FINDER_40.52" H 5800 4695 50 0001 L CNN "Footprint Ref"
F 14 "8 Leads, 2 Poles 8A Relay, FINDER 40.52 Serie, Body 29mm x 12.4mm" H 5800 4620 50 0001 L CNN "PackageDescription"
F 15 " " H 5800 4545 50 0001 L CNN "Family"
F 16 "Yes" H 5800 4470 50 0001 L CNN "Mounted"
F 17 "No" H 5800 4395 50 0001 L CNN "Socket"
F 18 "No" H 5800 4320 50 0001 L CNN "SMD"
F 19 "No" H 5800 4245 50 0001 L CNN "PressFit"
F 20 "Yes" H 5800 4170 50 0001 L CNN "Sense"
F 21 "Non-washable" H 5800 4095 50 0001 L CNN "Sense Comment"
F 22 "Not Recommended" H 5800 4020 50 0001 L CNN "Status"
F 23 "Sensitive (See Sensitive Field)" H 5800 3945 50 0001 L CNN "Status Comment"
F 24 " " H 5800 3870 50 0001 L CNN "SCEM"
F 25 "8A, DPDT PCB Relay, 40 Series" H 5800 3795 50 0001 L CNN "Part Description"
F 26 "FINDER" H 5800 3720 50 0001 L CNN "Manufacturer"
F 27 "40.52.7.005.0000" H 5800 3645 50 0001 L CNN "Manufacturer Part Number"
F 28 "25mm" H 5800 3570 50 0001 L CNN "ComponentHeight"
F 29 " " H 5800 3495 50 0001 L CNN "Manufacturer1 Example"
F 30 " " H 5800 3420 50 0001 L CNN "Manufacturer1 Part Number"
F 31 " " H 5800 3345 50 0001 L CNN "Manufacturer1 ComponentHeight"
F 32 " " H 5800 3270 50 0001 L CNN "ComponentLink1Description"
F 33 " " H 5800 3195 50 0001 L CNN "ComponentLink2Description"
F 34 "CERN DEM JLC" H 5800 3120 50 0001 L CNN "Author"
F 35 "10/03/13 00:00:00" H 5800 3045 50 0001 L CNN "CreateDate"
F 36 "08/30/18 00:00:00" H 5800 2970 50 0001 L CNN "LatestRevisionDate"
F 37 "Relays" H 5800 2895 50 0001 L CNN "Database Table Name"
F 38 "Eletro-mechanical.DbLib" H 5800 2820 50 0001 L CNN "Library Name"
F 39 "Relays" H 5800 2745 50 0001 L CNN "Footprint Library"
F 40 "This work is licensed under the Creative Commons CC-BY-SA 4.0 License. To the extent that circuit schematics that use Licensed Material can be considered to be ‘Adapted Material’, then the copyright holder waives article 3.b of the license with respect to these schematics." H 5800 2670 50 0001 L CNN "License"
1 5800 5850
-1 0 0 -1
$EndComp
$Comp
L Relays:REL_FINDER_40.52.7.024.0000 RL2
......
pcb/crate_front_panel/Crate-Front-Panel.step
View file @ 24ac5c0e
This source diff could not be displayed because it is too large. You can view the blob instead.
pcb/power_backplane/Power Backplane.kicad_pcb
View file @ 24ac5c0e
......@@ -2755,17 +2755,17 @@
(clearance 3))
)
(module Pads:MTG270_500 (layer Top_PWR.Cu) (tedit 5DEF841E) (tstamp 5D68C171)
(at 99.06 147)
(module Pads:MTG270_500 (layer Top_PWR.Cu) (tedit 5E67F5B4) (tstamp 5D68C171)
(at 99.06 175.5)
(descr "Plated Through Hole: Hole Dia.=2.7mm Pad Dia.=5.0mm")
(path /5D8B9FA3)
(fp_text reference B2 (at 0 -3.602) (layer F.SilkS) hide
(fp_text reference B2 (at 0.5588 -1.585) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value PLATED_HOLE2.7_PAD5.0 (at 0 3.602) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 0 28.5) (size 8 8) (drill 2.7) (layers *.Cu B.Mask)
(pad 1 thru_hole circle (at 0 0) (size 8 8) (drill 2.7) (layers *.Cu B.Mask)
(net 7 GND))
)
......
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