Review of the architecture of the Converter from/to TTL to Blocking
Date: 20 July 2011
Present: Carlos Gil Soriano, Matthieu Cattin, Olivier Barriere, Emmanuel
Said
Architectural decisions
- Main characteristics
- VME64x form factor using Front and Rear Transition Module
- 8 or more channels with 1 selectable TTL/TTL-bar/Blocking-level input and two Blocking level outputs. TTL level outputs on front
- Front module
- hosts all active electronics (for easy replacement)
- hosts TTL outputs on front-panel for all channels (LEMO 00
connectors)
- one output per channel is good enough
- is there a need for TTL-bar outputs too?
- hosts switch to select input level used on inputs on RTM
- one switch for all channels
- switch should be located on PCB, not accessible on the front-panel so it cannot be set by accident
- LED on front to show selected input level
- LEDs on front to show received pulses on inputs (one for each input)
- Reprogrammable Xilinx
- via I2C port on VME bus, preferred
- via connector on front-panel
- Rear Transition Module RTM
- hosts LEMO 00 connectors
- leave enough space to allow usage of BNC to LEMO 00 adapters
- 2 parallel connected inputs (to allow loop-through or external termination)
- no input termination
- loopthrough output for each input (for looping or external 50 Ohm termination)
- input protection for each input
- even when input set to TTL level, it should not fail when blocking level input (30V) connected
- LED on rear panel to show selected input level (copy of LED on
Front module)
- no other LEDs needed (e.g. input pulses received, these are at the front-panel)
- hosts LEMO 00 connectors
- Functionality
- simple level conversion
- module should not generate any pulses on output at power-on
- diagnostics via I2C bus on VME
- pulses detected (functionality like LEDs on front-panel)
- functionality like Timing Surveillance Module
(TSM)
would be nice to have
- TSM has resolution of 50 ns
Other information
- currently 450 modules with 8 channels are installed at CERN. Some modules have 16 outputs
- verify to see if possible to generate a wired-OR with two outputs
(Blocking level).
- if not possible, may use "boite a diodes".
Open questions
- what are the requirements on the input pulse width?
- loop-through usage may give signals with heavy reflections, notably
when used with TTL level input
- to be verified and see if other solutions may be practical (e.g. switches grouping outputs together instead of physical loop-through)
- always 2 input, 2 outputs?
- or can have combinations like 1 in, 3 out and other channels 1 in, 2 out?
- if the pulse passes through the FPGA, is the additional jitter/delay a problem?
References
Erik van der Bij - 22 July 2011