[testbench] added top-level testbench basis
It is based on the testbench in conv-ttl-blo-gw/sim/Release and includes - top-level (testbench.vhd) with DUT and i2c facilites (next) - i2c_bus_model.vhd to connect DUT with i2c_master_and_driver - i2c_master_and_driver that allows access to DUT's register via i2c - read_i2c procedures to easily use the driver (write_i2c semi-ready)
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sim/top_level/Manifest.py
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sim/top_level/run.do
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sim/top_level/testbench.vhd
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